NXP Semiconductors MC9S12XS128, Reference Manual

Page: 37 / 739

De
vice Over
vie
w S12XS F
amil
y
S12XS F
amil
y Ref
erence Man
ual, Re
v
. 1.13
F
reescale Semiconductor
37
55 39 31 PE1 IRQ — — — V
DDX
PUCR Up Port E Input, maskable
interrupt
56 40 32 PE0 XIRQ — — — V
DDX
PUCR Up Port E Input, non-
maskable interrupt
57 41 33 PA0 — — — — V
DDX
PUCR Disabled Port A I/O
58 42 34 PA1 — — — — V
DDX
PUCR Disabled Port A I/O
59 43 35 PA2 — — — — V
DDX
PUCR Disabled Port A I/O
60 44 36 PA3 — — — — V
DDX
PUCR Disabled Port A I/O
61 45 - PA4 — — — — V
DDX
PUCR Disabled Port A I/O
62 46 - PA5 — — — — V
DDX
PUCR Disabled Port A I/O
63 47 - PA6 — — — — V
DDX
PUCR Disabled Port A I/O
64 48 - PA7 — — — — V
DDX
PUCR Disabled Port A I/O
65 49 37 VDD — — — — — — — —
66 50 38 VSS2 — — — — — — — —
67 51 39 PAD00 AN00 — — — V
DDA
PER1AD Disabled Port AD I/O,
analog input of ATD
68 - - PAD08 AN08 — — — V
DDA
PER0AD Disabled Port AD I/O,
analog input of ATD
69 52 40 PAD01 AN01 — — — V
DDA
PER1AD Disabled Port AD I/O,
analog input of ATD
70 - - PAD09 AN09 — — — V
DDA
PER0AD Disabled Port AD I/O,
analog input of ATD
71 53 41 PAD02 AN02 — — — V
DDA
PER1AD Disabled Port AD I/O,
analog input of ATD
Table 1-6. Pin-Out Summary
1
(continued)
Package Terminal Function
Power
Supply
Internal Pull
Resistor
Description
LQFP
112
QFP
80
LQFP
64
Pin
2nd
Func.
3rd
Func.
4th
Func.
5th
Func.
CTRL
Reset
State