NXP Semiconductors MC9S12XS128, Reference Manual

Page: 374 / 739

Pulse-Width Modulator (S12PWM8B8CV1)
S12XS Family Reference Manual, Rev. 1.13
374 Freescale Semiconductor
Read: Anytime
Write: Anytime
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
s
Module Base + 0x0003
7 6 5 4 3 2 1 0
R 0
PCKB2 PCKB1 PCKB0
0
PCKA2 PCKA1 PCKA0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 13-6. PWM Prescale Clock Select Register (PWMPRCLK)
Table 13-4. PWMPRCLK Field Descriptions
Field Description
6–4
PCKB[2:0]
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or
7. These three bits determine the rate of clock B, as shown in
Table 13-5 .
2–0
PCKA[2:0]
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channels 0, 1, 4 or
5. These three bits determine the rate of clock A, as shown in
Table 13-6 .
Table 13-5. Clock B Prescaler Selects
PCKB2 PCKB1 PCKB0 Value of Clock B
0 0 0 Bus clock
0 0 1 Bus clock / 2
0 1 0 Bus clock / 4
0 1 1 Bus clock / 8
1 0 0 Bus clock / 16
1 0 1 Bus clock / 32
1 1 0 Bus clock / 64
1 1 1 Bus clock / 128
Table 13-6. Clock A Prescaler Selects
PCKA2 PCKA1 PCKA0 Value of Clock A
0 0 0 Bus clock
0 0 1 Bus clock / 2
0 1 0 Bus clock / 4
0 1 1 Bus clock / 8
1 0 0 Bus clock / 16
1 0 1 Bus clock / 32
1 1 0 Bus clock / 64
1 1 1 Bus clock / 128