NXP Semiconductors MC9S12XS128 Reference Manual Download | Manualshive

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S12X Debug (S12XDBGV3) Module

S12XS Family Reference Manual, Rev. 1.13

214

Freescale Semiconductor

6.3.2.8.5

Debug Comparator Data High Register (DBGXDH)

Read: Anytime. See

for visible register encoding.

Write: If DBG not armed. See

for visible register encoding.

6.3.2.8.6

Debug Comparator Data Low Register (DBGXDL)

Read: Anytime. See

for visible register encoding.

Write: If DBG not armed. See

for visible register encoding.

Address: 0x002C

7

6

5

4

3

2

1

0

R

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

W

Reset

0

0

0

0

0

0

0

0

Figure 6-18. Debug Comparator Data High Register (DBGXDH)

Table 6-32. DBGXAH Field Descriptions

Field

Description

7–0

Bits[15:8]

Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one

Address: 0x002D

7

6

5

4

3

2

1

0

R

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

W

Reset

0

0

0

0

0

0

0

0

Figure 6-19. Debug Comparator Data Low Register (DBGXDL)

Table 6-33. DBGXDL Field Descriptions

Field

Description

7–0

Bits[7:0]

Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected
comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one

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Summary of Contents for MC9S12XS128

Page 1: ...HCS12 Microcontrollers freescale com MC9S12XS256 Reference Manual Covers MC9S12XS Family MC9S12XS256 MC9S12XS128 MC9S12XS64 MC9S12XS256RMV1 Rev 1 13 08 2012 ...

Page 2: ... Description November 2010 1 11 Updated Chapter 3 Memory Mapping Control S12XMMCV4 Updated Chapter 11 Freescale s Scalable Controller Area Network S12MSCANV3 Updated Chapter 14 Serial Communication Interface S12SCIV5 Updated footnotes on table 1 2 Updated note in Appendix F Ordering Information Jul 2011 1 12 Corrected API accuracy in feature list Corrected name of pin 27 in 80QFP pinout PE5 PE4 Up...

Page 3: ... s Scalable Controller Area Network S12MSCANV3 295 Chapter 12 Periodic Interrupt Timer S12PIT24B4CV1 349 Chapter 13 Pulse Width Modulator S12PWM8B8CV1 365 Chapter 14 Serial Communication Interface S12SCIV5 397 Chapter 15 Serial Peripheral Interface S12SPIV5 435 Chapter 16 Timer Module TIM16B8CV2 461 Chapter 17 Voltage Regulator S12VREGL3V3V1 489 Chapter 18 256 KByte Flash Module S12XFTMR256K1V1 50...

Page 4: ...S12XS Family Reference Manual Rev 1 13 4 Freescale Semiconductor ...

Page 5: ...1 3 System Clock Description 48 1 4 Modes of Operation 49 1 4 1 Chip Configuration Summary 49 1 4 2 Power Modes 50 1 4 3 Freeze Mode 51 1 5 Security 51 1 6 Resets and Interrupts 51 1 6 1 Resets 51 1 6 2 Vectors 51 1 6 3 Effects of Reset 53 1 7 ATD0 Configuration 55 1 7 1 External Trigger Input Connection 55 1 7 2 ATD0 Channel 17 Connection 55 1 8 VREG Configuration 55 1 8 1 Temperature Sensor Conf...

Page 6: ...Port T Reduced Drive Register RDRT 87 2 3 22 Port T Pull Device Enable Register PERT 88 2 3 23 Port T Polarity Select Register PPST 88 2 3 24 PIM Reserved Register 89 2 3 25 Port T Routing Register PTTRR 89 2 3 26 Port S Data Register PTS 91 2 3 27 Port S Input Register PTIS 92 2 3 28 Port S Data Direction Register DDRS 93 2 3 29 Port S Reduced Drive Register RDRS 94 2 3 30 Port S Pull Device Enab...

Page 7: ...vice Enable Register PERJ 114 2 3 63 Port J Polarity Select Register PPSJ 115 2 3 64 Port J Interrupt Enable Register PIEJ 115 2 3 65 Port J Interrupt Flag Register PIFJ 116 2 3 66 Port AD0 Data Register 0 PT0AD0 116 2 3 67 Port AD0 Data Register 1 PT1AD0 117 2 3 68 Port AD0 Data Direction Register 0 DDR0AD0 117 2 3 69 Port AD0 Data Direction Register 1 DDR1AD0 118 2 3 70 Port AD0 Reduced Drive Re...

Page 8: ...l Description 154 4 3 Memory Map and Register Definition 155 4 3 1 Module Memory Map 155 4 3 2 Register Descriptions 156 4 4 Functional Description 161 4 4 1 S12X Exception Requests 162 4 4 2 Interrupt Prioritization 162 4 4 3 XGATE Requests 163 4 4 4 Priority Decoders 163 4 4 5 Reset Exception Requests 164 4 4 6 Exception Priority 164 4 5 Initialization Application Information 165 4 5 1 Initializ...

Page 9: ...XDBGV3 Module 6 1 Introduction 195 6 1 1 Glossary 195 6 1 2 Overview 196 6 1 3 Features 196 6 1 4 Modes of Operation 197 6 1 5 Block Diagram 198 6 2 External Signal Description 198 6 3 Memory Map and Registers 198 6 3 1 Module Memory Map 198 6 3 2 Register Descriptions 199 6 4 Functional Description 215 6 4 1 S12XDBG Operation 216 6 4 2 Comparator Modes 216 6 4 3 Trigger Modes 220 6 4 4 State Sequ...

Page 10: ...wer Options 260 8 5 Resets 262 8 5 1 Description of Reset Operation 263 8 6 Interrupts 265 8 6 1 Description of Interrupt Operation 266 Chapter 9 Pierce Oscillator S12XOSCLCPV2 9 1 Introduction 267 9 1 1 Features 267 9 1 2 Modes of Operation 267 9 1 3 Block Diagram 268 9 2 External Signal Description 268 9 2 1 VDDPLL and VSSPLL Operating and Ground Voltage Pins 268 9 2 2 EXTAL and XTAL Input and O...

Page 11: ... 3 Features 297 11 1 4 Modes of Operation 297 11 2 External Signal Description 298 11 2 1 RXCAN CAN Receiver Input Pin 298 11 2 2 TXCAN CAN Transmitter Output Pin 298 11 2 3 CAN System 298 11 3 Memory Map and Register Definition 299 11 3 1 Module Memory Map 299 11 3 2 Register Descriptions 301 11 3 3 Programmer s Model of Message Storage 320 11 4 Functional Description 331 11 4 1 General 331 11 4 ...

Page 12: ... 365 13 1 1 Features 365 13 1 2 Modes of Operation 366 13 1 3 Block Diagram 366 13 2 External Signal Description 366 13 2 1 PWM7 PWM Channel 7 367 13 2 2 PWM6 PWM Channel 6 367 13 2 3 PWM5 PWM Channel 5 367 13 2 4 PWM4 PWM Channel 4 367 13 2 5 PWM3 PWM Channel 3 367 13 2 6 PWM3 PWM Channel 2 367 13 2 7 PWM3 PWM Channel 1 367 13 2 8 PWM3 PWM Channel 0 367 13 3 Memory Map and Register Definition 367...

Page 13: ...lication Information 431 14 5 1 Reset Initialization 431 14 5 2 Modes of Operation 431 14 5 3 Interrupt Operation 432 14 5 4 Recovery from Wait Mode 434 14 5 5 Recovery from Stop Mode 434 Chapter 15 Serial Peripheral Interface S12SPIV5 15 1 Introduction 435 15 1 1 Glossary of Terms 435 15 1 2 Features 435 15 1 3 Modes of Operation 435 15 1 4 Block Diagram 436 15 2 External Signal Description 437 1...

Page 14: ...and Output Compare Channel 1 Pin 466 16 2 8 IOC0 Input Capture and Output Compare Channel 0 Pin 466 16 3 Memory Map and Register Definition 466 16 3 1 Module Memory Map 466 16 3 2 Register Descriptions 466 16 4 Functional Description 483 16 4 1 Prescaler 484 16 4 2 Input Capture 485 16 4 3 Output Compare 485 16 4 4 Pulse Accumulator 486 16 4 5 Event Counter Mode 486 16 4 6 Gated Time Accumulation ...

Page 15: ...TD High Temperature Detect 503 17 4 7 Regulator Control CTRL 503 17 4 8 Autonomous Periodical Interrupt API 503 17 4 9 Resets 504 17 4 10Description of Reset Operation 504 17 4 11Interrupts 504 Chapter 18 256 KByte Flash Module S12XFTMR256K1V1 18 1 Introduction 507 18 1 1 Glossary 508 18 1 2 Features 508 18 1 3 Block Diagram 509 18 2 External Signal Description 510 18 3 Memory Map and Registers 51...

Page 16: ...U in Special Single Chip Mode using BDM 605 19 5 3 Mode and Security Effects on Flash Command Availability 606 19 6 Initialization 606 Chapter 20 64 KByte Flash Module S12XFTMR64K1V1 20 1 Introduction 607 20 1 1 Glossary 608 20 1 2 Features 608 20 1 3 Block Diagram 610 20 2 External Signal Description 610 20 3 Memory Map and Registers 611 20 3 1 Module Memory Map 611 20 3 2 Register Descriptions 6...

Page 17: ... A 2 2 Factors Influencing Accuracy 673 A 2 3 ATD Accuracy 675 A 3 NVM Flash 679 A 3 1 Timing Parameters 679 A 3 2 NVM Reliability Parameters 683 A 4 Voltage Regulator 685 A 5 Output Loads 686 A 5 1 Resistive Loads 686 A 5 2 Capacitive Loads 686 A 5 3 Chip Power up and Voltage Drops 686 A 6 Reset Oscillator and PLL 688 A 6 1 Startup 688 A 6 2 Oscillator 690 A 6 3 Phase Locked Loop 691 A 7 MSCAN 69...

Page 18: ...ommended PCB Layout 710 C 1 3 64 Pin LQFP Recommended PCB Layout 711 Appendix D Derivative Differences D 1 Memory Sizes and Package Options S12XS family 712 Appendix E Detailed Register Address Map E 1 Detailed Register Map 713 Appendix F Ordering Information F 1 Ordering Information 735 ...

Page 19: ...tages currently enjoyed by users of Freescale s existing 16 bit S12 and S12X MCU families Like members of other S12X families the S12XS family runs 16 bit wide accesses without wait states for all peripherals and memories The S12XS family is available in 112 pin LQFP 80 pin QFP 64 pin LQFP package options and maintains a high level of pin compatibility with the S12XE family In addition to the I O ...

Page 20: ...trol Pierce oscillator utilizing a 4MHz to 16MHz crystal Good noise immunity Full swing Pierce option utilizing a 2MHz to 40MHz crystal Transconductance sized for optimum start up margin for typical crystals IPLL Internally filtered frequency modulated phase locked loop clock generation No external components required Configurable option to spread spectrum for reduced EMC radiation frequency modul...

Page 21: ...O MSCAN 1 M bit per second CAN 2 0 A B software compatible module 1 Mbit per second CAN 2 0 A B software compatible module Standard and extended data frames 0 8 bytes data length Programmable bit rate up to 1 Mbps Five receive buffers with FIFO storage scheme Three transmit buffers with internal prioritization Flexible identifier acceptance filter programmable as 2 x 32 bit 4 x 16 bit 8 x 8 bit Wa...

Page 22: ...ormat Selectable IrDA 1 4 return to zero inverted RZI format with programmable pulse widths 13 bit baud rate selection Programmable character length Programmable polarity for transmitter and receiver Receive wakeup on active edge Break detect and transmit collision detect supporting LIN On Chip Voltage Regulator Two parallel linear voltage regulators with bandgap reference Low voltage detect LVD w...

Page 23: ...ulator and I O allow optimized EMC filtering 40MHz maximum CPU bus frequency Ambient temperature range 40 C to 125 C Temperature Options 40 C to 85 C 40 C to 105 C 40 C to 125 C 1 1 2 Modes of Operation Operating modes Normal single chip mode Special single chip mode with active background debug mode NOTE This chip family does not support external bus modes Low power modes System stop modes Pseudo...

Page 24: ...ator PWM PIT PB 7 0 PTB PA 7 0 PTA PK 7 5 0 PTK XIRQ IRQ ECLK PE4 PE3 PE2 PE1 PE0 PE7 PE6 PE5 PTE VDDF 64 128 256 Kbytes Flash CPU12X Amplitude Controlled Low Power Pierce or Full drive Pierce Oscillator COP Watchdog PLL with Frequency Modulation option Debug Module 4 address breakpoints 2 data breakpoints 512 Byte Trace Buffer Reset Generation and Test Entry RXD TXD SCI1 Asynchronous Serial IF RX...

Page 25: ...tegration module 2 0x0034 0x003F ECRG clock and reset generator 12 0x0040 0x006F TIM timer module 48 0x0070 0x00C7 Reserved 88 0x00C8 0x00CF SCI0 serial communications interface 8 0x00D0 0x00D7 SCI1 serial communications interface 8 0x00D8 0x00DF SPI0 serial peripheral interface 8 0x00E0 0x00FF Reserved 32 0x0100 0x0113 FTMR control registers 20 0x0114 0x011F Reserved 12 0x0120 0x012F INT interrup...

Page 26: ...is reserved for future use Writing to these locations has no effect Read access to these locations returns zero 1 1 5 Address Mapping Figure 1 2 shows S12XS CPU and BDM local address translation to the global memory map It indicates also the location of the internal resources in the memory map 0x0368 0x07FF Reserved 1176 Table 1 1 Device Register Memory Map continued Address Module Size Bytes ...

Page 27: ...F RPAGE PPAGE 0x3F_FFFF CPU and BDM Local Memory Map Global Memory Map FLASH FLASHSIZE Unimplemented FLASH 0xFFFF Vectors 0xC000 0x8000 Unpaged 0x4000 0x1000 0x0000 16K FLASH window 0x2000 0x0800 8K RAM 4K RAM window 2K REGISTERS 16K FLASH Unpaged 16K FLASH 2K REGISTERS Unimplemented RAM Unimplemented Space RAM_LOW FLASH_LOW RAMSIZE DF_HIGH DFLASH Resources Reserved EPAGE 1K DFLASH window 0x0C00 ...

Page 28: ... is a word located in a flash information row at 0x40_00E8 The version ID number indicates a specific version of internal NVM variables used to patch NVM errata The default is no patch 0xFFFF Device FLASH_LOW SIZE PPAGE1 1 Number of 16K pages addressable via PPAGE register RAM_LOW SIZE RPAGE2 2 Number of 4K pages addressing the RAM via PPAGE register DF_HIGH SIZE EPAGE3 3 Number of 1K pages addres...

Page 29: ...signal properties and detailed discussion of signals It is built from the signal description sections of the individual IP blocks on the device 1 2 1 Device Pinout The XS family of devices offers pin compatible packaged devices to assist with system development and accommodate expansion of the application The S12XS family devices are offered in the following package options 112 pin LQFP 80 pin QFP...

Page 30: ...C2 PWM2 KWP2 PP2 IOC1 PWM1 KWP1 PP1 RXD1 IOC0 PWM0 KWP0 PP0 PK3 PK2 PK1 PK0 IOC0 PT0 IOC1 PT1 IOC2 PT2 IOC3 PT3 VDDF VSS1 PWM4 IOC4 PT4 VREG_API PWM5 IOC5 PT5 PWM6 IOC6 PT6 PWM7 IOC7 PT7 PK5 PK4 KWJ1 PJ1 KWJ0 PJ0 MODC BKGD PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 KWH7 PH7 KWH6 PH6 KWH5 PH5 KWH4 PH4 XCLKS ECLKX2 PE7 PE6 PE5 ECLK PE4 VSSX2 VDDX2 RESET VDDR VSS3 VSSPLL EXTAL XTAL VDDPLL KWH3 PH3 KWH2 PH2 KWH1...

Page 31: ...DDR VSS3 VSSPLL EXTAL XTAL VDDPLL PE3 PE2 IRQ PE1 XIRQ PE0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 S12XS Family 80QFP PWM3 KWP3 PP3 TXD1 IOC2 PWM2 KWP2 PP2 IOC1 PWM1 KWP1 PP1 RXD1 IOC0 PWM0 KWP0 PP0 IOC0 PT0 IOC1 PT1 IOC2 PT2 IOC3 PT3 VDDF VSS1 PWM4 IOC4 PT4 VREG_API PWM5 IOC5 PT5 PWM6 IOC6 PT6 PWM7 IOC7 PT7 MODC BKGD ...

Page 32: ...07 PAD06 AN06 PAD05 AN05 PAD04 AN04 PAD03 AN03 PAD02 AN02 PAD01 AN01 PAD00 AN00 VSS2 VDD PA3 PA2 PA1 PA0 PB5 PB6 PB7 XCLKS ECLKX2 PE7 ECLK PE4 VSSX2 VDDX2 RESET VDDR VSS3 VSSPLL EXTAL XTAL VDDPLL IRQ PE1 XIRQ PE0 PWM3 KWP3 PP3 TXD1 IOC2 PWM2 KWP2 PP2 IOC1 PWM1 KWP1 PP1 RXD1 IOC0 PWM0 KWP0 PP0 IOC0 PT0 IOC1 PT1 IOC2 PT2 IOC3 PT3 VDDF VSS1 PWM4 IOC4 PT4 VREG_API PWM5 IOC5 PT5 PWM6 IOC6 PT6 PWM7 IOC7...

Page 33: ...112 LQFP 80 QFP 64 LQFP Port AD ADC Channels 16 16 8 8 8 8 Port A pins 8 8 4 Port B pins 8 8 4 Port E pins inc IRQ XIRQ input only 8 8 4 Port H 8 0 0 Port J 4 2 0 Port K 7 0 0 Port M 8 6 6 Port P 8 7 6 Port S 8 4 4 Port T 8 8 8 Sum of Ports 91 59 44 I O Power Pairs VDDX VSSX 2 2 2 2 2 2 Table 1 5 Peripheral Port Routing Options1 1 X denotes reset condition O denotes a possible rerouting under soft...

Page 34: ...PSP Disabled Port P I O interrupt PWM TIMchannel TXD of SCI1 3 3 3 PP1 KWP1 PWM1 IOC1 VDDX PERP PPSP Disabled Port P I O interrupt PWM TIM channel 4 4 4 PP0 KWP0 PWM0 IOC0 RXD1 VDDX PERP PPSP Disabled Port P I O interrupt PWM TIM channel RXD of SCI1 5 PK3 VDDX PUCR Up Port K I O 6 PK2 VDDX PUCR Up Port K I O 7 PK1 VDDX PUCR Up Port K I O 8 PK0 VDDX PUCR Up Port K I O 9 5 5 PT0 IOC0 VDDX PERT PPST ...

Page 35: ...debug 24 16 16 PB0 VDDX PUCR Disabled Port B I O 25 17 PB1 VDDX PUCR Disabled Port B I O 26 18 PB2 VDDX PUCR Disabled Port B I O 27 19 PB3 VDDX PUCR Disabled Port B I O 28 20 PB4 VDDX PUCR Disabled Port B I O 29 21 17 PB5 VDDX PUCR Disabled Port B I O 30 22 18 PB6 VDDX PUCR Disabled Port B I O 31 23 19 PB7 VDDX PUCR Disabled Port B I O 32 PH7 KWH7 VDDX PERH PPSH Disabled Port H I O interrupt 33 PH...

Page 36: ...31 25 VDDR 44 32 26 VSS3 45 33 27 VSSPLL 46 34 28 EXTAL VDDPLL NA NA Oscillator pin 47 35 29 XTAL VDDPLL NA NA Oscillator pin 48 36 30 VDDPLL 49 PH3 KWH3 VDDX PERH PPSH Disabled Port H I O interrupt 50 PH2 KWH2 VDDX PERH PPSH Disabled Port H I O interrupt 51 PH1 KWH1 VDDX PERH PPSH Disabled Port H I O interrupt 52 PH0 KWH0 VDDX PERH PPSH Disabled Port H I O interrupt 53 37 PE3 VDDX PUCR Up Port E ...

Page 37: ...d Port A I O 63 47 PA6 VDDX PUCR Disabled Port A I O 64 48 PA7 VDDX PUCR Disabled Port A I O 65 49 37 VDD 66 50 38 VSS2 67 51 39 PAD00 AN00 VDDA PER1AD Disabled Port AD I O analog input of ATD 68 PAD08 AN08 VDDA PER0AD Disabled Port AD I O analog input of ATD 69 52 40 PAD01 AN01 VDDA PER1AD Disabled Port AD I O analog input of ATD 70 PAD09 AN09 VDDA PER0AD Disabled Port AD I O analog input of ATD ...

Page 38: ...D05 AN05 VDDA PER1AD Disabled Port AD I O analog input of ATD 78 PAD13 AN13 VDDA PER0AD Disabled Port AD I O analog input of ATD 79 57 45 PAD06 AN06 VDDA PER1AD Disabled Port AD I O analog input of ATD 80 PAD14 AN14 VDDA PER0AD Disabled Port AD I O analog input of ATD 81 58 46 PAD07 AN07 VDDA PER1AD Disabled Port AD I O analog input of ATD 82 PAD15 AN15 VDDA PER0AD Disabled Port AD I O analog inpu...

Page 39: ...S Up Port S I O SS of SPI0 97 67 54 TEST N A RESET pin DOWN Test input 98 68 PJ7 KWJ7 VDDX PERJ PPSJ Up Port J I O interrupt 99 69 PJ6 KWJ6 VDDX PERJ PPSJ Up Port J I O interrupt 100 70 55 PM5 SCK0 VDDX PERM PPSM Disabled Port M I O SCK of SPI0 101 71 56 PM4 MOSI0 VDDX PERM PPSM Disabled Port M I O MOSI of SPI0 102 72 57 PM3 SS0 VDDX PERM PPSM Disabled Port M I O SS of SPI0 103 73 58 PM2 MISO0 VDD...

Page 40: ... 64 PP5 KWP5 PWM5 VDDX PERP PPSP Disabled Port P I O interrupt PWM channel 112 80 PP4 KWP4 PWM4 VDDX PERP PPSP Disabled Port P I O interrupt PWM channel 1 Table shows a superset of pin functions Not all functions are available on all derivatives 2 For compatibility to XE family 3 VRL and VSSA share single pin on 64 package option Table 1 6 Pin Out Summary1 continued Package Terminal Function Power...

Page 41: ...ntrol signal It acts as an input to initialize the MCU to a known start up state As an output it is driven low to indicate when any internal MCU reset source triggers The RESET pin has an internal pull up device 1 2 3 3 TEST Test Pin This input only pin is reserved for factory test This pin has a pull down device NOTE The TEST pin must be tied to VSS in all applications 1 2 3 4 BKGD MODC Backgroun...

Page 42: ...r output pins 1 2 3 12 PE1 IRQ Port E Input Pin 1 PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from stop or wait mode 1 2 3 13 PE0 XIRQ Port E Input Pin 0 PE0 is a general purpose input pin and the non maskable interrupt request input that provides a means of applying asynchro...

Page 43: ...ode or slave output pin during slave mode MISO for the serial peripheral interface 0 SPI0 1 2 3 23 PM1 TXCAN0 TXD1 Port M I O Pin 1 PM1 is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the scalable controller area network controller 0 CAN0 It can be configured as the transmit pin TXD of serial communication interface 1 SCI1 1 2 3 24 PM0 RXCAN0 RXD1 Port M ...

Page 44: ...7 SS0 Port S I O Pin 7 PS7 is a general purpose input or output pin It can be configured as the slave select pin SS of the serial peripheral interface 0 SPI0 1 2 3 31 PS6 SCK0 Port S I O Pin 6 PS6 is a general purpose input or output pin It can be configured as the serial clock pin SCK of the serial peripheral interface 0 SPI0 1 2 3 32 PS5 MOSI0 Port S I O Pin 5 PS5 is a general purpose input or o...

Page 45: ... 3 40 PT4 IOC4 PWM4 Port T I O Pin 4 PT4 is a general purpose input or output pin It can be configured as timer TIM channel 4 or pulse width modulator PWM output 4 1 2 3 41 PT 3 0 IOC 3 0 Port T I O Pin 3 0 PT 3 0 are a general purpose input or output pins They can be configured as timer TIM channels 3 0 1 2 4 Power Supply Pins S12XS Family power and ground pins are described below Because fast si...

Page 46: ...ply Pins for PLL These pins provide operating voltage and ground for the oscillator and the phased locked loop The voltage supply of nominally 1 8 V is derived from the internal voltage regulator This allows the supply voltage to the oscillator and PLL to be bypassed independently This voltage is generated by the internal voltage regulator No static external loading of these pins is permitted Tabl...

Page 47: ...DPLL 1 8 V Provides operating voltage and ground for the phased locked loop This allows the supply voltage to the PLL to be bypassed independently Internal power and ground generated by internal regulator VSSPLL 0 V Table 1 7 Power and Ground Connection Summary Mnemonic Nominal Voltage Description ...

Page 48: ... Consult the S12XECRG section for details on clock generation NOTE The XS family uses the XE family clock and reset generator module Therefore all CRG references are related to S12XECRG Figure 1 6 Clock Connections The system clock can be supplied in several ways enabling a range of system operating frequencies to be supported The on chip phase locked loop PLL the PLL self clocking the oscillator ...

Page 49: ... of clock edges within a defined time window to insure that the clock is running The checker can be invoked following specific events such as on wake up or clock monitor failure 1 4 Modes of Operation The MCU can operate in different modes These are described in 1 4 1 Chip Configuration Summary The MCU can operate in different power modes to facilitate power saving when full system performance is ...

Page 50: ...mand is being processed then the system clocks continue running until NVM activity is completed If a non masked interrupt occurs within this time then the system does not effectively enter stop mode although the STOP instruction has been executed 1 4 2 2 Full Stop Mode The oscillator is stopped in this mode By default all clocks are switched off and all counters and dividers remain frozen The Auto...

Page 51: ...ription of the security features refer to the S12XS9SEC section 1 6 Resets and Interrupts Consult the CPU12 CPU12X Reference Manual and the S12XINT section for information on exception processing NOTE When referring to the S12XINT section please be aware that the XS family neither features an XGATE nor an MPU module 1 6 1 Resets Resets are explained in detail in the Clock Reset Generator S12XECRG ...

Page 52: ...3I No Yes Vector base E6 TIM timer channel 4 I bit TIE C4I No Yes Vector base E4 TIM timer channel 5 I bit TIE C5I No Yes Vector base E2 TIM timer channel 6 I bit TIE C6I No Yes Vector base E0 TIM timer channel 7 I bit TIE C7I No Yes Vector base DE TIM timer overflow I bit TSRC2 TOF No Yes Vector base DC TIM Pulse accumulator A overflow I bit PACTL PAOVI No Yes Vector base DA TIM Pulse accumulator...

Page 53: ...rgency shutdown I bit PWMSDN PWMIE No Yes Vector base 8A to Vector base 82 Reserved Vector base 80 Low voltage interrupt LVI I bit VREGCTRL LVIE No Yes Vector base 7E Autonomous periodical interrupt API I bit VREGAPICTRL APIE Yes Yes Vector base 7C High Temperature Interrupt HTI I bit VREGHTCL HTIE No Yes Vector base 7A Periodic interrupt timer channel 0 I bit PITINTE PINTE0 No Yes Vector base 78 ...

Page 54: ...uaranteed 1 6 3 3 I O Pins Refer to the PIM section for reset configurations of all peripheral module ports 1 6 3 4 Memory The RAM arrays are not initialized out of reset 1 6 3 5 COP Configuration The COP time out rate bits CR 2 0 and the WCOP bit in the COPCTL register are loaded from the Flash register FOPT See Table 1 11 and Table 1 12 for coding The FOPT register is loaded from the Flash confi...

Page 55: ...ternal voltage regulator is not supported The API trimming register APITR is loaded from the Flash IFR option field at global address 0x40_00F0 bits 5 0 during the reset sequence Currently factory programming of this IFR range is not supported Read access to reserved VREG register space returns 0 Write accesses have no effect This device does not support access abort of reserved VREG register spac...

Page 56: ... which controls whether a crystal in combination with the internal loop controlled low power Pierce oscillator is used or whether full swing Pierce oscillator external clock circuitry is used The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing This is the case for Power on reset or low voltage reset Clock monitor reset Any reset while...

Page 57: ...ibed reset cases Figure 1 7 Loop Controlled Pierce Oscillator Connections XCLKS 1 Figure 1 8 Full Swing Pierce Oscillator Connections XCLKS 0 Figure 1 9 External Clock Connections XCLKS 0 MCU EXTAL XTAL VSSPLL Crystal or Ceramic Resonator C2 C1 MCU EXTAL XTAL RS RB VSSPLL Crystal or Ceramic Resonator C2 C1 RB 1MΩ RS specified by crystal vendor MCU EXTAL XTAL CMOS Compatible External Oscillator Not...

Page 58: ...Device Overview S12XS Family S12XS Family Reference Manual Rev 1 13 58 Freescale Semiconductor ...

Page 59: ...ociated with 2 SCI module and 1 SPI module Port M associated with 1 MSCAN Port P connected to the PWM inputs can be used as an external interrupt source Port H and J used as general purpose I O inputs can be used as an external interrupt source Port AD associated with one 16 channel ATD module Most I O pins can be configured by register bits to select data direction and drive strength to enable an...

Page 60: ...rts T S M P H J and AD on per pin basis Single control register to enable disable reduced output drive on Ports A B E and K on per port basis Control registers to enable disable open drain wired or mode on Ports S and M Interrupt flag register for pin interrupts on Ports P H and J Control register to configure IRQ pin operation Routing registers to support module port relocation Free running clock...

Page 61: ...KGD I O S12X_BDM communication pin A PA 7 0 GPIO I O General purpose GPIO B PB 7 0 GPIO I O General purpose GPIO E PE 7 XCLKS 2 I External clock selection input during RESET GPIO ECLKX2 O Free running clock at core clock rate ECLK x 2 GPIO I O General purpose PE 6 5 GPIO I O General purpose PE 4 ECLK O Free running clock at bus clock rate or programmable down scaled bus clock GPIO I O General purp...

Page 62: ...ipheral Interface 0 slave select output in master mode input in slave mode or master mode GPIO GPIO I O General purpose PS6 SCK0 I O Serial Peripheral Interface 0 serial clock pin GPIO I O General purpose PS5 MOSI0 I O Serial Peripheral Interface 0 master out slave in pin GPIO I O General purpose PS4 MISO0 I O Serial Peripheral Interface 0 master in slave out pin GPIO I O General purpose PS3 TXD1 ...

Page 63: ...l Interface 0 slave select output in master mode input in slave mode or master mode GPIO I O General purpose PM2 MISO0 I O Serial Peripheral Interface 0 master in slave out pin GPIO I O General purpose PM1 TXCAN0 O MSCAN0 transmit pin TXD1 O Serial Communication Interface 1 transmit pin GPIO I O General purpose PM0 RXCAN0 I MSCAN0 receive pin RXD1 I Serial Communication Interface 1 receive pin GPI...

Page 64: ... General purpose with interrupt PP1 PWM1 O Pulse Width Modulator channel 1 IOC1 I O Timer Channel 1 GPIO KWP1 I O General purpose with interrupt PP0 PWM0 O Pulse Width Modulator channel 0 IOC0 I O Timer Channel 0 RXD1 I Serial Communication Interface 1 receive pin GPIO KWP0 I O General purpose with interrupt H PH 7 0 GPIO KWH 7 0 I O General purpose with interrupt GPIO J PJ 7 6 GPIO KWJ 7 6 I O Ge...

Page 65: ...d R 0x00 2 3 7 2 77 E 0x0008 PORTE Port E Data Register R W1 0x00 2 3 8 2 77 0x0009 DDRE Port E Data Direction Register R W1 0x00 2 3 9 2 78 0x000A 0x000B Non PIM address range2 A B E K 0x000C PUCR Pull up Control Register R W1 0xD0 2 3 10 2 79 0x000D RDRIV Reduced Drive Register R W1 0x00 2 3 11 2 80 0x000E 0x001B Non PIM address range2 E 0x001C ECLKCTL ECLK Control Register R W1 0b3 100_0000 2 3...

Page 66: ...ister R W 0x00 2 3 32 2 95 0x024F PIM Reserved R 0x00 2 3 33 2 96 M 0x0250 PTM Port M Data Register R W 0x00 2 3 34 2 96 0x0251 PTIM Port M Input Register R 4 2 3 35 2 98 0x0252 DDRM Port M Data Direction Register R W 0x00 2 3 36 2 98 0x0253 RDRM Port M Reduced Drive Register R W 0x00 2 3 37 2 99 0x0254 PERM Port M Pull Device Enable Register R W 0x00 2 3 38 2 100 0x0255 PPSM Port M Polarity Selec...

Page 67: ...x026D PPSJ Port J Polarity Select Register R W 0x00 2 3 63 2 115 0x026E PIEJ Port J Interrupt Enable Register R W 0x00 2 3 64 2 115 0x026F PIFJ Port J Interrupt Flag Register R W 0x00 2 3 65 2 116 AD 0x0270 PT0AD0 Port AD0 Data Register 0 R W 0x00 2 3 66 2 116 0x0271 PT1AD0 Port AD0 Data Register 1 R W 0x00 2 3 67 2 117 0x0272 DDR0AD0 Port AD0 Data Direction Register 0 R W 0x00 2 3 68 2 117 0x0273...

Page 68: ...RB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W 0x0004 Reserved R 0 0 0 0 0 0 0 0 W 0x0005 Reserved R 0 0 0 0 0 0 0 0 W 0x0006 Reserved R 0 0 0 0 0 0 0 0 W 0x0007 Reserved R 0 0 0 0 0 0 0 0 W 0x0008 PORTE R PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 W 0x0009 DDRE R DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 W 0x000A 0x000B Non PIM Address Range R Non PIM Address Range W 0x000C PUCR R PUPKE BKPUE 0 PUPEE 0 0 PUPBE PUPAE W 0...

Page 69: ...3 PK2 PK1 PK0 W 0x0033 DDRK R DDRK7 0 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 W 0x0034 0x023F Non PIM Address Range R Non PIM Address Range W 0x0240 PTT R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W 0x0241 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W 0x0242 DDRT R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x0243 RDRT R RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 W 0x0244 PERT R P...

Page 70: ... PERS R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W 0x024D PPSS R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W 0x024E WOMS R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W 0x024F Reserved R 0 0 0 0 0 0 0 0 W 0x0250 PTM R PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 W 0x0251 PTIM R PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 W 0x0252 DDRM R DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDR...

Page 71: ...2 RDRP1 RDRP0 W 0x025C PERP R PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W 0x025D PPSP R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W 0x025E PIEP R PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W 0x025F PIFP R PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W 0x0260 PTH R PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 W 0x0261 PTIH R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 W 0x0262 DD...

Page 72: ...C PERJ R PERJ7 PERJ6 0 0 0 0 PERJ1 PERJ0 W 0x026D PPSJ R PPSJ7 PPSJ6 0 0 0 0 PPSJ1 PPSJ0 W 0x026E PIEJ R PIEJ7 PIEJ6 0 0 0 0 PIEJ1 PIEJ0 W 0x026F PIFJ R PIFJ7 PIFJ6 0 0 0 0 PIFJ1 PIFJ0 W 0x0270 PT0AD0 R PT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00 W 0x0271 PT1AD0 R PT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00 W 0x0272 DDR0AD0 R DDR0AD07 DDR0AD06 DDR0AD05 DDR0A...

Page 73: ...either a pull up or pull down device if PE is active 0x0275 RDR1AD0 R RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 W 0x0276 PER0AD0 R PER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00 W 0x0277 PER1AD0 R PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 W 0x0278 Reserved R 0 0 0 0 0 0 0 0 W 0x0279 Reserved R 0 0 0 0 0 0 0 0 W 0x...

Page 74: ... 1 Always 0 on Port A B E K and AD IE2 2 Applicable only on Port P H and J Function Pull Device Interrupt 0 x x 0 x 0 Input Disabled Disabled 0 x x 1 0 0 Input Pull Up Disabled 0 x x 1 1 0 Input Pull Down Disabled 0 x x 0 0 1 Input Disabled Falling edge 0 x x 0 1 1 Input Disabled Rising edge 0 x x 1 0 1 Input Pull Up Falling edge 0 x x 1 1 1 Input Pull Down Rising edge 1 0 0 x x 0 Output full driv...

Page 75: ...egister bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read Address 0x0001 PRR Access User read write1 1 Read Anytime the data source depends on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 W Reset 0 0 0 0 0 0 0 0 Figure 2 2 Port B...

Page 76: ... Field Description 7 0 DDRA Port A Data Direction This bit determines whether the associated pin is an input or output 1 Associated pin configured as output 0 Associated pin configured as input Address 0x0003 PRR Access User read write1 1 Read Anytime the data source depends on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W Reset 0 0 0 0 ...

Page 77: ... 0 0 0 Unimplemented or Reserved Figure 2 5 PIM Reserved Registers Address 0x0008 PRR Access User read write1 1 Read Anytime the data source depends on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 W Altern Function XCLKS ECLK IRQ XIRQ ECLKX2 Reset 0 0 0 0 0 0 2 2 These registers are reset to zero Two bus clock cycles after reset release the register valu...

Page 78: ... If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read 4 PE Port E general purpose input output data Data Register ECLK output When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the a...

Page 79: ... Field Descriptions Field Description 7 PUPKE Port K Pull up Enable Enable pull up devices on all port input pins This bit configures whether a pull up device is activated on all associated port input pins If a pin is used as output this bit has no effect 1 Pull up device enabled 0 Pull up device disabled 6 BKPUE BKGD pin pull up Enable Enable pull up device on pin This bit configures whether a pu...

Page 80: ...s on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R RDPK 0 0 RDPE 0 0 RDPB RDPA W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 2 9 Ports ABEK Reduced Drive Register RDRIV Table 2 11 RDRIV Register Field Descriptions Field Description 7 RDPK Port K reduced drive Select reduced drive for output port This bit configures the drive strength of all associated port output pins as eith...

Page 81: ...ive Select reduced drive for output port This bit configures the drive strength of all associated port output pins as either full or reduced If a pin is used as input this bit has no effect The reduced drive function is independent of which function is being used on a particular pin 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x001C PRR Acce...

Page 82: ...ce the internal bus clock 1 ECLKX2 disabled 0 ECLKX2 enabled 5 DIV16 Free running ECLK predivider Divide by 16 This bit enables a divide by 16 stage on the selected EDIV rate 1 Divider enabled ECLK rate EDIV rate divided by 16 0 Divider disabled ECLK rate EDIV rate 4 0 EDIV Free running ECLK Divider Configure ECLK rate These bits determine the rate of the free running clock on the ECLK pin 00000 E...

Page 83: ...eserved Figure 2 12 IRQ Control Register IRQCR Table 2 13 IRQCR Register Field Descriptions Field Description 7 IRQE IRQ select edge sensitive only Special mode Read or write anytime Normal mode Read anytime write once 1 IRQ configured to respond only to falling edges Falling edges on the IRQ pin will be detected anytime IRQE 1 and will be cleared only upon a reset or the servicing of the IRQ inte...

Page 84: ...Table 2 14 PORTK Register Field Descriptions Field Description 7 5 0 PK Port K general purpose input output data Data Register The associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is rea...

Page 85: ...0 PWM7 PWM6 PWM5 PWM4 VREG_API Reset 0 0 0 0 0 0 0 0 Figure 2 16 Port T Data Register PTT Table 2 16 PTT Register Field Descriptions Field Description 7 6 4 PTT Port T general purpose input output data Data Register TIM output routed PWM output When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is ...

Page 86: ...ion if enabled 3 0 PTT Port T general purpose input output data Data Register TIM output When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state ...

Page 87: ...d as output 0 Associated pin configured as input 5 DDRT Port T data direction This bit determines whether the pin is an input or output The TIM forces the I O state to be an output for a timer port associated with an enabled output compare Else the routed PWM forces the I O state to be an output for an enabled channel Else the VREG_API forces the I O state to be an output if enabled In these cases...

Page 88: ...rive strength 0 Full drive strength enabled Address 0x0244 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W Reset 0 0 0 0 0 0 0 0 Figure 2 20 Port T Pull Device Enable Register PERT Table 2 20 PERT Register Field Descriptions Field Description 7 0 PERT Port T pull device enable Enable pull device on input pin This bit controls...

Page 89: ...cts a pull up or a pull down device if enabled on the associated port input pin 1 A pull down device selected 0 A pull up device selected Address 0x0246 Access User read1 1 Read Always reads 0x00 Write Unimplemented 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 2 22 PIM Reserved Register Address 0x0247 Access User read1 1 Read Anytime Write Anytime 7 6 ...

Page 90: ...ort T peripheral routing This register controls the routing of PWM channel 5 1 PWM5 routed to PT5 0 PWM5 routed to PP5 4 PTTRR Port T peripheral routing This register controls the routing of PWM channel 4 1 PWM4 routed to PT4 0 PWM4 routed to PP4 2 PTTRR Port T peripheral routing This register controls the routing of TIM channel 2 1 IOC2 routed to PP2 0 IOC2 routed to PT2 1 PTTRR Port T peripheral...

Page 91: ... pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read The SPI0 function takes precedence over the general purpose I O function if enabled 5 PTS Port S general purpose input output data Data Reg...

Page 92: ... Port S general purpose input output data Data Register SCI0 TXD output When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read The SCI0 ...

Page 93: ...ated pin is an input or output Depending on the configuration of the enabled SPI0 the I O state will be forced to be input or output In this case the data direction bit will not change 1 Associated pin configured as output 0 Associated pin configured as input 3 2 DDRS Port S data direction This bit determines whether the associated pin is an input or output Depending on the configuration of the en...

Page 94: ...this bit has no effect The reduced drive function is independent of which function is being used on a particular pin 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x024B Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W Reset 1 1 1 1 1 1 1 1 Figure 2 28 Port S Pull Device E...

Page 95: ...d port input pin 1 A pull down device selected 0 A pull up device selected Address 0x024C Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W Reset 0 0 0 0 0 0 0 0 Figure 2 30 Port S Wired Or Mode Register WOMS Table 2 29 WOMS Register Field Descriptions Field Description 7 0 WOMS Port S wired or mode Enable open drain functional...

Page 96: ...ld Descriptions Field Description 7 6 PTM Port M general purpose input output data Data Register When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin inpu...

Page 97: ... the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read The SPI0 function takes precedence over the general purpose I O function if enabled 1 PTM Port M general purpose input output data Data Register CAN0 TXCAN output SCI1 TXD output When not used with the alterna...

Page 98: ...eset u u u u u u u u Unimplemented or Reserved u Unaffected by reset Figure 2 33 Port M Input Register PTIM Table 2 31 PTIM Register Field Descriptions Field Description 7 0 PTIM Port M input data A read always returns the buffered input state of the associated pin It can be used to detect overload or short circuit conditions on output pins Address 0x0252 Access User read write1 1 Read Anytime Wri...

Page 99: ... this case the data direction bit will not change 1 Associated pin configured as output 0 Associated pin configured as input 0 DDRM Port M data direction This bit determines whether the associated pin is an input or output The enabled CAN0 or SCI1 forces the I O state to be an input In this case the data direction bit will not change 1 Associated pin configured as output 0 Associated pin configure...

Page 100: ...ted port input pin is active If a pin is used as output this bit has only effect if used in wired or mode The polarity is selected by the related polarity select register bit 1 Pull device enabled 0 Pull device disabled Address 0x0255 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 W Reset 0 0 0 0 0 0 0 0 Figure 2 37 Port M Pol...

Page 101: ...ed or mode Enable open drain functionality on output pin This bit configures an output pin as wired or open drain or push pull independent of the function used on the pins In wired or mode a logic 0 is driven active low while a logic 1 remains undriven This allows a multipoint connection of several serial modules The bit has no influence on pins used as input 1 Output buffer operates as open drain...

Page 102: ...g MODRRx Related Pins 4 MISO0 MOSI0 SCK0 SS0 0 PS4 PS5 PS6 PS7 1 PM2 PM4 PM5 PM3 Address 0x0258 Access User read write1 1 Read Anytime the data source depends on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W Altern Function PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 IOC2 IOC1 IOC0 TXD1 RXD1 Reset 0 0 0 0 0 0 0 0 Figure 2 40 Port P Data Register PTP...

Page 103: ...tput mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read The PWM function takes precedence over the general purpose I O function if the related channel is enabled Pin interrupts can be generated if enabled in input or output mode 2 PTP Port P general purpos...

Page 104: ...n the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read The PWM function takes precedence over the TIM SCI1 and general purpose I O function if the related channel is enabled The ...

Page 105: ...s the I O state to be an output for an enabled channel In this case the data direction bit will not change 1 Associated pin configured as output 0 Associated pin configured as input 2 0 DDRP Port P data direction This bit determines whether the associated pin is an input or output The PWM forces the I O state to be an output for an enabled channel Else the TIM forces the I O state to be an output ...

Page 106: ...f a pin is used as input this bit has no effect The reduced drive function is independent of which function is being used on a particular pin 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x025C Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W Reset 0 0 0 0 0 0 0 0 Figure ...

Page 107: ...ge polarity on input pin This bit selects a pull up or a pull down device if enabled on the associated port input pin This bit also selects the polarity of the active pin interrupt edge 1 A pull down device selected rising edge selected 0 A pull up device selected falling edge selected Address 0x025E Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PIEP7 PIEP6 PIEP5 PIEP4 PIE...

Page 108: ...t field clears the flag 1 Active edge on the associated bit has occurred an interrupt will occur if the associated enable bit is set 0 No active edge occurred Address 0x0260 Access User read write1 1 Read Anytime the data source depends on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 W Reset 0 0 0 0 0 0 0 0 Figure 2 48 Port H Data Register PTH Ta...

Page 109: ... PTIH Register Field Descriptions Field Description 7 0 PTIH Port H input data A read always returns the buffered input state of the associated pin It can be used to detect overload or short circuit conditions on output pins Address 0x0262 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 W Reset 0 0 0 0 0 0 0 0 Figure 2 50 Port ...

Page 110: ...f a pin is used as input this bit has no effect The reduced drive function is independent of which function is being used on a particular pin 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x0264 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 W Reset 0 0 0 0 0 0 0 0 Figure ...

Page 111: ...ge polarity on input pin This bit selects a pull up or a pull down device if enabled on the associated port input pin This bit also selects the polarity of the active pin interrupt edge 1 A pull down device selected rising edge selected 0 A pull up device selected falling edge selected Address 0x0266 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PIEH7 PIEH6 PIEH5 PIEH4 PIE...

Page 112: ...g bit field clears the flag 1 Active edge on the associated bit has occurred an interrupt will occur if the associated enable bit is set 0 No active edge occurred Address 0x0268 Access User read write1 1 Read Anytime the data source depends on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R PTJ7 PTJ6 0 0 0 0 PTJ1 PTJ0 W Reset 0 0 0 0 0 0 0 0 Figure 2 56 Port J Data Register PTJ Table 2 55...

Page 113: ...J Register Field Descriptions Field Description 7 6 1 0 PTIJ Port J input data A read always returns the buffered input state of the associated pin It can be used to detect overload or short circuit conditions on output pins Address 0x026A Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R DDRJ7 DDRJ6 0 0 0 0 DDRJ1 DDRJ0 W Reset 0 0 0 0 0 0 0 0 Figure 2 58 Port J Data Direction...

Page 114: ... a pin is used as input this bit has no effect The reduced drive function is independent of which function is being used on a particular pin 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x026C Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PERJ7 PERJ6 0 0 0 0 PERJ1 PERJ0 W Reset 1 1 1 1 1 1 1 1 Figure 2 60 Port J Pull ...

Page 115: ...ge polarity on input pin This bit selects a pull up or a pull down device if enabled on the associated port input pin This bit also selects the polarity of the active pin interrupt edge 1 A pull down device selected rising edge selected 0 A pull up device selected falling edge selected Address 0x026E Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PIEJ7 PIEJ6 0 0 0 0 PIEJ1 P...

Page 116: ...dge on the associated bit has occurred an interrupt will occur if the associated enable bit is set 0 No active edge occurred Address 0x0270 Access User read write1 1 Read Anytime the data source depends on the data direction value Write Anytime 7 6 5 4 3 2 1 0 R PT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00 W Altern Function AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 Reset 0 0 0 0 0 0...

Page 117: ...ternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read Address 0x0272 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R DDR0AD07 DDR0AD06 DD...

Page 118: ...TD Digital Input Enable Register ATD0DIEN has to be set to logic level 1 1 Associated pin configured as output 0 Associated pin configured as input Address 0x0274 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R RDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00 W Reset 0 0 0 0 0 0 0 0 Figure 2 68 Port AD0 Reduced Drive Register 0 RDR0AD0 Table 2 67 RDR0A...

Page 119: ...uced If a pin is used as input this bit has no effect The reduced drive function is independent of which function is being used on a particular pin 1 Reduced drive selected approx 1 5 of the full drive strength 0 Full drive strength enabled Address 0x0276 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00 W...

Page 120: ...1AD01 PER1AD00 W Reset 0 0 0 0 0 0 0 0 Figure 2 71 Port AD0 Pull Up Enable Register 1 PER1AD0 Table 2 70 PER1AD0 Register Field Descriptions Field Description 7 0 PER1AD0 Port AD0 pull device enable Enable pull up device on input pin This bit controls whether a pull device on the associated port input pin is active If a pin is used as output this bit has no effect The polarity is selected by the r...

Page 121: ...egister is returned This is independent of any other configuration Figure 2 73 2 4 2 2 Input register PTIx This is a read only register and always returns the buffered state of the pin Figure 2 73 2 4 2 3 Data direction register DDRx This register defines whether the pin is used as a input or an output If a peripheral module controls the pin the contents of the data direction register is ignored F...

Page 122: ...module 2 4 2 5 Pull device enable register PERx This register turns on a pull up or pull down device on the related pins determined by the associated polarity select register 2 4 2 5 2 122 The pull device becomes active only if the pin is used as an input or as a wired or output Some peripheral modules only allow certain configurations of pull devices to become active Refer to the respective bit d...

Page 123: ... SCI1 and SPI0 pins to alternative ports PTTRR supports the re routing of the PWM and TIM channels to alternative ports 2 4 3 Pins and Ports NOTE Please refer to the device pinout section to determine the pin availability in the different package options 2 4 3 1 BKGD pin The BKGD pin is associated with the BDM module During reset the BKGD pin is used as MODC input 2 4 3 2 Port A B Port A pins PA 7...

Page 124: ...t is associated with TIM and PWM Port T pins PT 7 4 can be used for either general purpose I O or with the PWM or with the channels of the standard Timer subsystem Port T pins PT 3 0 can be used for either general purpose I O or with the channels of the standard Timer subsystem The TIM pins IOC2 0 can be re routed 2 4 3 6 Port S This port is associated with SPI0 SCI0 and SCI1 Port S pins PS 7 4 ca...

Page 125: ...sed for either general purpose I O or with the ATD0 subsystem 2 4 4 Pin interrupts Ports P H and J offer pin interrupt capability The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on a per pin basis All bits pins in a port share the same interrupt vector Interrupts can be used with the pins configured as inputs or outputs An interrupt is gene...

Page 126: ...r runs only if the following condition is true on any pin individually Sample count 4 and interrupt enabled PIE 1 and interrupt flag not set PIF 0 2 5 Initialization Information 2 5 1 Port Data and Data Direction Register writes It is not recommended to write PORTx PTx and DDRx in a word access When changing the register pins from inputs to outputs the data may have extra transitions during the wr...

Page 127: ...n Figure 3 1 The MMC module controls the multi master priority accesses the selection of internal resources Internal buses including internal memories and peripherals are controlled in this module The local address space for each master is translated to a global memory space Rev No Item No Date Submitted By Sections Affected Substantial Change s v04 09 01 Feb 08 Minor changes v04 10 17 Feb 09 Mino...

Page 128: ... to Boolean true state Logic level 0 Voltage that corresponds to Boolean false state 0x Represents hexadecimal number x Represents logic level don t care Byte 8 bit data word 16 bit data local address based on the 64KB Memory Space 16 bit address global address based on the 8MB Memory Space 23 bit address Aligned address Address on even boundary Mis aligned address Address on odd boundary Bus Cloc...

Page 129: ...egisters and the default instruction set The 64KB visible at any instant can be considered as the local map accessed by the 16 bit CPU or BDM address The MMC module performs translation of the different memory mapping schemes to the specific global physical memory implementation 3 1 4 Modes of Operation This subsection lists and briefly describes all operating modes supported by the MMC 3 1 4 1 Po...

Page 130: ...d location of external bus signals Some pins may not be bonded out in all implementations Table 3 2 outlines the pin names and functions It also provides a brief description of their operation Table 3 2 External Input Signals Associated with the MMC Signal I O Description Availability MODC I Mode input Latched after RESET active low CPU BDM Target Bus Controller DBG MMC Address Decoder Priority Pe...

Page 131: ...ress Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x000A Reserved R 0 0 0 0 0 0 0 0 W 0x000B MODE R MODC 0 0 0 0 0 0 0 W 0x0010 GPAGE R 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 W 0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 W 0x0012 Reserved R 0 0 0 0 0 0 0 0 W 0x0013 MMCCTL1 R MGRAMON 0 DFIFRON PGMIFRON 0 0 0 0 W 0x0014 Reserved R 0 0 0 0 0 0 0 0 W 0x0015 PPAGE R PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 W ...

Page 132: ...is bit controls the current operating mode during RESET high inactive The external mode pin MODC determines the operating mode during RESET low active The state of the pin is latched into the respective register bit after the RESET signal goes inactive see Figure 3 3 Write restrictions exist to disallow transitions between certain modes Figure 3 5 illustrates all allowed mode changes Attempting no...

Page 133: ... register 22 16 see Figure 3 7 Figure 3 7 GPAGE Address Mapping Example 3 1 This example demonstrates usage of the GPAGE register LDX 0x5000 Set GPAGE offset to the value of 0x5000 MOVB 0x14 GPAGE Initialize GPAGE register with the value of 0x14 GLDAA X Load Accu A from the global address 0x14_5000 Address 0x0010 7 6 5 4 3 2 1 0 R 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 W Reset 0 0 0 0 0 0 0 0 Unimplemented...

Page 134: ...monstrates usage of the Direct Addressing Mode MOVB 0x80 DIRECT Set DIRECT register to 0x80 Write once only Global data accesses to the range 0xXX_80XX can be direct Logical data accesses to the range 0x80XX are direct LDY 00 Load the Y index register from 0x8000 direct access operator forces direct access on some assemblers but in many cases assemblers are direct page aware and can automatically ...

Page 135: ...er SCRATCH RAM visible in the global memory map 0 Not visible in the global memory map 1 Visible in the global memory map 5 DFIFRON Data Flash Information Row IFR visible in the global memory map Write Anytime This bit is used to made the IFR sector of the Data Flash visible in the global memory map 0 Not visible in the global memory map 1 Visible in the global memory map 4 PGMIFRON Program Flash ...

Page 136: ... to this register using the special access of the CALL and RTC instructions will be complete before the end of the instruction execution The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and 0xFFFF out of reset The fixed 16K page from 0xC000 0xFFFF is the page number 0xFF 3 3 2 6 RAM Page Index Register RPAGE Table 3 7 PPAGE Field Descriptions Fiel...

Page 137: ...hrough the RAM space when RPAGE 0x00 The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and 0x3FFF out of reset The fixed 4K page from 0x2000 0x2FFF of RAM is equivalent to page 254 page number 0xFE The fixed 4K page from 0x3000 0x3FFF of RAM is equivalent to page 255 page number 0xFF NOTE The page 0xFD reset value contains unimplemented area in the...

Page 138: ...12XS Family Reference Manual Rev 1 13 138 Freescale Semiconductor The two fixed 4KB pages 0xFE 0xFF contain unimplemented area in the range not occupied by RAM if RAMSIZE is less than 8KB Refer to Section 3 4 2 3 Implemented Memory Map ...

Page 139: ...he Data FLASH page index register is effectively used to construct paged Data FLASH addresses in the Local map format Figure 3 16 EPAGE Address Mapping Address 0x0017 7 6 5 4 3 2 1 0 R EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 W Reset 1 1 1 1 1 1 1 0 Figure 3 15 Data FLASH Page Index Register EPAGE Table 3 9 EPAGE Field Descriptions Field Description 7 0 EP 7 0 Data FLASH Page Index Bits 7 0 These page inde...

Page 140: ...Memory Map Scheme 3 4 2 1 CPU and BDM Memory Map Scheme The BDM firmware lookup tables and BDM register memory locations share addresses with other modules however they are not visible in the global memory map during user s code execution The BDM memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish between accesses to the BDM memory area and accesses to th...

Page 141: ...eset Vectors 0xC000 0x8000 Unpaged 0x4000 0x1000 0x0000 16KB FLASH window 0x0C00 0x2000 0x0800 8KB RAM 4KB RAM window Reserved 2KB REGISTERS 1KB Data Flash window 16KB FLASH Unpaged 16KB FLASH 2KB REGISTERS 2KB RAM 253 4KB paged RAM 256 1KB paged Data FLASH 253 16KB paged FLASH 16KB FLASH PPAGE 0xFD 8KB RAM 16KB FLASH PPAGE 0xFE 16KB FLASH PPAGE 0xFF 0x00_1000 0x0F_E000 0x13_FC00 0x40_0000 0x7F_40...

Page 142: ...he starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the PPAGE register will be set to the appropriate value when the service routine is called However an interrupt service routine can call other routines that are in paged memory The upper 16KB block of the local CPU memory space 0xC000 0xFFFF is unpaged It is recommended that all re...

Page 143: ...2 Global Page Index Register GPAGE The generated global address is the result of concatenation of the CPU local address 15 0 with the GPAGE register 22 16 see Figure 3 7 BDM Global Addresses Based on the Global Page The seven BDMGPR Global Page index bits allow access to the full 8MB address map that can be accessed with 23 address bits This provides an alternative way to access all of the various...

Page 144: ... the memory spaces occupied by the on chip resources Please note that the memory spaces have fixed top addresses Table 3 10 Global Implemented Memory Space Internal Resource Address RAM RAM_LOW 0x10_0000 minus RAMSIZE1 1 RAMSIZE is the hexadecimal value of RAM SIZE in Bytes Data FLASH DF_HIGH 0x10_0000 plus DFLASHSIZE2 2 DFLASHSIZE is the hexadecimal value of DFLASH SIZE in Bytes FLASH FLASH_LOW 0...

Page 145: ...implemented areas are allowed but the data will be undefined No misaligned word access from the BDM module will occur these accesses are blocked in the BDM module Refer to BDM Block Guide Misaligned word access to the last location of RAM is performed but the data will be undefined Misaligned word access to the last location of any global page 64KB by any global instruction is performed by accessi...

Page 146: ...GE RPAGE PPAGE 0x3F_FFFF CPU and BDM Local Memory Map Global Memory Map FLASHSIZE RAMSIZE 0xFFFF Reset Vectors 0xC000 0x8000 Unpaged 0x4000 0x1000 0x0000 16K FLASH window 0x0C00 0x2000 0x0800 8K RAM 4K RAM window Reserved 2K REGISTERS 1K Data Flash window 16K FLASH Unpaged 16K FLASH 2K REGISTERS Unimplemented RAM RAM_LOW FLASH FLASH_LOW Unimplemented FLASH Unimplemented Space DF_HIGH Data FLASH Re...

Page 147: ...s that interface the S12X masters CPU BDM with the rest of the system master buses In addition the MMC handles all CPU read data bus swapping operations All internal resources are connected to specific target buses see Figure 3 20 Figure 3 20 MMC Block Diagram CPU BDM Target Bus Controller DBG MMC Address Decoder Priority Peripherals PGMFLASH Data FLASH RAM S12X1 S12X0 XBUS0 ...

Page 148: ... the execution of the CALL instruction the CPU performs the following steps 1 Writes the current PPAGE value into an internal temporary register and writes the new instruction supplied PPAGE value into the PPAGE register 2 Calculates the address of the next instruction after the CALL instruction the return address and pushes this 16 bit value onto the stack 3 Pushes the temporarily stored PPAGE va...

Page 149: ...ion cycles Usage of JSR RTS instructions is therefore recommended when possible and CALL RTC instructions should only be used when needed The JSR and RTS instructions can be used to access subroutines that are already present in the local CPU memory map i e in the same page in the program memory page window for example However calling a function located in a different page requires usage of the CA...

Page 150: ...Memory Mapping Control S12XMMCV4 S12XS Family Reference Manual Rev 1 13 150 Freescale Semiconductor ...

Page 151: ...red to be handled by the CPU the priority scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed Interrupt requests configured to be handled by the XGATE module can be nested one level deep NOTE The HPRIO register and functionality of the original S12 interrupt module is no longer supp...

Page 152: ...ase 0x00F6 One non maskable unimplemented op code trap TRAP vector at address vector base 0x00F8 Three system reset vectors at addresses 0xFFFA 0xFFFE Determines the highest priority XGATE and interrupt vector requests drives the vector to the XGATE module or to the bus on CPU request respectively Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or whenever X...

Page 153: ...uest occurs Please refer to Section 4 5 3 Wake Up from Stop or Wait Mode for details Stop Mode In stop mode the XINT module is frozen It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs Please refer to Section 4 5 3 Wake Up from Stop or Wait Mode for details Freeze mode BDM active In freeze mode BDM active the interrupt vector ...

Page 154: ...XGATE Interrupts XGATE Requests Interrupt Requests Interrupt Requests CPU Vector Address New IPL IPL Up to 108 Channels RQST XGATE Request Route PRIOLVLn Priority Level bits from the channel configuration in the associated configuration register INT_XGPRIO XGATE Interrupt Priority IVBR Interrupt Vector Base IPL Interrupt Processing Level PRIOLVL0 PRIOLVL1 PRIOLVL2 INT_XGPRIO Peripheral Vector ID T...

Page 155: ...guration Register INT_XGPRIO R W 0x0127 Interrupt Request Configuration Address Register INT_CFADDR R W 0x0128 Interrupt Request Configuration Data Register 0 INT_CFDATA0 R W 0x0129 Interrupt Request Configuration Data Register 1 INT_CFDATA1 R W 0x012A Interrupt Request Configuration Data Register 2 INT_CFDATA2 R W 0x012B Interrupt Request Configuration Data Register 3 INT_CFDATA3 R W 0x012C Inter...

Page 156: ...0 0 0 0 0 XILVL 2 0 W 0x0127 INT_CFADDR R INT_CFADDR 7 4 0 0 0 0 W 0x0128 INT_CFDATA0 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x0129 INT_CFDATA1 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012A INT_CFDATA2 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012B INT_CFDATA3 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012C INT_CFDATA4 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012D INT_CFDATA5 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012E INT_CFDATA6 R RQST 0 0 0 0 PRIOLVL 2 0...

Page 157: ... with 0xFF before it is used to determine the reset vector address Therefore changing the IVBR has no effect on the location of the three reset vectors 0xFFFA 0xFFFE Note If the BDM is active i e the CPU is in the process of executing BDM firmware code the contents of IVBR are ignored and the upper byte of the vector address is fixed as 0xFF Address 0x0126 7 6 5 4 3 2 1 0 R 0 0 0 0 0 XILVL 2 0 W R...

Page 158: ...0 1 0 Priority level 2 0 1 1 Priority level 3 1 0 0 Priority level 4 1 0 1 Priority level 5 1 1 0 Priority level 6 high 1 1 1 Priority level 7 Address 0x0127 7 6 5 4 3 2 1 0 R INT_CFADDR 7 4 0 0 0 0 W Reset 0 0 0 1 0 0 0 0 Unimplemented or Reserved Figure 4 5 Interrupt Configuration Address Register INT_CFADDR Table 4 7 INT_CFADDR Field Descriptions Field Description 7 4 INT_CFADDR 7 4 Interrupt R...

Page 159: ...tes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 7 Interrupt Request Configuration Data Register 1 INT_CFDATA1 Address 0x012A 7 6 5 4 3 2 1 0 R RQST 0 0 0 0 PRIOLVL 2 0 W Reset 0 0 0 0 0 0 0 1 1 1 Please refer to the notes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 8 Interrupt Request Configuration Data Register 2 INT_CFDATA2 Ad...

Page 160: ...er to the notes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 11 Interrupt Request Configuration Data Register 5 INT_CFDATA5 Address 0x012E 7 6 5 4 3 2 1 0 R RQST 0 0 0 0 PRIOLVL 2 0 W Reset 0 0 0 0 0 0 0 1 1 1 Please refer to the notes following the PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 12 Interrupt Request Configuration Data Register 6 ...

Page 161: ...t requests are enabled at the lowest active level 1 to provide backwards compatibility with previous S12 interrupt controllers Please also refer to Table 4 9 for available interrupt request priority levels Note Write accesses to configuration data registers of unused interrupt channels will be ignored and read accesses will return all 0 For information about what interrupt channels are used in a s...

Page 162: ...peripheral module must be set 2 The setup in the configuration register associated with the interrupt request channel must meet the following conditions a The XGATE request enable bit must be 0 to have the CPU handle the interrupt request b The priority level must be set to non zero c The priority level must be greater than the current interrupt processing level in the condition code register CCR ...

Page 163: ...uest channel becomes active at the same time the channel with the highest vector address wins the prioritization 4 4 4 Priority Decoders The XINT module contains priority decoders to determine the priority for all interrupt requests pending for the respective target There are two priority decoders one for each interrupt request target CPU or XGATE The function of both priority decoders is basicall...

Page 164: ...plemented op code trap request SWI BGND request SYS request there is no real priority defined because they cannot occur simultaneously the S12XCPU executes one instruction at a time Table 4 10 Exception Vector Map and Priority Vector Address 1 1 16 bits vector address based Source 0xFFFE Pin reset power on reset low voltage reset illegal address reset 0xFFFC Clock monitor reset 0xFFFA COP watchdog...

Page 165: ...The interrupt request priority level scheme makes it possible to implement priority based interrupt request nesting for the I bit maskable interrupt requests handled by the CPU I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority so that there can be up to seven nested I bit maskable interrupt requests at a time refer to Figure 4 14 for an example usi...

Page 166: ...ll I bit maskable interrupts are masked from waking up the MCU An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the current IPL in CCR I bit maskable interrupt requests which are configured to be handled by the XGATE module are not capable of waking up the CPU The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime ...

Page 167: ...iconductor 167 4 5 3 2 XGATE Wake Up from Stop or Wait Mode Interrupt request channels which are configured to be handled by the XGATE module are capable of waking up the XGATE module Interrupt request channels handled by the XGATE module do not affect the state of the CPU ...

Page 168: ...Interrupt S12XINTV2 S12XS Family Reference Manual Rev 1 13 168 Freescale Semiconductor ...

Page 169: ...12 family with the following exceptions TAGGO command no longer supported by BDM External instruction tagging feature now part of DBG module BDM register map and register content extended modified Global page access functionality Enabled but not active out of reset in emulation modes if modes available CLKSW bit set out of reset in emulation modes if modes available Family ID readable from firmwar...

Page 170: ...ed all bus masters are in stop mode 5 1 2 Modes of Operation BDM is available in all operating modes but must be enabled before firmware commands are executed Some systems may have a control bit that allows suspending thefunction during background debug mode 5 1 2 1 Regular Run Modes All of these operations refer to the part in run mode and not being secured The BDM does not provide controls to co...

Page 171: ... mode the BDM clocks will restart and BDM will have a soft reset clearing the instruction register any command in progress and disable the ACK function The BDM is now ready to receive a new command 5 1 3 Block Diagram A block diagram of the BDM is shown in Figure 5 1 Figure 5 1 BDM Block Diagram 5 2 External Signal Description A single wire interface pin called the background debug interface BKGD ...

Page 172: ... Address Module Size Bytes 0x7FFF00 0x7FFF0B BDM registers 12 0x7FFF0C 0x7FFF0E BDM firmware ROM 3 0x7FFF0F Family ID part of BDM firmware ROM 1 0x7FFF10 0x7FFFFF BDM firmware ROM 240 Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x7FFF00 Reserved R X X X X X X 0 0 W 0x7FFF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE CLKSW UNSEC 0 W 0x7FFF02 Reserved R X X X X X X X X W 0x7FFF03 Reserved R X X X X ...

Page 173: ...fully erased non volatile memory This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed 1 0 0 0 0 03 3 UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased else it is 0 and can only be read if not secure see also bit description 0 Emulation Modes if modes available 1 0...

Page 174: ... available the ENBDM bit is set by BDM hardware out of reset In special single chip mode with the device secured this bit will not be set by the firmware until after the non volatile memory erase verify tests are complete In emulation modes if modes available with the device secured the BDM operations are blocked 6 BDMACT BDM Active Status This bit becomes set upon entering BDM The standard BDM fi...

Page 175: ...h changes it Note In emulation modes if modes available the CLKSW bit will be set out of RESET 1 UNSEC Unsecure If the device is secured this bit is only writable in special single chip mode from the BDM secure firmware It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map overlapping the standard BDM firmware lookup tab...

Page 176: ... condition code register of the user s program It is also used for temporary storage in the standard BDM firmware mode The BDM CCR LOW holding register can be written to modify the CCR value 5 3 2 3 BDM CCR HIGH Holding Register BDMCCRH Figure 5 5 BDM CCR HIGH Holding Register BDMCCRH Read All modes through BDM operation when not secured Write All modes through BDM operation when not secured When ...

Page 177: ...mode see Section 5 4 4 Standard BDM Firmware Commands The CPU resources referred to are the accumulator D X index register X Y index register Y stack pointer SP and program counter PC Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted see Section 5 4 3 BDM Hardware Commands and in secure mode see Section 5 4 1 Security Firmware commands can only...

Page 178: ... must be in active BDM to execute standard BDM firmware commands BDM can be activated only after being enabled BDM is enabled by setting the ENBDM bit in the BDM status BDMSTS register The ENBDM bit is set by writing to the BDM status BDMSTS register via the single wire interface using a hardware command such as WRITE_BD_BYTE After being enabled BDM is activated by one of the following1 Hardware B...

Page 179: ...e the same address BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle This allows the BDM to access BDM locations unobtrusively even if the addresses conflict with the application memory map Table 5 6 Hardware Commands Command Opcode hex Data Description BACKGROUND 90 None Enter background mode if firmware is enabled If enabled an ACK will be issued when the part enter...

Page 180: ...DM As the system enters active BDM the standard BDM firmware lookup table and BDM registers become visible in the on chip memory map at 0x7FFF00 0x7FFFFF and the CPU begins executing the standard BDM firmware The standard BDM firmware watches for serial commands and executes them as they are received The firmware commands are shown in Table 5 7 WRITE_WORD C8 16 bit address 16 bit data in Write to ...

Page 181: ...cumulator READ_X 65 16 bit data out Read X index register READ_Y 66 16 bit data out Read Y index register READ_SP 67 16 bit data out Read stack pointer WRITE_NEXT f hel vetica st superscri pt 42 16 bit data in Increment X index register by 2 X X 2 then write word to location pointed to by X WRITE_PC 43 16 bit data in Write program counter WRITE_D 44 16 bit data in Write D accumulator WRITE_X 45 16...

Page 182: ...he read data This includes the potential of extra cycles when the access is external and stretched 1 to maximum 7 cycles or to registers of the PRU port replacement unit in emulation modes if modes available The 48 cycle wait allows enough time for the requested data to be made available in the BDM shift register ready to be shifted out NOTE This timing has increased from previous BDM modules due ...

Page 183: ...active pull up that is enabled at all times It is assumed that there is an external pull up and that drivers connected to BKGD do not typically drive the high level Since R C rise time could be unacceptably long the target system and host provide brief driven high speedup pulses to drive BKGD to a logic 1 The source of this speedup pulse is the host for transmit cases and the target for receive ca...

Page 184: ...en high no later that eight target clock cycles after the falling edge for a logic 1 transmission Since the host drives the high speedup pulses in these two cases the rising edges look like digitally driven signals Figure 5 8 BDM Host to Target Serial Bit Timing The receive cases are more complicated Figure 5 9 shows the host receiving a logic 1 from the target system Since the host is asynchronou...

Page 185: ...tor 185 Figure 5 9 BDM Target to Host Serial Bit Timing Logic 1 High Impedance Earliest Start of Next Bit R C Rise 10 Cycles 10 Cycles Host Samples BKGD Pin Perceived Start of Bit Time BKGD Pin BDM Clock Target MCU Host Drive to BKGD Pin Target System Speedup Pulse High Impedance High Impedance ...

Page 186: ...the clock could be running This sub section will describe the hardware handshake protocol The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin This pulse is generated by the target MCU when a command issued by t...

Page 187: ...ode is sent by the host followed by the address of the memory location to be read The target BDM decodes the instruction A bus cycle is grabbed free or stolen by the BDM and it executes the READ_BYTE operation Having retrieved the data the BDM issues an ACK pulse to the host controller indicating that the addressed byte is ready to be retrieved After detecting the ACK pulse the host initiates the ...

Page 188: ...d NOTE The ACK pulse does not provide a time out This means for the GO_UNTIL command that it can not be distinguished if a stop or wait has been executed command discarded and ACK not issued or if the UNTIL condition BDM active is just not reached yet Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command See the...

Page 189: ...ld be used After a command is aborted the target assumes the next negative edge after the abort pulse is the first bit of a new BDM command NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior It is not recommended that this procedure be used in a real application Since the host knows the target serial clo...

Page 190: ...he target device If desired without the need for waiting for the ACK pulse The commands are described as follows ACK_ENABLE enables the hardware handshake protocol The target will issue the ACK pulse when a CPU command is executed by the CPU The ACK_ENABLE command itself also has the ACK pulse as a response ACK_DISABLE disables the ACK pulse protocol In this case the host needs to use the worst ca...

Page 191: ...and has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed The ACK pulse related to this command could be aborted using the SYNC command 5 4 9 SYNC Request Timed Reference Pulse The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM comm...

Page 192: ...standard BDM firmware execution the program counter points to the first instruction in the interrupt service routine Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist Do not trace the CPU ins...

Page 193: ... is not enabled However consider the behavior where the BDM is running in a frequency much greater than the CPU frequency In this case the command could time out before the data is ready to be retrieved In order to allow the data to be retrieved even with a large clock frequency mismatch between BDM and CPU when the hardware handshake protocol is enabled the time out between a read command and the...

Page 194: ...Background Debug Module S12XBDMV2 S12XS Family Reference Manual Rev 1 13 194 Freescale Semiconductor ...

Page 195: ...1 1 Glossary Revision Number Revision Date Sections Affected Description of Changes V03 20 14 Sep 2007 6 3 2 7 6 205 Clarified reserved State Sequencer encodings V03 21 23 Oct 2007 6 4 2 2 6 218 6 4 2 4 6 219 Added single databyte comparison limitation information Added statement about interrupt vector fetches whilst tagging V03 22 12 Nov 2007 6 4 5 2 6 223 6 4 5 5 6 227 Removed LOOP1 tracing rest...

Page 196: ...are the full address bus only Each comparator can be configured to monitor CPU12X buses Each comparator features selection of read or write access cycles Comparators B and D allow selection of byte or word access cycles Comparisons can be used as triggers for the state sequencer Three comparator modes Simple address data comparator match mode Inside address range mode Addmin Address Addmax Outside...

Page 197: ... 4 Modes of Operation The S12XDBG module can be used in all MCU functional modes During BDM hardware accesses and whilst the BDM module is active CPU12X monitoring is disabled Thus breakpoints comparators and CPU12X bus tracing are disabled When the CPU12X enters active BDM Mode through a BACKGROUND command with the S12XDBG module armed the S12XDBG remains armed The S12XDBG module tracing is disab...

Page 198: ... given in the subsections that follow Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0020 DBGC1 R ARM 0 reserved BDM DBGBRK reserved COMRV W TRIG 0x0021 DBGSR R TBF 0 0 0 0 SSF2 SSF1 SSF0 W 0x0022 DBGTCR R reserved TSOURCE TRANGE TRCMOD TALIGN W 0x0023 DBGC2 R 0 0 0 0 CDCM ABCM W Figure 6 2 Quick Reference to S12XDBG Registers S12XCPU BUS TRACE BUFFER BUS INTERFACE TRIGGER MATCH0 STATE COMPARATOR B COMPAR...

Page 199: ...DBGCNT R 0 CNT W 0x0027 DBGSCRX R 0 0 0 0 SC3 SC2 SC1 SC0 W 0x0027 DBGMFR R 0 0 0 0 MC3 MC2 MC1 MC0 W 0x00281 DBGXCTL COMPA C R 0 NDB TAG BRK RW RWE reserved COMPE W 0x00282 DBGXCTL COMPB D R SZE SZ TAG BRK RW RWE reserved COMPE W 0x0029 DBGXAH R 0 Bit 22 21 20 19 18 17 Bit 16 W 0x002A DBGXAM R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002B DBGXAL R Bit 7 6 5 4 3 2 1 Bit 0 W 0x002C DBGXDH R Bit 15 14 13 1...

Page 200: ...nt is generated with tracing not enabled On setting this bit the state sequencer enters State1 0 Debugger disarmed 1 Debugger armed 6 TRIG Immediate Trigger Request Bit This bit when written to 1 requests an immediate trigger independent of comparator signal status When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings This bit always reads back a ...

Page 201: ...0 0 SSF2 SSF1 SSF0 W Reset POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 4 Debug Status Register DBGSR Table 6 6 DBGSR Field Descriptions Field Description 7 TBF Trace Buffer Full The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed If this bit is set then all 64 lines will be valid data regardless of the value of DBGCNT bit...

Page 202: ...s the tracing session If the MCU system is secured this bit cannot be set and tracing is inhibited 0 No tracing selected 1 Tracing selected 5 4 TRANGE Trace Range Bits The TRANGE bits allow filtering of trace information from a selected address range when tracing from the CPU12X in Detail Mode To use a comparator for range filtering the corresponding COMPE bits must remain cleared If the COMPE bit...

Page 203: ...OD Trace Mode Bit Encoding TRCMOD Description 00 Normal 01 Loop1 10 Detail 11 Pure PC Table 6 11 TALIGN Trace Alignment Encoding TALIGN Description 00 Trigger at end of stored data 01 Trigger before storing data 10 Trace buffer entries before and after trigger 11 Reserved Address 0x0023 7 6 5 4 3 2 1 0 R 0 0 0 0 CDCM ABCM W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 6 Debug Control R...

Page 204: ...comparator A Match1 mapped to comparator B Address 0x0024 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W POR X X X X X X X X X X X X X X X X Other Resets Figure 6 7 Debug Trace Buffer Register DBGTB Table 6 15 DBGTB Field Descriptions Field Description 15 0 Bit 15 0 Trace Buffer Data Bits The Tr...

Page 205: ...e Trace Buffer When the CNT rolls over to zero the TBF bit in DBGSR is set and incrementing of CNT will continue in end trigger or mid trigger mode The DBGCNT register is cleared when ARM in DBGC1 is written to a one The DBGCNT register is cleared by power on reset initialization but is not cleared by other system resets Thus should a reset occur during a debug session the DBGCNT register still in...

Page 206: ... 8 1 Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register Table 6 18 State Control Register Access Encoding COMRV Visible State Control Register 00 DBGSCR1 01 DBGSCR2 10 DBGSCR3 11 DBGMFR Address 0x0027 7 6 5 4 3 2 1 0 R 0 0 0 0 SC3 SC2 SC1 SC0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 9 Debug State Control Register 1 DBGSCR1 ...

Page 207: ...have no effect 1001 Match2 triggers to State3 Match0 triggers Final State Other matches have no effect 1010 Match1 triggers to State2 Match3 triggers to State3 Other matches have no effect 1011 Match3 triggers to State3 Match1 triggers to Final State Other matches have no effect 1100 Match3 has no effect All other matches M0 M1 M2 trigger to State2 1101 Reserved No match triggers state sequencer t...

Page 208: ... Match1 triggers to State3 Match0 triggers Final State Other matches have no effect 1000 Match0 triggers to State1 Match2 triggers to State3 Other matches have no effect 1001 Match2 triggers to State3 Match0 triggers Final State Other matches have no effect 1010 Match1 triggers to State1 Match3 triggers to State3 Other matches have no effect 1011 Match3 triggers to State3 Match1 triggers Final Sta...

Page 209: ...register address map Comparators A and C consist of 8 register bytes 3 address bus compare registers two data bus compare registers two data bus mask registers and a control register 0010 Any match triggers to Final State 0011 Match0 triggers to State1 Other matches have no effect 0100 Match0 triggers to State2 Other matches have no effect 0101 Match0 triggers to Final State Match1 triggers to Sta...

Page 210: ...BG module register address map Read Anytime See Table 6 26 for visible register encoding Write If DBG not armed See Table 6 26 for visible register encoding WARNING DBGXCTL 1 is reserved Setting this bit maps the corresponding comparator to an Table 6 25 Comparator Register Layout 0x0028 CONTROL Read Write Comparators A B C D 0x0029 ADDRESS HIGH Read Write Comparators A B C D 0x002A ADDRESS MEDIUM...

Page 211: ... on data bus difference to comparator register contents 6 SZ Comparators B and D Size Comparator Value Bit The SZ bit selects either word or byte access size in comparison for the associated comparator This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set This bit position has NDB functionality for comparators A and C 0 Word access size will be compared 1 Byte...

Page 212: ...bled for state sequence triggers or tag generation Table 6 28 Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write 1 0 1 No match 1 1 0 No match 1 1 1 Read Address 0x0029 7 6 5 4 3 2 1 0 R 0 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 15 Debug...

Page 213: ...d Descriptions Field Description 7 0 Bit 15 8 Comparator Address Mid Compare Bits The Comparator address mid compare bits control whether the selected comparator will compare the address bus bits 15 8 to a logic one or logic zero 0 Compare corresponding address bit to a logic zero 1 Compare corresponding address bit to a logic one Address 0x002B 7 6 5 4 3 2 1 0 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...

Page 214: ... comparator compares the data bus bits 15 8 to a logic one or logic zero The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1 This register is available only for comparators A and C 0 Compare corresponding data bit to a logic zero 1 Compare corresponding data bit to a logic one Address 0x002D 7 6 5 4 3 2 1 0 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit ...

Page 215: ... 6 20 Debug Comparator Data High Mask Register DBGXDHM Table 6 34 DBGXDHM Field Descriptions Field Description 7 0 Bits 15 8 Comparator Data High Mask Bits The Comparator data high mask bits control whether the selected comparator compares the data bus bits 15 8 to the corresponding comparator data compare bits This register is available only for comparators A and C 0 Do not compare corresponding ...

Page 216: ... four comparators A B C and D Each comparator compares the selected address bus with the address stored in DBGXAH DBGXAM and DBGXAL Furthermore comparators A and C also compare the data buses to the data stored in DBGXDH DBGXDL and allow masking of individual data bus bits S12X comparator matches are disabled in BDM and during BDM accesses The comparator match control logic configures comparators ...

Page 217: ...on Section 6 4 3 4 6 4 2 1 Exact Address Comparator Match Comparators A and C With range comparisons disabled the match condition is an exact equivalence of address data bus with the value stored in the comparator address data registers Further qualification of the type of access R W word byte is possible Comparators A and C do not feature SZE or SZ control bits thus the access size is not compare...

Page 218: ...er on equivalence or trigger on difference This allows monitoring of a difference in the contents of an address location from an expected value When matching on an equivalence NDB 0 each individual data bus bit position can be masked out by clearing the corresponding mask bit DBGxDHM DBGxDLM so that it is ignored in the comparison A match occurs when all data bus bits with corresponding mask bits ...

Page 219: ...omparisons and tagging the ranges are accurate only to word boundaries 6 4 2 4 1 Inside Range CompAC_Addr address CompBD_Addr In the Inside Range comparator mode either comparator pair A and B or comparator pair C and D can be configured for range comparisons by the control register DBGC2 The match condition requires that a valid match for both comparators happens on the same bus cycle A match con...

Page 220: ...y the CPU12X The state control register for the current state determines the next state for each trigger 6 4 3 3 TRIG Immediate Trigger Independent of comparator matches it is possible to initiate a tracing session and or breakpoint by writing the TRIG bit in DBGC1 to a logic 1 If configured for begin or mid aligned tracing this triggers the state sequencer into the Final State if configured for e...

Page 221: ... configured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers Thus it is possible to generate an immediate breakpoint on selected channels whilst a state sequencer transition can be initiated by a match on other channels If a debug session is ended by a trigger on a channel with BRK 1 the state sequencer transitions through Final State...

Page 222: ...turns invalid data and the trace buffer pointer is not incremented 6 4 5 1 Trace Trigger Alignment Using the TALIGN bits see Section 6 3 2 3 it is possible to align the trigger with the end the middle or the beginning of a tracing session If End or Mid tracing is selected tracing begins when the ARM bit in DBGC1 is set and State1 is entered The transition to Final State if End is selected signals ...

Page 223: ...JSR and CALL instruction Destination address of RTI RTS and RTC instructions Vector address of interrupts except for SWI and BDM vectors LBRA BRA BSR BGND as well as non indexed JMP JSR and CALL instructions are not classified as change of flow and are not stored in the trace buffer Change of flow addresses stored include the full 23 bit address bus of CPU12X and an information byte which contains...

Page 224: ...ffer resulting from repeated branches Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs It does not inhibit repeated entries of destination addresses or vector addresses since repeated entries of these would most likely indicate a bug in the user s code that the S12XDBG module is designed to help find 6 4 5 2 3 Det...

Page 225: ...ail mode DBGCNT 0 remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry When a COF occurs a trace buffer entry is made and the corresponding CDV bit is set Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer CDATAL and the high byte is cleared When tracing word accesses the byte at the lower address is always stored to tr...

Page 226: ... indicates if the corresponding stored address is a source or destination address This is only used in Normal and Loop1 mode tracing 0 Source address 1 Destination address 6 CVA Vector Indicator This bit indicates if the corresponding stored address is a vector address Vector addresses are destination addresses thus if CVA is set then the corresponding CSD is also set This is only used in Normal a...

Page 227: ...able 6 40 The bytes containing invalid information shaded in Table 6 40 are also read out Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of the RAM pointer will occur 6 4 5 5 Trace Buffer Reset State The Trace Buffer contents are not initialized by a system reset Thus should a system reset occur the trace session information from immediately bef...

Page 228: ...ed out Read Write R W access size SZ monitoring and data bus monitoring is not useful if tagged triggering is selected since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the type of access Thus these bits are ignored if tagged triggering is selected When configured for range comparisons and tagging the ranges are accurate only to word boundar...

Page 229: ...ule If the S12XBDM module is active the CPU12X is executing out of BDM firmware and S12X breakpoints are disabled In addition while executing a BDM TRACE command tagging into BDM is disabled If BDM is not active the breakpoint will give priority to BDM requests over SWI requests if the breakpoint coincides with a SWI instruction in the user s code On returning from BDM the SWI from user code gets ...

Page 230: ... breakpoint could occur simultaneously The CPU12X ensures that BDM requests have a higher priority than SWI requests Returning from the BDM SWI service routine care must be taken to avoid re triggering a breakpoint NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it will return to the instruction whose tag generated the ...

Page 231: ...rough the SCI which allows access to a programming routine that updates parameters stored in another section of the Flash memory The security features of the S12XS chip family in secure mode are Protect the content of non volatile memories Flash EEPROM Execution of NVM commands is restricted Disable access to internal memory via background debug module BDM Table 7 2 gives an overview over availabi...

Page 232: ...nto the Flash security register FSEC during a reset sequence The meaning of the bits KEYEN 1 0 is shown in Table 7 3 Please refer to Section 7 1 5 1 Unsecuring the MCU Using the Backdoor Key Access for more information The meaning of the security bits SEC 1 0 is shown in Table 7 4 For security reasons the state of device security is controlled by two bits To put the device in unsecured mode these ...

Page 233: ...rstood that the security of the EEPROM and Flash memory contents also depends on the design of the application program For example if the application has the capability of downloading code through a serial port and then executing that code e g an application containing bootloader code then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcon...

Page 234: ... depends on the security state of the device The BDM secure firmware first performs a blank check of both the Flash memory and the EEPROM If the blank check succeeds security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails security will remain active only the BDM hardware commands will be enabled and...

Page 235: ... Flash This is particularly useful for failure analysis NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF 7 1 6 Reprogramming the Security Bits In normal single chip mode NS security can also be disabled by erasing and reprogramming the security bits within Flash options security byte to the unsecured value Because the erase operation will erase the entire sector from ...

Page 236: ...EPROM or Flash memory address is not erased only BDM hardware commands are enabled BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks When next reset into special single chip mode the BDM firmware will again verify whether all EEPROM and Flash memory are erased and this being the case will enable all BDM commands a...

Page 237: ...om Stop in Self Clock Mode for power saving and immediate program execution Clock switch for either Oscillator or PLL based system clocks Computer Operating Properly COP watchdog timer with time out clear window Table 8 1 Revision History Revision Number Revision Date Sections Affected Description of Changes V01 00 26 Oct 2005 Initial release V01 01 02 Nov 2006 8 4 1 1 8 254 Table Examples of IPLL...

Page 238: ...P 0 and Pseudo Stop Mode PSTP 1 Full Stop Mode The oscillator is disabled and thus all system and core clocks are stopped The COP and the RTI remain frozen Pseudo Stop Mode The oscillator continues to run and most of the system and core clocks are stopped If the respective enable bits are set the COP and RTI will continue to run else they remain frozen Self Clock Mode Self Clock Mode will be enter...

Page 239: ...PLL and VSSPLL must be connected to properly 8 2 2 RESET RESET is an active low bidirectional reset pin As an input it initializes the MCU asynchronously to a known start up state As an open drain output it indicates that an system reset internal to MCU has been triggered ICRG Registers COP RESET RTI IPLL VDDPLL VSSPLL EXTAL XTAL Bus Clock System Reset Oscillator Clock PLLCLK OSCCLK Core Clock CM ...

Page 240: ...R R VCOFRQ 1 0 SYNDIV 5 0 W 0x0001 REFDV R REFFRQ 1 0 REFDIV 5 0 W 0x0002 POSTDIV R 0 0 0 POSTDIV 4 0 W 0x0003 CRGFLG R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM W 0x0004 CRGINT R RTIE 0 0 LOCKIE 0 0 SCMIE 0 W 0x0005 CLKSEL R PLLSEL PSTP XCLKS 0 PLLWAI 0 RTIWAI COPWAI W 0x0006 PLLCTL R CME PLLON FM1 FM0 FSTWKP PRE PCE SCME W 0x0007 RTICTL R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W 0x0008 COPCTL ...

Page 241: ...ust not exceed the specified maximum If POSTDIV 00 then fPLL is same as fVCO divide by one The VCOFRQ 1 0 bit are used to configure the VCO gain for optimal stability and lock time For correct IPLL operation the VCOFRQ 1 0 bits have to be selected according to the actual target VCOCLK frequency as shown in Table 8 2 Setting the VCOFRQ 1 0 bits wrong can result in a non functional IPLL no locking a...

Page 242: ...ding to the actual REFCLK frequency as shown in Figure 8 3 Setting the REFFRQ 1 0 bits wrong can result in a non functional IPLL no locking and or insufficient stability 8 3 2 3 S12XECRG Post Divider Register POSTDIV The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK The count in the final divider divides VCOCLK frequency by 1 or 2 POSTDIV Note that if POSTDIV 00 fPLL ...

Page 243: ... 3 2 1 0 R 0 0 0 POSTDIV 4 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 5 S12XECRG Post Divider Register POSTDIV Module Base 0x0003 7 6 5 4 3 2 1 0 R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM W Reset 0 Note 1 Note 2 Note 3 0 0 0 0 1 PORF is set to 1 when a power on reset occurs Unaffected by system reset 2 LVRF is set to 1 when a low voltage reset occurs Unaffected by system reset ...

Page 244: ...F causes an interrupt request 0 No change in LOCK bit 1 LOCK bit has changed 3 LOCK Lock Status Bit LOCK reflects the current state of IPLL lock condition This bit is cleared in Self Clock Mode Writes have no effect 0 VCOCLK is not within the desired tolerance of the target frequency 1 VCOCLK is within the desired tolerance of the target frequency 2 ILAF Illegal Address Reset Flag ILAF is set to 1...

Page 245: ...tions Field Description 7 RTIE Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled 1 Interrupt will be requested whenever RTIF is set 4 LOCKIE Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled 1 Interrupt will be requested whenever LOCKIF is set 1 SCMIE Self Clock Mode Interrupt Enable Bit 0 SCM interrupt requests are disabled 1 Interrupt will be requested when...

Page 246: ...covery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption 5 XCLKS Oscillator Configuration Status Bit This read only bit shows the oscillator configuration status 0 Loop controlled Pierce Oscillator is selected 1 External clock full swing Pierce Oscillator is selected 3 PLLWAI PLL Stops in Wait M...

Page 247: ...CME 0 this bit has no effect 0 Fast wake up from full stop mode is disabled 1 Fast wake up from full stop mode is enabled When waking up from full stop mode the system will immediately resume operation in Self Clock Mode see Section 8 4 1 4 Clock Quality Checker The SCMIF flag will not be set The system will remain in Self Clock Mode with oscillator and clock monitor disabled until FSTWKP bit is c...

Page 248: ...ons Field Description 7 RTDEC Decimal or Binary Divider Select Bit RTDEC selects decimal or binary based prescaler values 0 Binary based divider value See Table 8 10 1 Decimal based divider value See Table 8 11 6 4 RTR 6 4 Real Time Interrupt Prescale Rate Select Bits These bits select the prescale rate for the RTI See Table 8 10 and Table 8 11 3 0 RTR 3 0 Real Time Interrupt Modulus Counter Selec...

Page 249: ...6 1101 14 OFF 14x210 14x211 14x212 14x213 14x214 14x215 14x216 1110 15 OFF 15x210 15x211 15x212 15x213 15x214 15x215 15x216 1111 16 OFF 16x210 16x211 16x212 16x213 16x214 16x215 16x216 1 Denotes the default value out of reset This value should be used to disable the RTI to ensure future backwards compatibility Table 8 11 RTI Frequency Divide Rates for RTDEC 1 RTR 3 0 RTR 6 4 000 1x103 001 2x103 01...

Page 250: ...450x103 900x103 1 8x106 1001 10 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106 1010 11 11 x103 22x103 55x103 110x103 220x103 550x103 1 1x106 2 2x106 1011 12 12x103 24x103 60x103 120x103 240x103 600x103 1 2x106 2 4x106 1100 13 13x103 26x103 65x103 130x103 260x103 650x103 1 3x106 2 6x106 1101 14 14x103 28x103 70x103 140x103 280x103 700x103 1 4x106 2 8x106 1110 15 15x103 30x103 75x103 150x...

Page 251: ...TI counters whenever the part is in Active BDM mode 5 WRTMASK Write Mask for WCOP and CR 2 0 Bit This write only bit serves as a mask for the WCOP and CR 2 0 bits while writing the COPCTL register It is intended for BDM writing the RSBCK without touching the contents of WCOP and CR 2 0 0 Write of WCOP and CR 2 0 has an effect with this write of COPCTL 1 Write of WCOP and CR 2 0 has no effect with ...

Page 252: ... designed for factory test purposes only and is not intended for general user access Writing to this register when in special test modes can alter the S12XECRG s functionality Read Always read 00 except in special modes 1 1 1 2 24 1 OSCCLK cycles are referenced from the previous COP time out reset writing 55 AA to the ARMCOP register Module Base 0x0009 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0...

Page 253: ... AA causes a COP reset To restart the COP time out period you must write 55 followed by a write of AA Other instructions may be executed between these writes but the sequence 55 AA must be completed prior to COP end of time out period to avoid a COP reset Sequences of 55 writes or sequences of AA writes are allowed When the WCOP bit is set 55 and AA writes must be done in the last 25 of the select...

Page 254: ... in a range of 1 2 4 6 8 to 62 to generate the PLLCLK NOTE Although it is possible to set the dividers to command a very high clock frequency do not exceed the specified bus frequency limit for the MCU If PLLSEL 1 then fBUS fPLL 2 IF POSTDIV 00 the fPLL is identical to fVCO divide by one Several examples of IPLL divider settings are shown in Table 8 14 Shaded rows indicated that these settings are...

Page 255: ...ed on this comparison If IPLL LOCK interrupt requests are enabled the software can wait for an interrupt request and then check the LOCK bit If interrupt requests are disabled software can poll the LOCK bit continuously during IPLL start up usually or at periodic intervals In either case only when the LOCK bit is set the PLLCLK can be selected as the source for the system and core clocks If the IP...

Page 256: ...ed to generate the clock visible at the ECLK pin The Core Clock signal is the clock for the CPU The Core Clock is twice the Bus Clock But note that a CPU cycle corresponds to one Bus Clock IPLL clock mode is selected with PLLSEL bit in the CLKSEL register When selected the IPLL output clock drives SYSCLK for the main system including the CPU and peripherals The IPLL cannot be turned off by clearin...

Page 257: ... Clock Quality Checker The clock monitor performs a coarse check on the incoming clock signal The clock quality checker provides a more accurate check in addition to the clock monitor A clock quality check is triggered by any of the following events Power on reset POR Low voltage reset LVR Wake up from Full Stop Mode exit full stop Clock Monitor fail indication CM fail A time window of 50000 PLLCL...

Page 258: ...e OSCCLK signal NOTE The Clock Quality Checker enables the IPLL and the voltage regulator VREG anytime a clock check has to be performed An ongoing clock quality check could also cause a running IPLL fSCM and an active VREG during Pseudo Stop Mode 1 A Clock Monitor Reset will always set the SCME bit to logical 1 CHECK WINDOW OSC OK SCM ACTIVE SWITCH TO OSCCLK EXIT SCM CLOCK OK NUM 50 NUM 0 NUM NUM...

Page 259: ...mature write will immediately reset the part If PCE bit is set the COP will continue to run in Pseudo Stop Mode 8 4 1 6 Real Time Interrupt RTI The RTI can be used to generate a hardware interrupt at a fixed periodic rate If enabled by setting RTIE 1 this interrupt will occur at the rate selected by the RTICTL register The RTI runs with a gated OSCCLK At the end of the RTI time out period the RTIF...

Page 260: ...ect bits to zero The COP can be stopped by setting the associated rate select bits to zero 8 4 3 2 Wait Mode The WAI instruction puts the MCU in a low power consumption stand by mode depending on setting of the individual bits in the CLKSEL register All individual Wait Mode configuration bits can be superposed This provides enhanced granularity in reducing the level of power consumption during Wai...

Page 261: ...from Self Clock Mode the ongoing clock quality check will be stopped A complete timeout window check will be started when Stop Mode is left again There are two ways to restart the MCU from Stop Mode 1 Any reset 2 Any interrupt If the MCU is woken up from Full Stop Mode by an interrupt and the fast wake up feature is enabled FSTWKP 1 and SCME 1 the system will immediately no clock quality check res...

Page 262: ...ne External Reset None Illegal Address Reset None Clock Monitor Reset PLLCTL CME 1 SCME 0 Oscillator Clock PLL Clock Core Clock Instruction STOP IRQ service FSTWKP 1 IRQ service STOP STOP IRQ service Oscillator Disabled Power Saving Self Clock Mode SCME 1 CPU resumes program execution immediately Interrupt Interrupt Interrupt Oscillator Clock PLL Clock Core Clock Instruction Clock Quality Check ST...

Page 263: ...y n 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency After 128 n SYSCLK cycles the RESET pin is released The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source Table 8 17 shows which vector will be fetched NOTE External circuitry connected to the RESET pin should be able to raise ...

Page 264: ...l the clock quality check starts As soon as clock quality check indicates a valid Oscillator Clock the S12XECRG switches to OSCCLK and leaves Self Clock Mode Since the clock quality checker is running in parallel to the reset generator the S12XECRG may leave Self Clock Mode while still completing the internal reset sequence 8 5 1 2 Computer Operating Properly Watchdog COP Reset When COP is enabled...

Page 265: ...when the RESET pin is tied to VDD and when the RESET pin is held low Figure 8 22 RESET Pin Tied to VDD by a Pull up Resistor Figure 8 23 RESET Pin Held Low Externally 8 6 Interrupts The interrupts reset vectors requested by the S12XECRG are listed in Table 8 18 Refer to MCU specification for related vector addresses and priorities Table 8 18 S12XECRG Interrupt Vectors Interrupt Source CCR Mask Loc...

Page 266: ...te to an unlocked state or vice versa Lock interrupts are locally disabled by setting the LOCKIE bit to zero The IPLL Lock interrupt flag LOCKIF is set to1 when the LOCK condition has changed and is cleared to 0 by writing a 1 to the LOCKIF bit 8 6 1 3 Self Clock Mode Interrupt The S12XECRG generates a Self Clock Mode interrupt when the SCM condition of the system has changed either entered or exi...

Page 267: ...ed dynamically Transconductance gm sized for optimum start up margin for typical oscillators Dynamic gain control eliminates the need for external current limiting resistor Integrated resistor eliminates the need for external bias resistor in loop controlled Pierce mode Low power consumption Operates from 1 8 V nominal supply Amplitude control limits power Clock monitor 9 1 2 Modes of Operation Tw...

Page 268: ...ltage VDDPLL and ground VSSPLL for the XOSC circuitry This allows the supply voltage to the XOSC to use an independent bypass capacitor 9 2 2 EXTAL and XTAL Input and Output Pins These pins provide the interface for either a crystal or a 1 8V CMOS compatible clock to control the internal clock generator circuitry EXTAL is the external clock input or the input to the crystal oscillator amplifier XT...

Page 269: ...and crystals Figure 9 2 Loop Controlled Pierce Oscillator Connections LCP mode selected NOTE Full swing Pierce circuit is not suited for overtone resonators and crystals without a careful component selection Figure 9 3 Full Swing Pierce Oscillator Connections FSP mode selected Figure 9 4 External Clock Connections FSP mode selected MCU EXTAL XTAL VSSPLL Crystal or Ceramic Resonator C2 C1 Rs can be...

Page 270: ...control system will be utilized whereby the amplifier is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude The output peak to peak voltage will be kept above twice the maximum hysteresis level of the input buffer Electrical specification details are provided in the Electrical Characteristics appendix 9 4 2 Clock Monitor The clock monitor circuit is based on an...

Page 271: ...rogrammable sample time Left right justified result data External trigger control Sequence complete interrupt Analog input multiplexer for 16 analog input channels Special conversions for VRH VRL VRL VRH 2 1 to 16 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on any AD channel or any of four additional trigger inputs The f...

Page 272: ...e all flags are cleared etc ICLKSTP 1 in ATDCTL2 register A D conversion sequence seamless continues in Stop Mode based on the internally generated clock ICLK as ATD clock For conversions during transition from Run to Stop Mode or vice versa the result is not written to the results register no CCF flag is set and no compare is done When converting in Stop Mode ICLKSTP 1 an ATD Stop Recovery time t...

Page 273: ...lts ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample Hold VDDA VRL VRH Sequence Complete Comparator Clock Prescaler Bus Clock ATD Clock ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ETRIG0 See device specifi cation for availability ETRIG1 ETRIG2 ETRIG3 and connectivity Timing Control ATDDIEN ATDCTL1 Trigger Mux...

Page 274: ...Pin 4 Pin 8 Pin 12 channel 16 channel 20 Pin 5 Pin 9 Pin 13 channel 17 channel 21 Pin 1 Pin 6 Pin 10 Pin 14 channel 18 channel 22 Pin 2 Pin 7 Pin 11 Pin 15 channel 19 channel 23 Pin 3 VRL 6pF S H cap to comparator 6pF Pin 0 sample channel select 1st stage channel select 2nd stage A D channel MUX in sum 4pF ch 4 0 SC CD CC CB CA bits of ATDCTL5 register ch 1 0 11 ch 1 0 10 ch 1 0 01 ch 1 0 00 ch 4 ...

Page 275: ...external trigger for the ATD conversion Refer to device specification for availability and connection of these inputs 10 2 1 3 VRH VRL VRH is the high reference voltage VRL is the low reference voltage for ATD conversion 10 2 1 4 VDDA VSSA These pins are the power supplies for the analog circuitry of the ADC12B16C block 10 3 Memory Map and Register Definition This section provides a detailed descr...

Page 276: ...CMPHT 7 0 W 0x0010 ATDDR0 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0012 ATDDR1 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0014 ATDDR2 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Da...

Page 277: ...See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0028 ATDDR12 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x002A ATDDR13 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x002C ATDDR14 ...

Page 278: ...P1 WRAP0 Multiple Channel Conversions MULT 1 Wraparound to AN0 after Converting 0 0 0 0 Reserved1 1 If only AN0 should be converted use MULT 0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15 Module Base 0x0001 7 6 5 4 3 2 1 0 R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIG...

Page 279: ...SMP_DIS Discharge Before Sampling Bit 0 No discharge before sampling 1 The internal sample capacitor is discharged before sampling the channel This adds 2 ATD clock cycles to the sampling time This can help to detect an open circuit instead of measuring the previous sampled channel 3 0 ETRIGCH 3 0 External Trigger Channel Select These bits select one of the AD channels or one of the ETRIG3 0 input...

Page 280: ...it This bit enables A D conversions in stop mode When going into stop mode and ICLKSTP 1 the ATD conversion clock is automatically switched to the internally generated clock ICLK Current conversion sequence will seamless continue Conversion speed will change from prescaled bus frequency to the ICLK frequency see ATD Electrical Characteristics in device description The prescaler bits PRS4 0 in ATDC...

Page 281: ...in stop mode 0 Disable external trigger 1 Enable external trigger 1 ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled 1 ATD Sequence Complete interrupt will be requested whenever SCF 1 is set 0 ACMPIE ATD Compare Interrupt Enable If automatic compare is enabled for conversion n CMPE n 1 in ATDCMPE register this bit enables the compare interrupt If...

Page 282: ...ches the end of the result register file The conversion counter value CC3 0 in ATDSTAT0 can be used to determine where in the result register file the current conversion result will be placed Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO 1 So the first result of a new conversion sequence started by writing to ATDCTL5 will always be place in the first...

Page 283: ...0 010 0 008 0 006 0 004 0 003 0 002 0 000 255 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 4 4 4 3 3 2 2 2 1 1 0 0 0 4095 17 16 14 12 11 9 8 6 4 3 2 1 0 Table 10 11 Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 ...

Page 284: ...lect the length of the sample time in units of ATD conversion clock cycles Note that the ATD conversion clock period is itself a function of the prescaler value bits PRS4 0 Table 10 14 lists the available sample time lengths 4 0 PRS 4 0 ATD Clock Prescaler These 5 bits are the binary prescaler value PRS The ATD conversion clock frequency is calculated as follows Refer to Device Specification for a...

Page 285: ...el Sample Mode When MULT is 0 the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence The analog channel is selected by channel selection code control bits CD CC CB CA located in ATDCTL5 When MULT is 1 the ATD sequence controller samples across channels The number of channels sampled is determined by the sequence length value S8C S4C S2C S...

Page 286: ...ng SC CD CC CB CA Analog Input Channel 0 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15 1 0 0 0 0 Reserved 0 0 0 1 Reserved 0 0 1 X Reserved 0 1 0 0 VRH 0 1 0 1 VRL 0 1 1 0 VRH VRL 2 0 1 1 1 Reserved 1 X X X Reserved Module Base 0x0006 7 6 5 4 3 2 1...

Page 287: ... Register Over Run Flag This bit indicates that a result register has been written to before its associated conversion complete flag CCF has been cleared This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels However it is also practical for non FIFO modes and indicates that a result register has been o...

Page 288: ... n 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 of a Sequence These bits enable automatic compare of conversion results individually for conversions of a sequence The sense of each comparison is determined by the CMPHT n bit in the ATDCMPHT register For each conversion number with CMPE n 1 do the following 1 Write compare value to ATDDRn result register 2 Write compare operator with CMPHT n in ATDCPMHT r...

Page 289: ...ion in a sequence is complete and the result is available in ATDDR9 and so forth If automatic compare of conversion results is enabled CMPE n 1 in ATDCMPE the conversion complete flag is only set if comparison with ATDDRn is true and if ACMPIE 1 a compare interrupt will be requested In this case as the ATDDRn result register is used to hold the compare value the result will not be stored there at ...

Page 290: ... input buffer to ANx pin 1 Enable digital input buffer on ANx pin Note Setting this bit will enable the corresponding digital input buffer continuously If this bit is set while simultaneously using it as an analog port there is potentially increased power consumption because the digital input buffer maybe in the linear region Module Base 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CMPHT 15 0 W ...

Page 291: ... 12 2 Right Justified Result Data DJM 1 Table 10 16 shows how depending on the A D resolution the conversion result is transferred to the ATD result registers Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn Module Base 0x0010 ATDDR0 0x0012 ATDDR1 0x0014 ATDDR2 0x0016 ATDDR3 0x0018 ATDDR4 0x001A ATDDR5 0x001C ATDDR6 0x001E ATDDR7 0x0020 ATDDR8 ...

Page 292: ...t is disconnected from the storage node 10 4 1 2 Analog Input Multiplexer The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine 10 4 1 3 Analog to Digital A D Machine The A D Machine performs analog to digital conversions The resolution is program selectable at either 8 or 10 or 12 bits The A D machine uses a successive approximation arch...

Page 293: ...additional active edges are detected the overrun error flag ETORF is set In either level or edge triggered modes the first conversion begins when the trigger is received Once ETRIGE is enabled conversions cannot be started by a write to ATDCTL5 but rather must be triggered externally If the level mode is active and the external trigger both de asserts and re asserts itself during a conversion sequ...

Page 294: ...r off with the ATDDIEN register This is important so that the buffer does not draw excess current when analog potentials are presented at its input 10 5 Resets At reset the ADC12B16C is in a power down state The reset state of each individual bit is listed within the Register Description section see Section 10 3 2 Register Descriptions which details the registers and their bit field 10 6 Interrupt...

Page 295: ...irst to familiarize the reader with the terms and concepts contained within this document Though not exclusively intended for automotive applications CAN protocol is designed to meet the specific requirements of a vehicle serial data bus real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth MSCAN uses an advanced buffer arrangement re...

Page 296: ... Out Memory IFS Inter Frame Sequence SOF Start of Frame CPU bus CPU related read write data bus CAN bus CAN protocol related serial bus oscillator clock Direct clock from external oscillator bus clock CPU bus related clock CAN clock CAN protocol related clock RXCAN TXCAN Receive Transmit Engine Message Filtering and Buffering Control and Status Wake Up Interrupt Req Errors Interrupt Req Receive In...

Page 297: ...grammable wake up functionality with integrated low pass filter Programmable loopback mode supports self test operation Programmable listen only mode for monitoring of CAN bus Programmable bus off recovery functionality Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states warning error passive bus off Programmable MSCAN clock source either bus clock or o...

Page 298: ...N is the MSCAN receiver input pin 11 2 2 TXCAN CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin The TXCAN output pin represents the logic level on the CAN bus 0 Dominant state 1 Recessive state 11 2 3 CAN System A typical CAN system with MSCAN is shown in Figure 11 2 Each CAN station is connected physically to the CAN bus lines through a transceiver device The transceiver is ca...

Page 299: ...memory map The register address results from the addition of base address and address offset The base address is determined at the MCU level and can be found in the MCU memory map description The address offset is defined at the module level The MSCAN occupies 64 bytes in the memory space The base address of the MSCAN module is determined at the MCU level when the MCU is defined The register decod...

Page 300: ...FLG R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0005 CANRIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0006 CANTFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0007 CANTIER R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W 0x0008 CANTARQ R 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 W 0x0009 CANTAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W 0x000A CANTBSEL R 0 0 0 0 0 TX2 TX1 TX0 W 0x000B CANIDAC R 0 0 IDAM1 IDAM...

Page 301: ...the MSCAN module as described below 0x000F CANTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0010 0x0013 CANIDAR0 3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x0014 0x0017 CANIDMRx R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0018 0x001B CANIDAR4 7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x001C 0x001F CANIDMR4 7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0020 0x002F CANRXFG R See Section 11 3 3 Pro...

Page 302: ...lost 5 CSWAI 2 CAN Stops in Wait Mode Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode 4 SYNCH Synchronized Status This read only flag indicates whether the MSCAN is synchronized to the CAN bus and able to partici...

Page 303: ...ialization mode INITRQ 1 and INITAK 1 The values of the error counters are not affected by initialization mode When this bit is cleared by the CPU the MSCAN restarts and then tries to synchronize to the CAN bus If the MSCAN is not in bus off state it synchronizes after 11 consecutive recessive bits on the CAN bus if the MSCAN is in bus off state it continues to wait for 128 occurrences of 11 conse...

Page 304: ...N behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node In this state the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message Both transmit and receive interrupts are generated 0 Loopback self test disabled 1 Loopback self test enabled 4 LISTEN Listen ...

Page 305: ...AK 1 The registers CANCTL1 CANBTR0 CANBTR1 CANIDAC CANIDAR0 CANIDAR7 and CANIDMR0 CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode 0 Running The MSCAN operates normally 1 Initialization mode active The MSCAN has entered initialization mode Module Base 0x0002 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6 5 4 3 ...

Page 306: ...P Sampling This bit determines the number of CAN bus samples taken per bit time 0 One sample per bit 1 Three samples per bit 1 If SAMP 0 the resulting bit value is equal to the value of the single bit positioned at the sample point If SAMP 1 the resulting bit value is determined by using majority rule on the three total samples For higher bit rates it is recommended that only one sample is taken p...

Page 307: ...ent 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle 1 1 This setting is not valid Please refer to Table 11 37 for valid settings 0 0 1 2 Tq clock cycles 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles Table 11 10 Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle 1 1 This setting is not valid Please refer to Table 11 37 for valid settings ...

Page 308: ...s the system on the actual CAN bus status see Section 11 3 2 6 MSCAN Receiver Interrupt Enable Register CANRIER If not masked an error interrupt is pending while this flag is set CSCIF provides a blocking interrupt That guarantees that the receiver transmitter status bits RSTAT TSTAT are only updated when no CAN status change interrupt is pending If the TECs RECs change their current value after t...

Page 309: ...that message from the RxFG buffer in the receiver FIFO the RXF flag must be cleared to release the buffer A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer RxFG If not masked a receive interrupt is pending while this flag is set 0 No new message available within the RxFG 1 The receiver FIFO is not empty A new message is available in the RxFG 1 Redundant Inform...

Page 310: ...tate Discard other receiver state changes for generating CSCIF interrupt 11 Generate CSCIF interrupt on all state changes 2 Bus off state is only defined for transmitters by the CAN standard see Bosch CAN 2 0A B protocol specification Because the only possible state change for the transmitter from bus off to TxOK also forces the receiver to skip its current state to RxOK the coding of the RXSTAT 1...

Page 311: ...for transmission The MSCAN sets the flag after the message is sent successfully The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request see Section 11 3 2 9 MSCAN Transmitter Message Abort Request Register CANTARQ If not masked a transmit interrupt is pending while this flag is set Clearing a TXEx flag also clears the corresponding ABT...

Page 312: ...tter empty transmit buffer available for transmission event causes a transmitter empty interrupt request Module Base 0x0008 Access User read write 1 1 Read Anytime Write Anytime when not in initialization mode 7 6 5 4 3 2 1 0 R 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 12 MSCAN Transmitter Message Abort Request Register CANTARQ Table 11 15 CANTARQ Register Fiel...

Page 313: ...0 0 0 ABTAK2 ABTAK1 ABTAK0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 13 MSCAN Transmitter Message Abort Acknowledge Register CANTAAK Table 11 16 CANTAAK Register Field Descriptions Field Description 2 0 ABTAK 2 0 Abort Acknowledge This flag acknowledges that a message was aborted due to a pending abort request from the CPU After a particular message buffer is flagged empty this flag can be u...

Page 314: ...110 STAA CANTBSEL value written is 0b0000_0110 LDAA CANTBSEL value read is 0b0000_0010 If all transmit message buffers are deselected no accesses are allowed to the CANTXFG registers 11 3 2 12 MSCAN Identifier Acceptance Control Register CANIDAC The CANIDAC register is used for identifier acceptance control as described below Table 11 17 CANTBSEL Register Field Descriptions Field Description 2 0 T...

Page 315: ...on see Section 11 4 3 Identifier Acceptance Filter Table 11 19 summarizes the different settings In filter closed mode no message is accepted such that the foreground buffer is never reloaded 2 0 IDHIT 2 0 Identifier Acceptance Hit Indicator The MSCAN sets these flags to indicate an identifier acceptance hit see Section 11 4 3 Identifier Acceptance Filter Table 11 20 summarizes the different setti...

Page 316: ... 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 16 MSCAN Reserved Register Module Base 0x000D Access User read write 1 1 Read Anytime Write Anytime write of 1 clears flag write of 0 ignored 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 BOHOLD W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 17 MSCAN Miscellaneous Register CANMISC Table 11 21 CANMISC Register Field Descriptions Field Desc...

Page 317: ...an incorrect value For MCUs with dual CPUs this may result in a CPU fault condition Writing to this register when in special modes can alter the MSCAN functionality Module Base 0x000E Access User read write 1 1 Read Only when in sleep mode SLPRQ 1 and SLPAK 1 or initialization mode INITRQ 1 and INITAK 1 Write Unimplemented 7 6 5 4 3 2 1 0 R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W...

Page 318: ...st two CANIDAR0 1 CANIDMR0 1 are applied Module Base 0x0010 to Module Base 0x0013 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 Figure 11 20 MSCAN Identifier Acceptance Registers First Bank CANIDAR0 CANIDAR3 Table 11 22 CANIDAR0 CANIDAR3 Register Field Descriptions Field D...

Page 319: ...n masked with the corresponding identifier mask register Module Base 0x0014 to Module Base 0x0017 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 Figure 11 22 MSCAN Identifier Mask Registers First Bank CANIDMR0 CANIDMR3 Table 11 24 CANIDMR0 CANIDMR3 Register Field Descriptio...

Page 320: ...ion of a message This feature is only available for transmit and receiver buffers if the TIME bit is set see Section 11 3 2 1 MSCAN Control Register 0 CANCTL0 The time stamp register is written by the MSCAN The CPU can only read these registers 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 Table 11 25 CANIDMR4 CANIDMR7 Register Field Descriptions Field Description 7 0 A...

Page 321: ...er Organization Offset Address Register Access 0x00X0 Identifier Register 0 R W 0x00X1 Identifier Register 1 R W 0x00X2 Identifier Register 2 R W 0x00X3 Identifier Register 3 R W 0x00X4 Data Segment Register 0 R W 0x00X5 Data Segment Register 1 R W 0x00X6 Data Segment Register 2 R W 0x00X7 Data Segment Register 3 R W 0x00X8 Data Segment Register 4 R W 0x00X9 Data Segment Register 5 R W 0x00XA Data...

Page 322: ...17 ID16 ID15 W 0x00X2 IDR2 R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W 0x00X3 IDR3 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W 0x00X4 DSR0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X5 DSR1 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X6 DSR2 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X7 DSR3 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X8 DSR4 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X9 DSR5 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB...

Page 323: ... is selected in CANTBSEL see Section 11 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Unimplemented for receive buffers Reset Undefined because of RAM based implementation 11 3 3 1 Identifier Registers IDR0 IDR3 The identifier registers for an extended format identifier consist of a total of 32 bits ID 28 0 SRR IDE and RTR The identifier registers for a standard format identifier consis...

Page 324: ...ed Format Identifier The identifiers consist of 29 bits ID 28 0 for the extended format ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure The priority of an identifier is defined to be highest for the smallest binary number 4 SRR Substitute Remote Request This fixed recessive bit is used only in extended format It must be set to 1 by the user...

Page 325: ... 4 3 2 1 0 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset x x x x x x x x Figure 11 29 Identifier Register 3 IDR3 Extended Identifier Mapping Table 11 30 IDR3 Register Field Descriptions Extended Field Description 7 1 ID 6 0 Extended Format Identifier The identifiers consist of 29 bits ID 28 0 for the extended format ID28 is the most significant bit and is transmitted first on the CAN bus during the ar...

Page 326: ...ons Field Description 7 5 ID 2 0 Standard Format Identifier The identifiers consist of 11 bits ID 10 0 for the standard format ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure The priority of an identifier is defined to be highest for the smallest binary number See also ID bits in Table 11 31 4 RTR Remote Transmission Request This flag refle...

Page 327: ...nding DLR register Module Base 0x00X2 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 11 32 Identifier Register 2 Standard Mapping Module Base 0x00X3 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 11 33 Identifier Register 3 Standard Mapping Module Base 0x00X4 to Module Base 0x00XB 7 6 5 4 3 2 1 0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W Reset x x x x x x x ...

Page 328: ...immediately before the SOF start of frame is sent Module Base 0x00XC 7 6 5 4 3 2 1 0 R DLC3 DLC2 DLC1 DLC0 W Reset x x x x x x x x Unused always read x Figure 11 35 Data Length Register DLR Extended Identifier Mapping Table 11 34 DLR Register Field Descriptions Field Description 3 0 DLC 3 0 Data Length Code Bits The data length code contains the number of bytes data byte count of the respective me...

Page 329: ...e The CPU can only read the time stamp registers Module Base 0x00XD Access User read write 1 1 Read Anytime when TXEx flag is set see Section 11 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer is selected in CANTBSEL see Section 11 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Write Anytime when TXEx flag is set see Section 11 3 2 7 MSCAN Transmitter ...

Page 330: ... Anytime when TXEx flag is set see Section 11 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer is selected in CANTBSEL see Section 11 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Write Unimplemented 7 6 5 4 3 2 1 0 R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 W Reset x x x x x x x x Figure 11 38 Time Stamp Register Low Byte TSRL ...

Page 331: ...n 11 4 1 General This section provides a complete functional description of the MSCAN 11 4 2 Message Storage Figure 11 39 User Model for Message Buffer Organization MSCAN Rx0 Rx1 CAN Receive Transmit Engine Memory Mapped I O CPU bus MSCAN Tx2 TXE2 PRIO Receiver Transmitter RxBG TxBG Tx0 TXE0 PRIO TxBG Tx1 PRIO TXE1 TxFG CPU bus Rx2 Rx3 Rx4 RXF RxFG ...

Page 332: ...ffer No buffer would then be ready for transmission and the CAN bus would be released At least three transmit buffers are required to meet the first of the above requirements under all circumstances The MSCAN has three transmit buffers The second requirement calls for some sort of internal prioritization which the MSCAN implements with the local priority concept described in Section 11 4 2 2 Trans...

Page 333: ...are already in transmission cannot be aborted the user must request the abort by setting the corresponding abort request bit ABTRQ see Section 11 3 2 9 MSCAN Transmitter Message Abort Request Register CANTARQ The MSCAN then grants the request if possible by 1 Setting the corresponding abort acknowledge flag ABTAK in the CANTAAK register 2 Setting the associated TXE flag to release the buffer 3 Gen...

Page 334: ...transmit messages while the receiver FIFO is being filled but all incoming messages are discarded As soon as a receive buffer in the FIFO is available again new valid messages will be accepted 11 4 3 Identifier Acceptance Filter The MSCAN identifier acceptance registers see Section 11 3 2 12 MSCAN Identifier Acceptance Control Register CANIDAC define the acceptable patterns of the standard or exte...

Page 335: ...er 2 and 3 hits Eight identifier acceptance filters each to be applied to the first 8 bits of the identifier This mode implements eight independent filters for the first 8 bits of a CAN 2 0A B compliant standard identifier or a CAN 2 0B compliant extended identifier Figure 11 42 shows how the first 32 bit filter bank CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 produces filter 0 to 3 hits Similarly the sec...

Page 336: ...ance Filters ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDMR1 ID Accepted Filter 0 Hit AC7 AC0 CANIDAR2 AM7 AM0 CANIDMR2 AC7 AC0 CANIDAR3 AM7 AM0 CANIDMR3 ID Accepted Filter 1 Hit CAN 2 0B Extended Identifier CAN 2 0A B Standard Identifier ...

Page 337: ...2 0B Extended Identifier CAN 2 0A B Standard Identifier AC7 AC0 CIDAR3 AM7 AM0 CIDMR3 ID Accepted Filter 3 Hit AC7 AC0 CIDAR2 AM7 AM0 CIDMR2 ID Accepted Filter 2 Hit AC7 AC0 CIDAR1 AM7 AM0 CIDMR1 ID Accepted Filter 1 Hit ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CIDAR0 AM7 AM0 CIDMR0 ID Accepted Filter 0 Hit ...

Page 338: ...he TXCAN is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode see Section 11 4 5 6 MSCAN Power Down Mode and Section 11 4 4 5 MSCAN Initialization Mode The MSCAN enable bit CANE is writable only once in normal system operation modes which provides further protection against inadvertently disabling the MSCAN 11 4 3 2 Clock System Figure 11 4...

Page 339: ...egment has a fixed length of one time quantum Signal edges are expected to happen within this section Time Segment 1 This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta Time Segment 2 This segment represents the PHASE_SEG2 of the CAN standard It can be programmed by setting the TSEG2 paramet...

Page 340: ...liance with the CAN standard 11 4 4 Modes of Operation 11 4 4 1 Normal System Operating Modes The MSCAN module behaves as described within this specification in all normal system operating modes Write restrictions exist for some registers Table 11 36 Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the CAN bus during this period Transmit Point A node in transm...

Page 341: ...N Initialization Mode The MSCAN enters initialization mode when it is enabled CANE 1 When entering initialization mode during operation any on going transmission or reception is immediately aborted and synchronization to the CAN bus is lost potentially causing CAN protocol violations To protect the CAN bus system from fatal consequences of violations the MSCAN immediately drives TXCAN into a reces...

Page 342: ...or the request INITRQ to go into initialization mode NOTE The CPU cannot clear INITRQ before initialization mode INITRQ 1 and INITAK 1 is active 11 4 5 Low Power Options If the MSCAN is disabled CANE 0 the MSCAN clocks are stopped for power saving If the MSCAN is enabled CANE 1 the MSCAN has two additional modes with reduced power consumption compared to normal mode sleep and power down mode In sl...

Page 343: ...round debug mode 11 4 5 3 Operation in Stop Mode The STOP instruction puts the MCU in a low power consumption stand by mode In stop mode the MSCAN is set in power down mode regardless of the value of the SLPRQ SLPAK and CSWAI bits Table 11 38 11 4 5 4 MSCAN Normal Mode This is a non power saving mode Enabling the MSCAN puts the module from disabled mode into normal mode In this mode the module can...

Page 344: ... or more TXEx flag s and immediately request sleep mode by setting SLPRQ Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations If sleep mode is active the SLPRQ and SLPAK bits are set Figure 11 46 The application software must use SLPAK as a handshake indication for the request SLPRQ to go into sleep mode When in sleep mode SLPRQ 1 and S...

Page 345: ... MSCAN remains in bus off state after sleep mode was exited it continues counting the 128 occurrences of 11 consecutive recessive bits 11 4 5 6 MSCAN Power Down Mode The MSCAN is in power down mode Table 11 38 when CPU is in stop mode or CPU is in wait mode and the CSWAI bit is set When entering the power down mode the MSCAN immediately stops all ongoing transmissions and receptions potentially ca...

Page 346: ... individual bit is listed in Section 11 3 2 Register Descriptions which details all the registers and their bit fields 11 4 7 Interrupts This section describes all interrupts originated by the MSCAN It documents the enable bits and generated flags Each interrupt is listed and described separately 11 4 7 1 Description of Interrupt Operation The MSCAN supports four interrupt vectors see Table 11 39 ...

Page 347: ...eceive Structures occurred CAN Status Change The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN As soon as the error counters skip into a critical range Tx Rx warning Tx Rx error bus off the MSCAN flags an error condition The status change which caused the error condition is indicated by the TSTAT and RSTAT flags see Section 11 3 2 5 MSCAN Receiver F...

Page 348: ...nfiguration registers in initialization mode 4 Clear INITRQ to leave initialization mode and continue 11 5 2 Bus Off Recovery The bus off recovery is user configurable The bus off state can either be left automatically or on user request For reasons of backwards compatibility the MSCAN defaults to automatic recovery after reset In this case the MSCAN will become error active again after counting 1...

Page 349: ...n bus clock cycles with 1 m 256 and 1 n 65536 Timers that can be enabled individually Four time out interrupts Four time out trigger output signals available to trigger peripheral modules Start of timer channels can be aligned to each other 12 1 3 Modes of Operation Refer to the SoC guide for a detailed explanation of the chip modes Version Number Revision Date Effective Date Author Description of...

Page 350: ...operation in freeze mode is controlled by the PITFRZ bit located in the PITCFLMT register In freeze mode if the PITFRZ bit is clear the PIT operates like in run mode In freeze mode if the PITFRZ bit is set the PIT module is stalled 12 1 4 Block Diagram Figure 12 1 shows a block diagram of the PIT module Figure 12 1 PIT24B4C Block Diagram 12 2 External Signal Description The PIT module has no exter...

Page 351: ... 0 0 0 0 PCE3 PCE2 PCE1 PCE0 W 0x0003 PITMUX R 0 0 0 0 PMUX3 PMUX2 PMUX1 PMUX0 W 0x0004 PITINTE R 0 0 0 0 PINTE3 PINTE2 PINTE1 PINTE0 W 0x0005 PITTF R 0 0 0 0 PTF3 PTF2 PTF1 PTF0 W 0x0006 PITMTLD0 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W 0x0007 PITMTLD1 R PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0 W 0x0008 PITLD0 High R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 ...

Page 352: ...6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0012 PITCNT2 High R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0013 PITCNT2 Low R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x0014 PITLD3 High R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0015 PITLD3 Low R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x0016 PITCNT3 High R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0017 P...

Page 353: ... 6 PITSWAI PIT Stop in Wait Mode Bit This bit is used for power conservation while in wait mode 0 PIT operates normally in wait mode 1 PIT clock generation stops and freezes the PIT module when in wait mode 5 PITFRZ PIT Counter Freeze while in Freeze Mode Bit When during debugging a breakpoint freeze mode is encountered it is useful in many cases to freeze the PIT counters to avoid e g interrupt g...

Page 354: ...ed PITE set Writing a one into a PFLT bit loads the corresponding 16 bit timer load register into the 16 bit timer down counter Writing a zero has no effect Reading these bits will always return zero Module Base 0x0002 7 6 5 4 3 2 1 0 R 0 0 0 0 PCE3 PCE2 PCE1 PCE0 W Reset 0 0 0 0 0 0 0 0 Figure 12 5 PIT Channel Enable Register PITCE Table 12 4 PITCE Field Descriptions Field Description 3 0 PCE 3 0...

Page 355: ...itched to the other micro time base immediately 0 The corresponding 16 bit timer counts with micro time base 0 1 The corresponding 16 bit timer counts with micro time base 1 Module Base 0x0004 7 6 5 4 3 2 1 0 R 0 0 0 0 PINTE3 PINTE2 PINTE1 PINTE0 W Reset 0 0 0 0 0 0 0 0 Figure 12 7 PIT Interrupt Enable Register PITINTE Table 12 6 PITINTE Field Descriptions Field Description 3 0 PINTE 3 0 PIT Time ...

Page 356: ...cro timer modulus down counter have counted to zero The flag can be cleared by writing a one to the flag bit Writing a zero has no effect If flag clearing by writing a one and flag setting happen in the same bus clock cycle the flag remains set The flag bits are cleared if the PIT module is disabled or if the corresponding timer channel is disabled 0 Time out of the corresponding PIT channel has n...

Page 357: ...r Load Bits 7 0 These bits set the 8 bit modulus down counter load value of the micro timers Writing a new value into the PITMTLD register will not restart the timer When the micro timer has counted down to zero the PMTLD register value will be loaded The PFLMT bits in the PITCFLMT register can be used to immediately update the count register with the new value if an immediate load is desired ...

Page 358: ...D14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 13 PIT Load Register 2 PITLD2 Module Base 0x0014 0x0015 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 14 PIT Load Register 3 PITLD3 Table 12 9...

Page 359: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 16 PIT Count Register 1 PITCNT1 Module Base 0x0012 0x0013 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT 15 PCNT 14 PCNT 13 PCNT 12 PCNT 11 PCNT 10 PCNT 9 PCNT 8 PCNT 7 PCNT 6 PCNT 5 PCNT 4 PCNT 3 PCNT 2 PCNT 1 PCNT 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 17 PIT Count Register 2 PITCNT2 Module Base 0x0016 0x0017 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 360: ...l and force load micro timer PITCFLMT register is set and if the corresponding PCE bit in the PIT channel enable PITCE register is set Two 8 bit modulus down counters are used to generate two micro time bases As soon as a micro time base is selected for an enabled timer channel the corresponding micro timer modulus down counter will load its start value as specified in the PITMTLD0 or PITMTLD1 reg...

Page 361: ...g force load micro timer PFLMT bits in the PIT control and force load micro timer PITCFLMT register The 16 bit timers can individually be restarted by writing a one to the corresponding force load timer PFLT bits in the PIT forceload timer PITFLT register If desired any group of timers and micro timers can be restarted at the same time by using one 16 bit write to the adjacent PITCFLMT and PITFLT ...

Page 362: ... Startup Set the configuration registers before the PITE bit in the PITCFLMT register is set Before PITE is set the configuration registers can be written in arbitrary order 12 5 2 Shutdown When the PITCE register bits the PITINTE register bits or the PITE bit in the PITCFLMT register are cleared the corresponding PIT interrupt flags are cleared In case of a pending PIT interrupt request a spuriou...

Page 363: ...to specific range to be selected LDS RAMEND load stack pointer to top of RAM MOVW CH0_ISR VEC_PIT_CH0 Change value of channel 0 ISR adr Start PIT Initialization CLR PITCFLMT disable PIT MOVB 01 PITCE enable timer channel 0 CLR PITMUX ch0 connected to micro timer 0 MOVB 63 PITMTLD0 micro time base 0 equals 100 clock cycles MOVW 0004 PITLD0 time base 0 eq 5 micro time bases 0 5 100 500 MOVB 01 PITIN...

Page 364: ...Periodic Interrupt Timer S12PIT24B4CV1 S12XS Family Reference Manual Rev 1 13 364 Freescale Semiconductor ...

Page 365: ...puts can be programmed as left aligned outputs or center aligned outputs 13 1 1 Features The PWM block includes these distinctive features Eight independent PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Programmable PWM enable disable for each channel Software selection of PWM duty pulse polarity for each channel Period and duty cycle are double buffer...

Page 366: ...lock Diagram Figure 13 1 shows the block diagram for the 8 bit 8 channel PWM block Figure 13 1 PWM Block Diagram 13 2 External Signal Description The PWM module has a total of 8 external pins Period and Duty Counter Channel 6 Clock Select PWM Clock Period and Duty Counter Channel 5 Period and Duty Counter Channel 4 Period and Duty Counter Channel 3 Period and Duty Counter Channel 2 Period and Duty...

Page 367: ... This pin serves as waveform output of PWM channel 0 13 3 Memory Map and Register Definition This section describes in detail all the registers and register bits in the PWM module The special purpose registers and register bit functions that are not normally available to device end users such as factory test control registers and reserved registers are clearly identified by means of shading the ap...

Page 368: ...3 2 Register Descriptions This section describes in detail all the registers and register bits in the PWM module Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PWME R PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W 0x0001 PWMPOL R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W 0x0002 PWMCLK R PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 W 0x0003 PWMPRCLK R 0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 ...

Page 369: ...2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0010 PWMCNT4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0011 PWMCNT5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0012 PWMCNT6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0013 PWMCNT7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0014 PWMPER0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0015 PWMPER1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0016 PWMPER2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0017 ...

Page 370: ...MPER5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001A PWMPER6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001B PWMPER7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001C PWMDTY0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001D PWMDTY1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001E PWMDTY2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001F PWMDTY3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0010 PWMDTY4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0021 PWMDTY5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0022 PWMDTY6 R Bit 7...

Page 371: ...Pulse Width Channel 6 Enable 0 Pulse width channel 6 is disabled 1 Pulse width channel 6 is enabled The pulse modulated signal becomes available at PWM output bit6 when its clock source begins its next cycle If CON67 1 then bit has no effect and PWM output line 6 is disabled 5 PWME5 Pulse Width Channel 5 Enable 0 Pulse width channel 5 is disabled 1 Pulse width channel 5 is enabled The pulse modula...

Page 372: ...bed below 1 PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled 1 Pulse width channel 1 is enabled The pulse modulated signal becomes available at PWM output bit 1 when its clock source begins its next cycle 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled 1 Pulse width channel 0 is enabled The pulse modulated signal becomes available at PWM output bit 0 ...

Page 373: ... channel 7 6 PCLK6 Pulse Width Channel 6 Clock Select 0 Clock B is the clock source for PWM channel 6 1 Clock SB is the clock source for PWM channel 6 5 PCLK5 Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5 1 Clock SA is the clock source for PWM channel 5 4 PCLK4 Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4 1 Clock SA is the ...

Page 374: ...elect for Clock B Clock B is one of two clock sources which can be used for channels 2 3 6 or 7 These three bits determine the rate of clock B as shown in Table 13 5 2 0 PCKA 2 0 Prescaler Select for Clock A Clock A is one of two clock sources which can be used for channels 0 1 4 or 5 These three bits determine the rate of clock A as shown in Table 13 6 Table 13 5 Clock B Prescaler Selects PCKB2 P...

Page 375: ...he PWM module Read Anytime Write Anytime There are three control bits for concatenation each of which is used to concatenate a pair of PWM channels into one 16 bit channel When channels 6 and 7are concatenated channel 6 registers become the high order bytes of the double byte channel When channels 4 and 5 are concatenated channel 4 registers become the high order bytes of the double byte channel W...

Page 376: ...d channel 3 becomes the low order byte Channel 3 output pin is used as the output for this 16 bit PWM bit 3 of port PWMP Channel 3 clock select control bit determines the clock source channel 3 polarity bit determines the polarity channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode 4 CON01 Concatenate Channels 0 and 1 0 Channels 0 and 1 are se...

Page 377: ...n normal modes Read Always read 00 in normal modes Write Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality 13 3 2 9 PWM Scale A Register PWMSCLA PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA Clock SA is generated by taking clock A dividing it by the value in the PWMSCLA register and dividing that...

Page 378: ...in the PWMSCLB register and dividing that by two Clock SB Clock B 2 PWMSCLB NOTE When PWMSCLB 00 PWMSCLB value is considered a full scale value of 256 Clock B is thus divided by 512 Any value written to this register will cause the scale counter to load the new scale value PWMSCLB Read Anytime Write Anytime causes the scale counter to load the PWMSCLB value 13 3 2 11 Reserved Registers PWMSCNTx Th...

Page 379: ...of the effective period see Section 13 4 2 5 Left Aligned Outputs and Section 13 4 2 6 Center Aligned Outputs for more details When the channel is disabled PWMEx 0 the PWMCNTx register does not count When a channel becomes enabled PWMEx 1 the associated PWM counter starts at the count in the PWMCNTx register For more detailed information on the operation of the counters see Section 13 4 2 4 PWM Ti...

Page 380: ... period register will go directly to the latches as well as the buffer NOTE Reads of this register return the most recent value written Reads do not necessarily return the value of the currently active period due to the double buffering scheme See Section 13 4 2 3 PWM Period and Duty for more information To calculate the output period take the selected clock source period for the channel of intere...

Page 381: ...ecent value written Reads do not necessarily return the value of the currently active duty due to the double buffering scheme See Section 13 4 2 3 PWM Period and Duty for more information NOTE Depending on the polarity bit the duty registers will contain the count of either the high time or the low time If the polarity bit is one the output starts high and then goes low when the duty count is reac...

Page 382: ...d 1 PWM interrupt is enabled 5 PWMRSTRT PWM Restart The PWM can only be restarted if the PWM channel input 7 is de asserted After writing a logic 1 to the PWMRSTRT bit trigger event the PWM channels start running after the corresponding counter passes next counter 0 phase Also if the PWM7ENA bit is reset to 0 the PWM do not start before the counter passes 00 The bit is always read as 0 4 PWMLVL PW...

Page 383: ... whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register If this bit is set whenever the MCU is in freeze mode freeze mode signal active the input clock to the prescaler is disabled This is useful for emulation in order to freeze the PWM The input clock can also be disabled when all eight PWM channels are disabled PWME7 0 0 This is useful for reducing power by disabling ...

Page 384: ...by PFRZ Freeze Mode Signal Bus Clock Clock Select M U X PCLK0 Clock to PWM Ch 0 M U X PCLK2 Clock to PWM Ch 2 M U X PCLK1 Clock to PWM Ch 1 M U X PCLK4 Clock to PWM Ch 4 M U X PCLK5 Clock to PWM Ch 5 M U X PCLK6 Clock to PWM Ch 6 M U X PCLK7 Clock to PWM Ch 7 M U X PCLK3 Clock to PWM Ch 3 Load DIV 2 PWMSCLB Clock SB Clock B 2 B 4 B 6 B 512 M U X PCKA2 PCKA1 PCKA0 PWME7 0 Count 1 Load DIV 2 PWMSCLA...

Page 385: ...der the case in which the user writes FF into the PWMSCLA register Clock A for this case will be E divided by 4 A pulse will occur at a rate of once every 255x4 E cycles Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate Similarly a value of 01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by 8 rate Writ...

Page 386: ... the block diagram for the PWM timer Figure 13 19 PWM Timer Channel Block Diagram 13 4 2 1 PWM Enable Each PWM channel has an enable bit PWMEx to start its waveform output When any of the PWMEx bits are set PWMEx 1 the associated PWM output signal is enabled immediately However the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to...

Page 387: ...er the old waveform or the new waveform not some variation in between If the channel is not enabled then writes to the period and duty registers will go directly to the latches as well as the buffer A change in duty or period can be forced into effect immediately by writing the new value to the duty and or period registers and then writing to the counter This forces the counter to reset and the ne...

Page 388: ...ted immediately with the output set according to the polarity bit NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur The counter is cleared at the end of the effective period see Section 13 4 2 5 Left Aligned Outputs and Section 13 4 2 6 Center Aligned Outputs for more details 13 4 2 5 Left Aligned Outputs The PWM timer provides the choice of two typ...

Page 389: ...particular channel take the selected clock source frequency for the channel A B SA or SB and divide it by the value in the period register for that channel PWMx Frequency Clock A B SA or SB PWMPERx PWMx Duty Cycle high time as a of period Polarity 0 PPOLx 0 Duty Cycle PWMPERx PWMDTYx PWMPERx 100 Polarity 1 PPOLx 1 Duty Cycle PWMDTYx PWMPERx 100 As an example of a left aligned output consider the f...

Page 390: ...rection from an up count to a down count When the PWM counter decrements and matches the duty register again the output flip flop changes state causing the PWM output to also change state When the PWM counter decrements and reaches zero the counter direction changes from a down count back to an up count and a load from the double buffer period and duty registers to the associated registers is perf...

Page 391: ...ode for a particular channel take the selected clock source frequency for the channel A B SA or SB and divide it by twice the value in the period register for that channel PWMx Frequency Clock A B SA or SB 2 PWMPERx PWMx Duty Cycle high time as a of period Polarity 0 PPOLx 0 Duty Cycle PWMPERx PWMDTYx PWMPERx 100 Polarity 1 PPOLx 1 Duty Cycle PWMDTYx PWMPERx 100 ...

Page 392: ...th the CON01 bit NOTE Change these bits only when both corresponding channels are disabled When channels 6 and 7 are concatenated channel 6 registers become the high order bytes of the double byte channel as shown in Figure 13 24 Similarly when channels 4 and 5 are concatenated channel 4 registers become the high order bytes of the double byte channel When channels 2 and 3 are concatenated channel...

Page 393: ...t and their corresponding PWM output is disabled In concatenated mode writes to the 16 bit counter by using a 16 bit access or writes to either the low or high order byte of the counter will reset the 16 bit counter Reads of the 16 bit counter must be made by 16 bit access to maintain data coherency PWMCNT6 PWCNT7 PWM7 Clock Source 7 High Low Period Duty Compare PWMCNT4 PWCNT5 PWM5 Clock Source 5 ...

Page 394: ... 2 Register Descriptions which details the registers and their bit fields All special functions or modes which are initialized during or just following reset are described within this section The 8 bit up down counter is configured as an up counter out of reset All the channels are disabled and all the counters do not count Table 13 11 16 bit Concatenation Mode Summary CONxx PWMEx PPOLx PCLKx CAEx...

Page 395: ... level of the PWM7 channel changes while PWM7ENA 1 or when PWMENA is being asserted while the level at PWM7 is active In stop mode or wait mode with the PSWAI bit set the emergency shutdown feature will drive the PWM outputs to their shutdown output levels but the PWMIF flag will not be set A description of the registers involved and affected due to this interrupt is explained in Section 13 3 2 15...

Page 396: ...Pulse Width Modulator S12PWM8B8CV1 S12XS Family Reference Manual Rev 1 13 396 Freescale Semiconductor ...

Page 397: ...ate IRQ Interrupt Request LIN Local Interconnect Network LSB Least Significant Bit MSB Most Significant Bit NRZ Non Return to Zero RZI Return to Zero Inverted RXD Receive Pin SCI Serial Communication Interface TXD Transmit Pin Table 14 1 Revision History Version Number Revision Date Effective Date Author Description of Changes 05 03 12 25 2008 remove redundancy comments in Figure1 2 05 04 08 05 20...

Page 398: ...larity for transmitter and receiver Programmable transmitter output parity Two receiver wakeup methods Idle line wakeup Address mark wakeup Interrupt driven operation with eight flags Transmitter empty Transmission complete Receiver full Idle receiver input Receiver overrun Noise error Framing error Parity error Receive wakeup on active edge Transmit collision detect supporting LIN Break Detect su...

Page 399: ... of various function blocks Figure 14 1 SCI Block Diagram SCI Data Register RXD Data In Data Out TXD Receive Shift Register Infrared Decoder Receive Wakeup Control Data Format Control Transmit Control Baud Rate Generator Bus Clock 1 16 Transmit Shift Register SCI Data Register Receive Interrupt Generation Transmit Interrupt Generation Infrared Encoder IDLE RDRF OR TC TDRE BRKD BERR RXEDG SCI Inter...

Page 400: ...pin receives SCI standard or infrared data An idle line is detected as a line high This input is ignored when the receiver is disabled and should be terminated to a known voltage 14 3 Memory Map and Register Definition This section provides a detailed description of all the SCI registers 14 3 1 Module Memory Map and Register Definition The memory map for the SCI module is given below in Figure 14 ...

Page 401: ...SBR9 SBR8 W 0x0001 SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR12 R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W 0x0001 SCIACR12 R RXEDGIE 0 0 0 0 0 BERRIE BKDIE W 0x0002 SCIACR22 R 0 0 0 0 0 BERRM1 BERRM0 BKDFE W 0x0003 SCICR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x0004 SCISR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x0005 SCISR2 R AMAP...

Page 402: ...le 14 2 SCIBDH and SCIBDL Field Descriptions Field Description 7 IREN Infrared Enable Bit This bit enables disables the infrared modulation demodulation submodule 0 IR disabled 1 IR enabled 6 5 TNP 1 0 Transmitter Narrow Pulse Bits These bits enable whether the SCI transmits a 1 16 3 16 1 32 or 1 4 narrow pulse See Table 14 3 4 0 7 0 SBR 12 0 SCI Baud Rate Bits The baud rate for the SCI is determi...

Page 403: ...smitter and the receiver must be enabled to use the loop function 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit 6 SCISWAI SCI Stop in Wait Mode Bit SCISWAI disables the SCI in wait mode 0 SCI enabled in wait mode 1 SCI disabled in wait mode 5 RSRC Receiver Source Bit When LOOPS 1 the RSRC bit determines the source for the receiver shift regist...

Page 404: ...begins after stop bit 1 PE Parity Enable Bit PE enables the parity function When enabled the parity function inserts a parity bit in the most significant bit position 0 Parity function disabled 1 Parity function enabled 0 PT Parity Type Bit PT determines whether the SCI generates and checks for even parity or odd parity With even parity an even number of 1s clears the parity bit and an odd number ...

Page 405: ...Bit Error Value BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened The value is only meaningful if BERRIF 1 0 A low input was sampled when a high was expected 1 A high input reassembled when a low was expected 1 BERRIF Bit Error Interrupt Flag BERRIF is asserted when the bit error detect circuitry is enabled and if...

Page 406: ... Description 7 RSEDGIE Receive Input Active Edge Interrupt Enable RXEDGIE enables the receive input active edge interrupt flag RXEDGIF to generate interrupt requests 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt requests enabled 1 BERRIE Bit Error Interrupt Enable BERRIE enables the bit error interrupt flag BERRIF to generate interrupt requests 0 BERRIF interrupt requests disabled 1 BE...

Page 407: ...Descriptions Field Description 2 1 BERRM 1 0 Bit Error Mode Those two bits determines the functionality of the bit error detect feature See Table 14 9 0 BKDFE Break Detect Feature Enable BKDFE enables the break detect circuitry 0 Break detect circuit disabled 1 Break detect circuit enabled Table 14 9 Bit Error Mode Coding BERRM1 BERRM0 Function 0 0 Bit error detect circuit is disabled 0 1 Receive ...

Page 408: ...sts disabled 1 RDRF and OR interrupt requests enabled 4 ILIE Idle Line Interrupt Enable Bit ILIE enables the idle line flag IDLE to generate interrupt requests 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled 3 TE Transmitter Enable Bit TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI The TE bit can be used to queue an idle preamble 0 Tra...

Page 409: ... Transmit Complete Flag TC is set low when there is a transmission in progress or when a preamble or break character is loaded TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes idle logic 1 Clear TC by reading SCI status register 1 SCISR1 with TC set and then writing to SCI data register low SCIDRL TC is cleared...

Page 410: ...t exactly the same time as event 2 or any time after When this happens a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received 2 NF Noise Flag NF is set when the SCI detects noise on the receiver input NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun Clear NF by reading SCI status register 1...

Page 411: ...it time remaining idle high for a one for inverted polarity 0 Normal polarity 1 Inverted polarity 3 RXPOL Receive Polarity This bit control the polarity of the received data In NRZ format a one is represented by a mark and a zero is represented by a space for normal polarity and the opposite for inverted polarity In IrDA format a zero is represented by short high pulse in the middle of a bit time ...

Page 412: ... first to SCI data register high SCIDRH then SCIDRL Module Base 0x0006 7 6 5 4 3 2 1 0 R R8 T8 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 14 12 SCI Data Registers SCIDRH Module Base 0x0007 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Figure 14 13 SCI Data Registers SCIDRL Table 14 13 SCIDRH and SCIDRL Field Descriptions Field D...

Page 413: ...aud rate generator The CPU monitors the status of the SCI writes the data to be transmitted and processes received data Figure 14 14 Detailed SCI Block Diagram SCI Data Receive Shift Register SCI Data Register Transmit Shift Register Register Baud Rate Generator SBR12 SBR0 Bus Transmit Control 16 Receive and Wakeup Data Format Control Control T8 PF FE NF RDRF IDLE TIE OR TCIE TDRE TC R8 RAF LOOPS ...

Page 414: ...during transmission The infrared block receives two clock sources from the SCI R16XCLK and R32XCLK which are configured to generate the narrow pulse width during transmission The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively Both R16XCLK and R32XCLK clocks are used for transmitting data The receive decoder uses only the R16XCLK clock 14 4 1 1 I...

Page 415: ...d for 9 bit data characters the ninth data bit is the T8 bit in SCI data register high SCIDRH It remains unchanged after transmission and can be used repeatedly without rewriting it A frame with nine data bits has a total of 11 bits Table 14 14 Example of 8 Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 1 7 11 1 The address bit identifies the frame as an...

Page 416: ...rate of 16 samples per bit time Baud rate generation is subject to one source of error Integer division of the bus clock may not give the exact target frequency Table 14 16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz When IREN 0 then SCI baud rate SCI bus clock 16 SCIBR 12 0 1 The address bit identifies the frame as an address character See Section 14 4 ...

Page 417: ...rs SCIDRH SCIDRL which in turn are transferred to the transmitter shift register The transmit shift register then shifts a frame out through the TXD pin after it has prefaced them with a start bit and appended them with a stop bit The SCI data registers SCIDRH and SCIDRL are the write only buffers between the internal data bus and the transmit shift register PE PT H 8 7 6 5 4 3 2 1 0 L 11 Bit Tran...

Page 418: ...RH L where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9 bit data format A new transmission will not result until the TDRE flag has been cleared 3 Repeat step 2 for each subsequent transmission NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH L which happens generally speaking a little over half way through the stop ...

Page 419: ...depends on the M bit in SCI control register 1 SCICR1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees the recognition of the st...

Page 420: ... 1s and has no start stop or parity bit Idle character length depends on the M bit in SCI control register 1 SCICR1 The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1 If the TE bit is cleared during a transmission the TXD pin becomes idle after completion of the transmission in progress Clearing and then setting the TE b...

Page 421: ...nd the byte in transmit buffer is discarded the transmit data register empty and the transmission complete flag will be set The bit error interrupt flag BERRIF will be set No further transmissions will take place until the BERRIF is cleared Figure 14 19 Timing Diagram Bit Error Detection If the bit error detect feature is disabled the bit error interrupt flag is cleared NOTE The RXPOL and TXPOL bi...

Page 422: ...XD pin The SCI data register is the read only buffer between the internal data bus and the receive shift register After a complete frame shifts into the receive shift register the data portion of the frame transfers to the SCI data register The receive data register full flag RDRF in SCI status register 1 SCISR1 becomes set All 1s M WAKE ILT PE PT RE H 8 7 6 5 4 3 2 1 0 L 11 Bit Receive Shift Regi...

Page 423: ... the start bit data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 Figure 14 21 Receiver Data Sampling To verify the start bit and to detect noise data recovery logic takes samples at RT3 RT5 and RT7 Figure 14 17 summarizes the results of the start bit verification samples I...

Page 424: ...es are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit logic 0 To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 14 19 summarizes the results of the stop bit samples Table 14 18 Data Bit Recovery RT8 RT9 and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 ...

Page 425: ...RT3 is high The RT3 sample sets the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful Figure 14 23 Start Bit Search Example 2 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Start Bit R...

Page 426: ...14 25 shows the effect of noise early in the start bit time Although this noise does not affect proper synchronization with the start bit time it does set the noise flag Figure 14 25 Start Bit Search Example 4 Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT13 RT12 RT11 RT16 RT15 RT14 RT4 RT3 RT2 RT1 RT5 RT6 RT7 RT8 RT9 Samples RT Clock RT Clock Count Actual Start Bit RXD 1 0...

Page 427: ...9 and RT10 data samples are ignored Figure 14 27 Start Bit Search Example 6 14 4 6 4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame it sets the framing error flag FE in SCI status register 1 SCISR1 A break character also sets the FE flag because a break character has no stop bit The FE flag is set at the same time that the RDRF...

Page 428: ...arrives in time for the stop bit data samples at RT8 RT9 and RT10 Figure 14 28 Slow Data Let s take RTr as receiver RT clock and RTt as transmitter RT clock For an 8 bit data character it takes the receiver 9 bit times x 16 RTr cycles 7 RTr cycles 151 RTr cycles to start data sampling of the stop bit With the misaligned character shown in Figure 14 28 the receiver counts 151 RTr cycles at the poin...

Page 429: ... 29 the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles 176 RTt cycles The maximum percent difference between the receiver count and the transmitter count of a fast 9 bit character with no errors is 176 170 176 x 100 3 40 14 4 6 6 Receiver Wakeup To enable the SCI to ignore transmissions intended only for other receivers in mult...

Page 430: ...er 1 SCICR1 14 4 6 6 2 Address Mark Wakeup WAKE 1 In this wakeup method a logic 1 in the most significant bit MSB position of a frame clears the RWU bit and wakes up the SCI The logic 1 in the MSB position marks a frame as an address frame that contains addressing information All receivers evaluate the addressing information and the receivers for which the message is addressed process the frames t...

Page 431: ...op operation the transmitter output goes to the receiver input The RXD pin is disconnected from the SCI Figure 14 31 Loop Operation LOOPS 1 RSRC 0 Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 SCICR1 Setting the LOOPS bit disables the path from the RXD pin to the receiver Clearing the RSRC bit connects the transmitter output to the receiver inpu...

Page 432: ...set aborts any transmission or reception in progress and resets the SCI The receive input active edge detect circuit is still active in stop mode An active edge on the receive input can be used to bring the CPU out of stop mode 14 5 3 Interrupt Operation This section describes the interrupt originated by the SCI block The MCU must service the interrupt requests Table 14 20 lists the eight interrup...

Page 433: ... indicates that there is no transmission in progress TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes idle logic 1 Clear TC by reading SCI status register 1 SCISR1 with TC set and then writing to SCI data register low SCIDRL TC is cleared automatically when data preamble or break is queued and ready to be sent ...

Page 434: ...data in a single wire application like LIN was detected Clear BERRIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if the bit error detect feature is disabled 14 5 3 1 8 BKDIF Description The BKDIF interrupt is set when a break signal was received Clear BKDIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if bre...

Page 435: ...ansfer width Bidirectional mode Slave select output Mode fault error flag with CPU interrupt capability Double buffered data register Serial clock with programmable polarity and phase Control of SPI operation during wait mode 15 1 3 Modes of Operation The SPI functions in three modes run wait and stop Table 15 1 Revision History Revision Number Revision Date Sections Affected Description of Change...

Page 436: ...mode If the SPI is configured as a slave reception and transmission of data continues so that the slave stays synchronized to the master Stop mode The SPI is inactive in stop mode for reduced power consumption If the SPI is configured as a master any transmission in progress stops but is resumed after CPU goes into run mode If the SPI is configured as a slave reception and transmission of data con...

Page 437: ...5 2 2 MISO Master In Slave Out Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master SPI Control Register 1 SPI Control Register 2 SPI Baud Rate Register SPI Status Register SPI Data Register Shifter Port Control Logic MOSI SCK Interrupt Control SPI MSB LSB LSBFE 1 LSBFE 0 LSBFE 0 LSBFE 1 Data In LSBFE 1 LSBFE ...

Page 438: ...e SPI 15 3 1 Module Memory Map The memory map for the SPI is given in Figure 15 2 The address listed for each register is the sum of a base address and an address offset The base address is defined at the SoC level and the address offset is defined at the module level Reads from the reserved bits return zeros and writes to the reserved bits have no effect Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x00...

Page 439: ...reset 0 SPI disabled lower power consumption 1 SPI enabled port pins are dedicated to SPI functions 5 SPTIE SPI Transmit Interrupt Enable This bit enables SPI interrupt requests if SPTEF flag is set 0 SPTEF interrupt disabled 1 SPTEF interrupt enabled 4 MSTR SPI Master Slave Mode Select Bit This bit selects whether the SPI operates in master or slave mode Switching the SPI from master to slave or ...

Page 440: ...he data register Reads and writes of the data register always have the MSB in the highest bit position In master mode a change of this bit will abort a transmission in progress and force the SPI system into idle state 0 Data is transferred most significant bit first 1 Data is transferred least significant bit first Table 15 3 SS Input Output Selection MODFEN SSOE Master Mode Slave Mode 0 0 SS not ...

Page 441: ...Table 15 3 In master mode a change of this bit will abort a transmission in progress and force the SPI system into idle state 0 SS port pin is not used by the SPI 1 SS port pin with MODF feature 3 BIDIROE Output Enable in the Bidirectional Mode of Operation This bit controls the MOSI and MISO output buffer of the SPI when in bidirectional mode of operation SPC0 is set In master mode this bit contr...

Page 442: ...ns Field Description 6 4 SPPR 2 0 SPI Baud Rate Preselection Bits These bits specify the SPI baud rates as shown in Table 15 7 In master mode a change of these bits will abort a transmission in progress and force the SPI system into idle state 2 0 SPR 2 0 SPI Baud Rate Selection Bits These bits specify the SPI baud rates as shown in Table 15 7 In master mode a change of these bits will abort a tra...

Page 443: ...0 1 1 1 1 0 512 48 83 kbit s 0 1 1 1 1 1 1024 24 41 kbit s 1 0 0 0 0 0 10 2 5 Mbit s 1 0 0 0 0 1 20 1 25 Mbit s 1 0 0 0 1 0 40 625 kbit s 1 0 0 0 1 1 80 312 5 kbit s 1 0 0 1 0 0 160 156 25 kbit s 1 0 0 1 0 1 320 78 13 kbit s 1 0 0 1 1 0 640 39 06 kbit s 1 0 0 1 1 1 1280 19 53 kbit s 1 0 1 0 0 0 12 2 08333 Mbit s 1 0 1 0 0 1 24 1 04167 Mbit s 1 0 1 0 1 0 48 520 83 kbit s 1 0 1 0 1 1 96 260 42 kbit ...

Page 444: ...information about clearing SPIF Flag please refer to Table 15 9 0 Transfer not yet complete 1 New data copied to SPIDR 5 SPTEF SPI Transmit Empty Interrupt Flag If set this bit indicates that the transmit data register is empty For information about clearing this bit and placing data into the transmit data register please refer to Table 15 10 0 SPI data register not empty 1 SPI data register empty...

Page 445: ...thout any effect on SPIF SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF 1 Byte Read SPIDRL or Word Read SPIDRH SPIDRL XFRW Bit SPTEF Interrupt Flag Clearing Sequence 0 Read SPISR with SPTEF 1 then Write to SPIDRL 1 1 Any write to SPIDRH or SPIDRL with SPTEF 0 is effectively ignored 1 Read SPISR with SPTEF 1 then Byte Write to SPIDRL 12 2 Data in SPIDRH is undefined i...

Page 446: ...is set and not serviced and a second data value has been received the second received data is kept as valid data in the receive shift register until the start of another transmission The data in the SPIDR does not change If SPIF is set and valid data is in the receive shift register and SPIF is serviced before the start of a third transmission the data in the receive shift register is transferred ...

Page 447: ...I system is enabled by setting the SPI enable SPE bit in SPI control register 1 While SPE is set the four associated SPI port pins are dedicated to the SPI function as Slave select SS Serial clock SCK Master out slave in MOSI Master in slave out MISO Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received Data B...

Page 448: ...ction 15 4 3 Transmission Formats The SPI can be configured to operate as a master or as a slave When the MSTR bit in SPI control register1 is set master mode is selected when the MSTR bit is clear slave mode is selected NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided 15 4 1 Master Mode The SP...

Page 449: ...into idle state The remote slave cannot detect this therefore the master must ensure that the remote slave is returned to idle state 15 4 2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear Serial clock In slave mode SCK is the SPI clock input from the master MISO MOSI pin In slave mode the function of the serial data output pin MISO and serial data inp...

Page 450: ... data is driven out of the serial data output pin After the nth1 shift the transfer is considered complete and the received data is transferred into the SPI data register To indicate transfer is complete the SPIF flag in the SPI status register is set NOTE A change of the bits CPOL CPHA SSOE LSBFE MODFEN SPC0 or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and must b...

Page 451: ...gister depending on LSBFE bit After this second edge the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave This process continues for a total of 16 edges on the SCK line with data being latched on odd numbered edges and shifted on even numbered edges Data reception is double buffered Data is shifted serially into the...

Page 452: ...2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS I MOSI pin MISO pin Master only MOSI MISO tT If next transfer begins here for tT tl tL Minimum 1 2 SCK tI tL tL Minimum leading time before the first SCK edge tT Minimum trailing time after the last SCK edge tI Minimum idling time between transfers minimum SS high time tL tT and tI are guaranteed for the master mode and ...

Page 453: ...e of SCK occurs immediately after the half SCK clock cycle synchronization delay This first edge commands the slave to transfer its first data bit to the serial data input pin of the master A half SCK cycle later the second edge appears on the SCK pin This is the latching edge for both the master and slave 1 n depends on the selected transfer width please refer to Section 15 3 2 2 SPI Control Regi...

Page 454: ...sfer is complete Figure 15 14 shows two clocking variations for CPHA 1 The diagram may be interpreted as a master or slave timing diagram because the SCK MISO and MOSI pins are connected directly between the master and the slave The MISO signal is the output from the slave and the MOSI signal is the output from the master The SS line is the slave select input to the slave The SS pin of the master ...

Page 455: ...divisor to the SPI module clock which results in the SPI baud rate The SPI clock rate is determined by the product of the value in the baud rate preselection bits SPPR2 SPPR0 and the value in the baud rate selection bits SPR2 SPR0 The module clock divisor equation is shown in Equation 15 3 BaudRateDivisor SPPR 1 2 SPR 1 Eqn 15 3 tL Begin End SCK CPOL 0 SAMPLE I CHANGE O SEL SS O Transfer SCK CPOL ...

Page 456: ...ical Specification in the Electricals chapter of this data sheet 15 4 5 Special Features 15 4 5 1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices When SS output is selected the SS output pin is connected to the SS input pin of the external device The SS output is available...

Page 457: ...ase MISO becomes occupied by the SPI and MOSI is not used This must be considered if the MISO pin is used for another purpose 15 4 6 Error Conditions The SPI has one error condition Mode fault error 15 4 6 1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simult...

Page 458: ...wer Mode Options 15 4 7 1 SPI in Run Mode In run mode with the SPI system enable SPE bit in the SPI control register clear the SPI system is in a low power disabled state SPI registers remain accessible but clocks to the core of this module are disabled 15 4 7 2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2 If SPISWAI is clear the S...

Page 459: ...will stay synchronized with the master The stop mode is not dependent on the SPISWAI bit 15 4 7 4 Reset The reset values of registers and signals are described in Section 15 3 Memory Map and Register Definition which details the registers and their bit fields If a data transmission occurs in slave mode after reset without a write to SPIDR it will transmit garbage or the data last received from the...

Page 460: ...er SPIF is set it does not clear until it is serviced SPIF has an automatic clearing process which is described in Section 15 3 2 4 SPI Status Register SPISR 15 4 7 5 3 SPTEF SPTEF occurs when the SPI data register is ready to accept new data After SPTEF is set it does not clear until it is serviced SPTEF has an automatic clearing process which is described in Section 15 3 2 4 SPI Status Register ...

Page 461: ... or the input capture output compare registers should take place in one clock cycle Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word 16 1 1 Features The TIM16B8CV2 includes these distinctive features Table 16 1 Revision History Revision Number Revision Date Sections Affected Description of Changes V02 05 9 Jul 2009 1...

Page 462: ...caling 16 bit counter 16 bit pulse accumulator 16 1 2 Modes of Operation Stop Timer is off because clocks are stopped Freeze Timer counter keep on running unless TSFRZ in TSCR1 0x0006 is set to 1 Wait Counters keep on running unless TSWAI in TSCR1 0x0006 is set to 1 Normal Timer counter keep on running unless TEN in TSCR1 0x0006 is cleared to 0 ...

Page 463: ...IOC5 IOC3 IOC4 IOC6 IOC7 PA input interrupt PA overflow interrupt Timer overflow interrupt Timer channel 0 interrupt Timer channel 7 interrupt Registers Bus clock Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Channel 0 Channel 1 Channel 2 Chan...

Page 464: ... Accumulator Block Diagram Figure 16 3 Interrupt Flag Setting Edge detector Intermodule Bus PT7 M clock Divide by 64 Clock select CLK0 CLK1 4 1 MUX TIMCLK PACLK PACLK 256 PACLK 65536 Prescaled clock PCLK Timer clock Interrupt MUX PAMOD PACNT PTn Edge detector 16 bit Main Timer TCn Input Capture Reg Set CnF Interrupt ...

Page 465: ...utput Compare Channel 6 Pin This pin serves as input capture or output compare for channel 6 16 2 3 IOC5 Input Capture and Output Compare Channel 5 Pin This pin serves as input capture or output compare for channel 5 16 2 4 IOC4 Input Capture and Output Compare Channel 4 Pin This pin serves as input capture or output compare for channel 4 Pin 16 2 5 IOC3 Input Capture and Output Compare Channel 3 ...

Page 466: ...s for each register is the sum of the base address for the TIM16B8CV2 module and the address offset for each register 16 3 2 Register Descriptions This section consists of register descriptions in address order Each description includes a standard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order Register Name Bit...

Page 467: ...1I C0I W 0x000D TSCR2 R TOI 0 0 0 TCRE PR2 PR1 PR0 W 0x000E TFLG1 R C7F C6F C5F C4F C3F C2F C1F C0F W 0x000F TFLG2 R TOF 0 0 0 0 0 0 0 W 0x0010 0x001F TCxH TCxL R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0020 PACTL R 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI W 0x0021 PAFLG R 0 0 0 0 0 0 PAOVF PAIF W 0x0022 PACNTH R PACNT15 PACNT14 P...

Page 468: ...S6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 W Reset 0 0 0 0 0 0 0 0 Figure 16 6 Timer Input Capture Output Compare Select TIOS Table 16 2 TIOS Field Descriptions Field Description 7 0 IOS 7 0 Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture 1 The corresponding channel acts as an output compare Module Base 0x0001 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FOC...

Page 469: ...output compare then forced output compare action will take precedence and interrupt flag won t get set Module Base 0x0002 7 6 5 4 3 2 1 0 R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 W Reset 0 0 0 0 0 0 0 0 Figure 16 8 Output Compare 7 Mask Register OC7M Table 16 4 OC7M Field Descriptions Field Description 7 0 OC7M 7 0 Output Compare 7 Mask A channel 7 event which can be a counter overflow wh...

Page 470: ...0 0 0 0 0 0 0 0 Figure 16 9 Output Compare 7 Data Register OC7D Table 16 5 OC7D Field Descriptions Field Description 7 0 OC7D 7 0 Output Compare 7 Data A channel 7 event which can be a counter overflow when TTOV 7 is set or a successful output compare on channel 7 can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask...

Page 471: ...tions Field Description 7 TEN Timer Enable 0 Disables the main timer including the counter Can be used for reducing power consumption 1 Allows the timer to function normally If for any reason the timer is not active there is no 64 clock for the pulse accumulator because the 64 is generated by the timer prescaler 6 TSWAI Timer Module Stops While in Wait 0 Allows the timer module to continue running...

Page 472: ...aring due to unintended accesses 3 PRNT Precision Timer 0 Enables legacy timer PR0 PR1 and PR2 bits of the TSCR2 register are used for timer counter prescaler selection 1 Enables precision timer All bits of the PTPSR register are used for Precision Timer Prescaler Selection and all bits This bit is writable only once out of reset Module Base 0x0007 7 6 5 4 3 2 1 0 R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 T...

Page 473: ...are When either OMx or OLx is 1 the pin associated with OCx becomes an output tied to OCx Note To enable output action by OMx bits on timer port the corresponding bit in OC7M should be cleared For an output line to be driven by an OCx the OCPDx must be cleared 7 0 OLx Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx...

Page 474: ...x is timer Input Capture Output Compare register IOCx is channel x OMx OLx is the register TCTL1 TCTL2 OC7Dx is the register OC7D bit x IOCx OC7Dx OMx OLx means that both OC7 event and OCx event will change channel x value 16 3 2 9 Timer Control Register 3 Timer Control Register 4 TCTL3 and TCTL4 OC7M7 0 OC7M7 1 OC7Mx 1 OC7Mx 0 OC7Mx 1 OC7Mx 0 TC7 TCx TC7 TCx TC7 TCx TC7 TCx TC7 TCx TC7 TCx TC7 TC...

Page 475: ...GnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge rising or falling Module Base 0x000C 7 6 5 4 3 2 1 0 R C7I C6I C5I C4I C3I C2I C1I C0I W Reset 0 0 0 0 0 0 0 0 Figure 16 18 Timer Interrupt Enable Register TIE Table 16 13 TIE Field Descriptions Field Description 7 0 C7I C0I Input Capture Output Compare x Interrup...

Page 476: ...ration is similar to an up counting modulus counter 0 Counter reset inhibited and counter free runs 1 Counter reset by a successful output compare 7 Note If TC7 0x0000 and TCRE 1 TCNT will stay at 0x0000 continuously If TC7 0xFFFF and TCRE 1 TOF will never be set when TCNT is reset from 0xFFFF to 0x0000 Note TCRE 1 and TC7 0 the TCNT cycle period will be TC7 x prescaler counter width 1 Bus Clock f...

Page 477: ...m set bits cause corresponding bits to be cleared Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set Module Base 0x000E 7 6 5 4 3 2 1 0 R C7F C6F C5F C4F C3F C2F C1F C0F W Reset 0 0 0 0 0 0 0 0 Figure 16 20 Main Timer Interrupt Flag 1 TFLG1 Table 16 16 TRLG1 Field Descriptions Field Description 7 0 C 7 0 F Input Capture Output Compare Channel x Flag These flags a...

Page 478: ...e low byte otherwise it will give a different result Table 16 17 TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag Set when 16 bit free running timer overflows from 0xFFFF to 0x0000 Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one See also TCRE control bit explanation Module Base 0x0010 TC0H 0x0012 ...

Page 479: ...ly when the Pulse Accumulator is enabled PAEN 1 See Table 16 19 0 Event counter mode 1 Gated time accumulation mode 4 PEDGE Pulse Accumulator Edge Control This bit is active only when the Pulse Accumulator is enabled PAEN 1 For PAMOD bit 0 event counter mode See Table 16 19 0 Falling edges on IOC7 pin cause the count to be incremented 1 Rising edges on IOC7 pin cause the count to be incremented Fo...

Page 480: ...t in the TSCR register is set any access to the PACNT register will clear all the flags in the PAFLG register Timer module or Pulse Accumulator must stay enabled TEN 1 or PAEN 1 while clearing these bits Table 16 19 Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div by 64 clock enabled with pin high level 1 1 Div by 64 clock enabled with pin low level Table 16 20 Timer Cloc...

Page 481: ...ccumulator overflows from 0xFFFF to 0x0000 Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one 0 PAIF Pulse Accumulator Input edge Flag Set when the selected edge is detected at the IOC7 input pin In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate sign...

Page 482: ...igure 16 28 Ouput Compare Pin Disconnect Register OCPD Table 16 22 OCPD Field Description Field Description OCPD 7 0 Output Compare Pin Disconnect Bits 0 Enables the timer channel port Ouptut Compare action will occur on the channel pin These bits do not affect the input capture or pulse accumulator functions 1 Disables the timer channel port Output Compare action will not occur on the channel pin...

Page 483: ...criptions Field Description 7 0 PTPS 7 0 Precision Timer Prescaler Select Bits These eight bits specify the division rate of the main Timer prescaler These are effective only when the PRNT bit of TSCR1 is set to 1 Table 16 24 shows some selection examples in this case The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal ze...

Page 484: ...EN PAE 16 BIT COMPARATOR TCNT hi TCNT lo CHANNEL 1 TC1 16 BIT COMPARATOR 16 BIT COUNTER INTERRUPT LOGIC TOF TOI C0F C1F EDGE DETECT IOC1 PIN LOGIC EDGE DETECT CxF CHANNEL7 TC7 16 BIT COMPARATOR C7F IOC7 PIN LOGIC EDGE DETECT OM OL0 TOV0 OM OL1 TOV1 OM OL7 TOV7 EDG1A EDG1B EDG7A EDG7B EDG0B TCRE PAIF CLEAR COUNTER PAIF PAI INTERRUPT LOGIC CxI INTERRUPT REQUEST PAOVF CH 7 COMPARE CH 7 CAPTURE CH 1 C...

Page 485: ...ity duration and frequency When the timer counter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin if the corresponding OCPDx bit is set to zero An output compare on channel x sets the CxF flag The CxI bit enables the CxF flag to generate interrupt requests Timer module or Pulse Accumulator must stay enabled TEN bit of TSCR1 ...

Page 486: ...ator input pin PAI Gated time accumulation mode Counting pulses from a divide by 64 clock The PAMOD bit selects the mode of operation The minimum pulse width for the PAI input is greater than two bus clocks 16 4 5 Event Counter Mode Clearing the PAMOD bit configures the PACNT for event counter operation An active edge on the IOC7 pin increments the pulse accumulator counter The PEDGE bit selects f...

Page 487: ...e last reset NOTE The timer prescaler generates the divided by 64 clock If the timer is not active there is no divided by 64 clock 16 5 Resets The reset state of each individual bit is listed within Section 16 3 Memory Map and Register Definition which details the registers and their bit fields 16 6 Interrupts This section describes interrupts originated by the TIM16B8CV2 block Table 16 25 lists t...

Page 488: ...is active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller 16 6 3 Pulse Accumulator Overflow Interrupt PAOVF This active high output will be asserted by the module to request a timer pulse accumulator overflow interrupt to be serviced by the system controller 16 6 4 Timer Overflow Interrupt TOF This active high ...

Page 489: ...Modes of Operation There are three modes VREG_3V3 can operate in 1 Full performance mode FPM MCU is not in stop mode The regulator is active providing the nominal supply voltages with full current sourcing capability Features LVD low voltage detect LVR low voltage reset and POR power on reset and HTD High Temperature Detect are available The API is available 2 Reduced power mode RPM MCU is in stop...

Page 490: ...igh impedance state only the POR feature is available LVD LVR and HTD are disabled The API internal RC oscillator clock is not available This mode must be used to disable the chip internal regulator VREG_3V3 i e to bypass the VREG_3V3 to use external supplies 17 1 3 Block Diagram Figure 17 1 shows the function principle of VREG_3V3 by means of a block diagram The regulator core REG consists of thr...

Page 491: ... Diagram LVR LVD POR VDDR VDD LVI POR LVR CTRL VSS VDDPLL VSSPLL VREGEN REG PIN VDDA REG Regulator Core CTRL Regulator Control LVD Low Voltage Detect LVR Low Voltage Reset POR Power on Reset HTD High Temperature Detect C HTI HTD API API API Auto Periodical Interrupt VBG API Rate Select Bus Clock REG2 REG1 REG3 VDDF VSSA VDDX ...

Page 492: ...erence Supply Pins Signals VDDA VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator Internal precision reference circuits are supplied from these signals A chip external decoupling capacitor 100 nF 220 nF X7R ceramic between VDDA and VSSA can further improve the quality of this supply 17 2 3 VDD VSS Regulator Output1 Core Logic Pins Signals VDD VSS a...

Page 493: ...are monitored by VREG_3V3 with the LVR feature 17 2 7 VREGEN Optional Regulator Enable Pin This optional signal is used to shutdown VREG_3V3 In that case VDD VSS and VDDPLL VSSPLL must be provided externally Shutdown mode is entered with VREGEN being low If VREGEN is high the VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode For the connectivity of VREGEN see device specificatio...

Page 494: ...t 7 6 5 4 3 2 1 Bit 0 0x02F0 VREGHTCL R 0 0 VSEL VAE HTEN HTDS HTIE HTIF W 0x02F1 VREGCTRL R 0 0 0 0 0 LVDS LVIE LVIF W 0x02F2 VREGAPIC L R APICLK 0 0 APIFES APIEA APIFE APIE APIF W 0x02F3 VREGAPIT R R APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 0 0 W 0x02F4 VREGAPIR H R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x02F5 VREGAPIR L R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x02...

Page 495: ... set 4 VAE Voltage Access Enable Bit If set the voltage selected by bit VSEL can be accessed internally i e multiplexed to an internal Analog to Digital Converter channel See device level specification for connectivity 0 Voltage selected by VSEL can not be accessed internally i e External analog input is connected to Analog to Digital Converter channel 1 Voltage selected by VSEL can be accessed in...

Page 496: ...tus Bit This read only status bit reflects the input voltage Writes have no effect 0 Input voltage VDDA is above level VLVID or RPM or shutdown mode 1 Input voltage VDDA is below level VLVIA and FPM 1 LVIE Low Voltage Interrupt Enable Bit 0 Interrupt request is disabled 1 Interrupt will be requested whenever LVIF is set 0 LVIF Low Voltage Interrupt Flag LVIF is set to 1 when LVDS status bit change...

Page 497: ...the size of half of the min period Table 17 10 See device level specification for connectivity 0 At the external periodic high pulses are visible if APIEA and APIFE is set 1 At the external pin a clock is visible if APIEA and APIFE is set 3 APIEA Autonomous Periodical Interrupt External Access Enable Bit If set the waveform selected by bit APIES can be accessed externally See device level specific...

Page 498: ...evice Overview for details Unimplemented or Reserved Figure 17 4 Autonomous Periodical Interrupt Trimming Register VREGAPITR Table 17 7 VREGAPITR Field Descriptions Field Description 7 2 APITR 5 0 Autonomous Periodical Interrupt Period Trimming Bits See Table 17 8 for trimming effects Table 17 8 Trimming Effect of APIT Bit Trimming Effect APITR 5 Increases period APITR 4 Decreases period less than...

Page 499: ...0 0 0 0 0 0 0 Unimplemented or Reserved Figure 17 5 Autonomous Periodical Interrupt Rate High Register VREGAPIRH 0x02F5 7 6 5 4 3 2 1 0 R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W Reset 0 0 0 0 0 0 0 0 Figure 17 6 Autonomous Periodical Interrupt Rate Low Register VREGAPIRL Table 17 9 VREGAPIRH VREGAPIRL Field Descriptions Field Description 15 0 APIR 15 0 Autonomous Periodical Interrupt Rat...

Page 500: ...15 0 Selected Period 0 0000 0 2 ms1 1 When trimmed within specified accuracy See electrical specifications for details 0 0001 0 4 ms1 0 0002 0 6 ms1 0 0003 0 8 ms1 0 0004 1 0 ms1 0 0005 1 2 ms1 0 0 FFFD 13106 8 ms1 0 FFFE 13107 0 ms1 0 FFFF 13107 2 ms1 1 0000 2 bus clock period 1 0001 4 bus clock period 1 0002 6 bus clock period 1 0003 8 bus clock period 1 0004 10 bus clock period 1 0005 12 bus cl...

Page 501: ...TTR2 HTTR1 HTTR0 W Reset 0 0 0 0 01 01 01 01 1 Reset value is either 0 or preset by factory See Section 1 Device Overview for details Unimplemented or Reserved Figure 17 8 VREGHTTR Table 17 11 VREGHTTR field descriptions Field Description 7 HTOEN High Temperature Offset Enable Bit If set the temperature sense offset is enabled 0 The temperature sense offset is disabled 1 The temperature sense offs...

Page 502: ...voltage by an operational amplifier The amplified input voltage difference drives the gate of an output transistor 17 4 2 2 Reduced Power Mode In Reduced Power Mode the gate of the output transistor is connected directly to a reference voltage to reduce power consumption Mode switching from reduced power to full performance requires a transition time of tvup if the voltage regulator is enabled 17 ...

Page 503: ...f the clock source of the MCU To enable the timer the bit APIFE needs to be set The API timer is either clocked by a trimmable internal RC oscillator or the bus clock Timer operation will freeze when MCU clock source is selected and bus clock is turned off See CRG specification for details The clock source can be selected with bit APICLK APICLK can only be written when APIFE is not set The APIR 15...

Page 504: ...10 1 Power On Reset POR During chip power up the digital core may not work if its supply voltage VDD is below the POR deassertion level VPORD Therefore signal POR which forces the other blocks of the device into reset is kept high until VDD exceeds VPORD The MCU will run the start up sequence after POR deassertion The power on reset is active in all operation modes of VREG_3V3 17 4 10 2 Low Voltag...

Page 505: ... Power Mode the LVIF is not cleared by the VREG_3V3 17 4 11 2 HTI High Temperature Interrupt In FPM VREG monitors the die temperature TDIE Whenever TDIE exceeds level THTIA the status bit HTDS is set to 1 Vice versa HTDS is reset to 0 when TDIE get below level THTID An interrupt indicated by flag HTIF 1 is triggered by any change of the status bit HTDS if interrupt enable bit HTIE 1 NOTE On enteri...

Page 506: ...Voltage Regulator S12VREGL3V3V1 S12XS Family Reference Manual Rev 1 13 506 Freescale Semiconductor ...

Page 507: ... Revision History Revision Number Revision Date Sections Affected Description of Changes V01 04 03 Jan 2008 Cosmetic changes V01 05 19 Dec 2008 18 1 18 507 18 4 2 4 18 542 18 4 2 6 18 544 18 4 2 11 18 54 7 18 4 2 11 18 54 7 18 4 2 11 18 54 7 Clarify single bit fault correction for P Flash phrase Add statement concerning code runaway when executing Read Once Program Once and Verify Backdoor Access ...

Page 508: ... to execute built in algorithms including program and erase on the Flash memory D Flash Memory The D Flash memory constitutes the nonvolatile memory store for data D Flash Sector The D Flash sector is the smallest portion of the D Flash memory that can be erased The D Flash sector consists of four 64 byte rows for a total of 256 bytes NVM Command Mode An NVM mode using the CPU to setup the FCCOB r...

Page 509: ...double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of D Flash memory Ability to program up to four words in a burst sequence 18 1 2 3 Other Flash Module Features No external high voltage power supply r...

Page 510: ... Flash module Read data from unimplemented memory space in the Flash module is undefined Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module Oscillator Clock Divider Clock XTAL Command Interrupt Request FCLK Protection Security Registers Flash Interface P Flash 32Kx72 sector 0 sector 1 sector 127 sector 0 sector 1 sector 127 16bit internal...

Page 511: ...ion that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 18 3 Table 18 2 P Flash Memory Addressing Global Address Size Bytes Description 0x7C_0000 0x7F_FFFF 256 K P Flash Block 0 Contains Flash Configuration Field see Table 18 3 Table 18 3 Flash Configuration Field1 1 Older versions may have swapped protection byte addresses G...

Page 512: ...Flash Protected Unprotected Lower Region 1 2 4 8 Kbytes 0x7F_8000 0x7F_9000 0x7F_8400 0x7F_8800 0x7F_A000 P Flash END 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x7F_FF00 0x7F_FF0F Flash Protected Unprotected Region 224 Kbytes P Flash START 0x7C_0000 ...

Page 513: ... Once Command 0x40_0140 0x40_01FF 192 Reserved Table 18 5 D Flash and Memory Controller Resource Fields Global Address Size Bytes Description 0x10_0000 0x10_1FFF 8 192 D Flash Memory 0x10_2000 0x11_FFFF 122 880 Reserved 0x12_0000 0x12_007F 128 D Flash Nonvolatile Information Register DFIFRON1 1 1 MMCCTL1 register bit 0x12_0080 0x12_0FFF 3 968 Reserved 0x12_1000 0x12_1FFF 4 096 Reserved 0x12_2000 0...

Page 514: ...wing subsections CAUTION Writes to any Flash register must be avoided while a Flash command is active CCIF 0 to prevent corruption of Flash register contents and Memory Controller behavior Address Name 7 6 5 4 3 2 1 0 0x0000 FCLKDIV R FDIVLD FDIV6 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W Figure 18 4 FTMR256K1 Register Summary 0x12_FFFF 0x12_...

Page 515: ... R 0 0 0 0 0 0 DFDIF SFDIF W 0x0008 FPROT R FPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0009 DFPROT R DPOPEN 0 0 DPS4 DPS3 DPS2 DPS1 DPS0 W 0x000A FCCOBHI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000B FCCOBLO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x000C FRSV0 R 0 0 0 0 0 0 0 0 W 0x000D FRSV1 R 0 0 0 0 0 0 0 0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12...

Page 516: ...6 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 5 Flash Clock Divider Register FCLKDIV Table 18 6 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divide OSCCLK down to generate an internal Fla...

Page 517: ...Family Reference Manual Rev 1 13 Freescale Semiconductor 517 CAUTION The FCLKDIV register should never be written while a Flash command is executing CCIF 0 The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear ...

Page 518: ...3 5 25 6 30 0x05 37 80 38 85 0x24 6 30 7 35 0x06 38 85 39 90 0x25 7 35 8 40 0x07 39 90 40 95 0x26 8 40 9 45 0x08 40 95 42 00 0x27 9 45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D 15 75 16 80 0x0F 48 30 49 35 0x2E 16 80 17 85 0x10 49 35 50 40 0x2F...

Page 519: ...key access disabled Offset Module Base 0x0001 7 6 5 4 3 2 1 0 R KEYEN 1 0 RNV 5 2 SEC 1 0 W Reset F F F F F F F F Unimplemented or Reserved Figure 18 6 Flash Security Register FSEC Table 18 8 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor key access to the Flash module as shown in Table 18 9 5 2 RNV 5 2 R...

Page 520: ...set Module Base 0x0002 7 6 5 4 3 2 1 0 R 0 0 0 0 0 CCOBIX 2 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 7 FCCOB Index Register FCCOBIX Table 18 11 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to See Section 18 3 2 11 Flash Common Command ...

Page 521: ...gle bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is det...

Page 522: ...Detect Interrupt Enable The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set see Section 18 3 2 8 0 SFDIE Single Bit Fault Detect Interrupt Enable The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash bloc...

Page 523: ...s no effect on ACCERR 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P Flash or D Flash memory during a command write sequence The FPVIOL bit is cleared by writing a 1 to FPVIOL Writing a 0 to the FPVIOL bit has no effect on FPVIOL While FPVIOL is set it i...

Page 524: ...he FPVIOL bit will be set in the FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected Table 18 16 FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits durin...

Page 525: ...rmine the size of the protected unprotected area in P Flash memory as shown inTable 18 19 The FPHS bits can only be written to while the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning with global address 0x7F_8000 0 Protection Unprotection enabled 1 ...

Page 526: ...0C during the reset sequence it can be changed by the user The P Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 18 20 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected Size 00 0x7F_8000 0x7F_83FF 1 Kbyte 01 0x7F_8000 0x7F_87FF 2 Kbytes ...

Page 527: ...HS 1 0 FPLS 1 0 3 2 1 0 FPHS 1 0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FLASH START FPOPEN 1 FPOPEN 0 ...

Page 528: ...ten from 1 protection disabled to 0 protection enabled If the DPOPEN bit is set the state of the DPS bits is irrelevant During the reset sequence the DFPROT register is loaded with the contents of the D Flash protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Flash memory see Table 18 3 as indicated by reset condition F in Figure 18 15 To change the D Flash p...

Page 529: ...n Size The DPS 4 0 bits determine the size of the protected area in the D Flash memory as shown in Table 18 23 Table 18 23 D Flash Protection Address Range DPS 4 0 Global Address Range Protected Size 0_0000 0x10_0000 0x10_00FF 256 bytes 0_0001 0x10_0000 0x10_01FF 512 bytes 0_0010 0x10_0000 0x10_02FF 768 bytes 0_0011 0x10_0000 0x10_03FF 1024 bytes 0_0100 0x10_0000 0x10_04FF 1280 bytes 0_0101 0x10_0...

Page 530: ...the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 0x10_16FF 5888 bytes 1_0111 0x10_0000 0x10_17FF 6144 bytes 1_1000 0x10_0000 0x10_18FF 6400 bytes 1_1001 0x10_0000 0x10_19FF 6656 bytes 1_1010 0x10_0000 0x10_1AFF 6912 bytes 1_1011 0x10_0000 0x10_1BFF 7168 bytes 1_1100 0x10_0000 0x10...

Page 531: ... the CCOB array contains the command code followed by the parameters for this specific Flash command For details on the FCCOB settings required by each command see the Flash command descriptions in Section 18 4 2 18 3 2 12 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing All bits in the FRSV0 register read 0 and are not writable Table 18 24 FCCOB NVM Command Mode ...

Page 532: ... fault information has been stored no other fault information will be recorded until the specific ECC fault flag has been cleared In the event of simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault All FECCR bits are readable but not writable Offset Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved ...

Page 533: ...le Table 18 25 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8 Bit 7 Bits 6 0 000 Parity bits read from Flash block 0 Global address 22 16 001 Global address 15 0 010 Data 0 15 0 011 Data 1 15 0 P Flash only 100 Data 2 15 0 P Flash only 101 Data 3 15 0 P Flash only 110 Not used returns 0x0000 when read 111 Not used returns 0x0000 when read Table 18 26 FECCR Index 000 Bit Descripti...

Page 534: ...ing All bits in the FRSV2 register read 0 and are not writable 18 3 2 17 Flash Reserved3 Register FRSV3 This Flash register is reserved for factory testing All bits in the FRSV3 register read 0 and are not writable 18 3 2 18 Flash Reserved4 Register FRSV4 This Flash register is reserved for factory testing Table 18 27 FOPT Field Descriptions Field Description 7 0 NV 7 0 Nonvolatile Bits The NV 7 0...

Page 535: ...ite the FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz Table 18 7 shows recommended values for the FDIV field based on OSCCLK frequency NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz Setting FDIV too high can destroy the Flash memory due to overstress Setting FDIV too low can result in incomplete programming or erasure of...

Page 536: ...ust be avoided while a Flash command is active CCIF 0 to prevent corruption of Flash register contents and Memory Controller behavior 18 4 1 2 1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register see Section 18 3 2 3 The conte...

Page 537: ...ccess Error and Protection Violation Read FSTAT register Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Completion Check yes CCIF Set to identify specific command parameter to load Write to FCCOB register to load required command parameter yes no More...

Page 538: ...nsecured Normal Expanded mode SS3 3 Unsecured Special Single Chip mode ST4 4 Unsecured Special Mode NS5 5 Secured Normal Single Chip mode NX6 6 Secured Normal Expanded mode SS7 7 Secured Special Single Chip mode ST8 8 Secured Special Mode 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P Flash Section 0x04 Read Once 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Block...

Page 539: ...ommand 0x09 Erase Flash Block Erase a P Flash or D Flash block An erase of the full P Flash block is only possible when FPLDIS FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command 0x0A Erase P Flash Sector Erase all bytes in a P Flash sector 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all P Flash and D Flash blocks and verifying that al...

Page 540: ...ta and parity fields set to all 0 If the ACCERR or FPVIOL bits are set in the FSTAT register the user must clear these bits before starting any command write sequence see Section 18 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash word or phrase is not allowed 18 4 2 1 Erase Verify All Blocks Command The Erase Ve...

Page 541: ...erify that a section of code in the P Flash memory is erased The Erase Verify P Flash Section command defines the starting point of the code to be verified and the number of phrases The section to be verified cannot cross a 256 Kbyte boundary in the P Flash memory space Table 18 32 Erase Verify All Blocks Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 000 ...

Page 542: ...t after the Read Once operation has completed Valid Table 18 35 Erase Verify P Flash Section Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x03 Global address 22 16 of a P Flash block 001 Global address 15 0 of the first phrase to be verified 010 Number of phrases to be verified Table 18 36 Erase Verify P Flash Section Command Error Handling Register Error Bit Error Condition FSTAT AC...

Page 543: ...ds to the supplied global address and will then proceed to verify the data words read back as expected The CCIF flag will set after the Program P Flash operation has completed Table 18 38 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 18 28 Set if an invalid phrase index...

Page 544: ...e information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed Valid phrase index values for the Program Once command range from 0x0000 to 0x0007 During execution of the Program Once command any attempt to read addresses within P Flash block 0 will return invalid data Table 18 40 Program P Flash Command...

Page 545: ...RR Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 18 28 Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 1 If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF the Program Once command will be allowed to execute again on that same phrase FPVIOL None MGSTAT1 Set if any errors have...

Page 546: ...000 0x09 Global address 22 16 to identify Flash block 001 Global address 15 0 in Flash block to be erased Table 18 46 Erase Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 18 28 Set if an invalid global address 22 16 is supplied Set if the supplied P Flash address is no...

Page 547: ...kdoor Access Key command releases security if user supplied keys match those stored in the Flash security bytes of the Flash configuration field see Table 18 48 Erase P Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 18 28 Set if an invalid global address 22 16 is supp...

Page 548: ...ify Backdoor Access Key command are aborted set ACCERR until a reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed 18 4 2 12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of a specific P Flash or D Flash block Table 18 51 Verify Backdoor Access Key Command FC...

Page 549: ...alid in special modes only causes the Memory Controller to set the margin level specified for future read operations of a specific P Flash or D Flash block Table 18 54 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level1 1 Read margin to the erased state 0x0002 User Margin 0 Level2 2 Read margin to the programmed state Tab...

Page 550: ... erased and reprogrammed 18 4 2 14 Erase Verify D Flash Section Command The Erase Verify D Flash Section command will verify that a section of code in the D Flash is erased The Erase Verify D Flash Section command defines the starting point of the data to be verified and the number of words Table 18 57 Valid Set Field Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal ...

Page 551: ...0 FCCOB Parameters 000 0x10 Global address 22 16 to identify the D Flash block 001 Global address 15 0 of the first word to be verified 010 Number of words to be verified Table 18 60 Erase Verify D Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Table 18 28 Set if an invali...

Page 552: ...3 program value if desired Table 18 62 Program D Flash Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 18 28 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the requeste...

Page 553: ...FG Section 18 3 2 7 Flash Status Register FSTAT and Section 18 3 2 8 Flash Error Status Register FERSTAT The logic used for generating the Flash module interrupts is shown in Figure 18 27 Table 18 64 Erase D Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 18 28 Set if ...

Page 554: ...amming the security byte of the Flash configuration field This assumes that you are starting from a mode where the necessary P Flash erase and program commands are available and that the upper region of the P Flash is unprotected If the Flash security byte is successfully programmed its new value will take affect after the next MCU reset The following subsections describe these security related su...

Page 555: ...y byte can be erased and the Flash security byte can be reprogrammed to the unsecure state if desired In the unsecure state the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00 0x7F_FF07 in the Flash configuration field The security as defined in the Flash security byte 0x7F_FF0F is not changed by using the Verify Backdoor Access Key command sequence Th...

Page 556: ...he FOPT and FSEC registers The Flash module reverts to built in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence If a double bit fault is detected during the reset sequence both MGSTAT bits in the FSTAT register will be set CCIF remains clear throughout the reset sequence The Flash module holds off all CPU ...

Page 557: ... Revision History Revision Number Revision Date Sections Affected Description of Changes V01 04 03 Jan 2008 Cosmetic changes V01 05 19 Dec 2008 19 1 19 557 19 4 2 4 19 592 19 4 2 6 19 594 19 4 2 11 19 59 7 19 4 2 11 19 59 7 19 4 2 11 19 59 7 Clarify single bit fault correction for P Flash phrase Add statement concerning code runaway when executing Read Once Program Once and Verify Backdoor Access ...

Page 558: ... to execute built in algorithms including program and erase on the Flash memory D Flash Memory The D Flash memory constitutes the nonvolatile memory store for data D Flash Sector The D Flash sector is the smallest portion of the D Flash memory that can be erased The D Flash sector consists of four 64 byte rows for a total of 256 bytes NVM Command Mode An NVM mode using the CPU to setup the FCCOB r...

Page 559: ...double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of D Flash memory Ability to program up to four words in a burst sequence 19 1 2 3 Other Flash Module Features No external high voltage power supply r...

Page 560: ...d registers for the Flash module Read data from unimplemented memory space in the Flash module is undefined Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module Oscillator Clock Divider Clock XTAL Command Interrupt Request FCLK Protection Security Registers Flash Interface 16bit internal bus sector 0 sector 1 sector 127 16Kx72 P Flash Error...

Page 561: ...ion that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 19 3 Table 19 2 P Flash Memory Addressing Global Address Size Bytes Description 0x7E_0000 0x7F_FFFF 128 K P Flash Block 0 Contains Flash Configuration Field see Table 19 3 Table 19 3 Flash Configuration Field1 1 Older versions may have swapped protection byte addresses G...

Page 562: ... Flash Protected Unprotected Lower Region 1 2 4 8 Kbytes 0x7F_8000 0x7F_9000 0x7F_8400 0x7F_8800 0x7F_A000 P Flash END 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x7F_FF00 0x7F_FF0F Flash Protected Unprotected Region 96 Kbytes P Flash START 0x7E_0000 ...

Page 563: ... Once Command 0x40_0140 0x40_01FF 192 Reserved Table 19 5 D Flash and Memory Controller Resource Fields Global Address Size Bytes Description 0x10_0000 0x10_1FFF 8 192 D Flash Memory 0x10_2000 0x11_FFFF 122 880 Reserved 0x12_0000 0x12_007F 128 D Flash Nonvolatile Information Register DFIFRON1 1 1 MMCCTL1 register bit 0x12_0080 0x12_0FFF 3 968 Reserved 0x12_1000 0x12_1FFF 4 096 Reserved 0x12_2000 0...

Page 564: ...wing subsections CAUTION Writes to any Flash register must be avoided while a Flash command is active CCIF 0 to prevent corruption of Flash register contents and Memory Controller behavior Address Name 7 6 5 4 3 2 1 0 0x0000 FCLKDIV R FDIVLD FDIV6 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W Figure 19 4 FTMR128K1 Register Summary 0x12_FFFF 0x12_...

Page 565: ... R 0 0 0 0 0 0 DFDIF SFDIF W 0x0008 FPROT R FPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0009 DFPROT R DPOPEN 0 0 DPS4 DPS3 DPS2 DPS1 DPS0 W 0x000A FCCOBHI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000B FCCOBLO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x000C FRSV0 R 0 0 0 0 0 0 0 0 W 0x000D FRSV1 R 0 0 0 0 0 0 0 0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12...

Page 566: ...6 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19 5 Flash Clock Divider Register FCLKDIV Table 19 6 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divide OSCCLK down to generate an internal Fla...

Page 567: ...Family Reference Manual Rev 1 13 Freescale Semiconductor 567 CAUTION The FCLKDIV register should never be written while a Flash command is executing CCIF 0 The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear ...

Page 568: ...3 5 25 6 30 0x05 37 80 38 85 0x24 6 30 7 35 0x06 38 85 39 90 0x25 7 35 8 40 0x07 39 90 40 95 0x26 8 40 9 45 0x08 40 95 42 00 0x27 9 45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D 15 75 16 80 0x0F 48 30 49 35 0x2E 16 80 17 85 0x10 49 35 50 40 0x2F...

Page 569: ...key access disabled Offset Module Base 0x0001 7 6 5 4 3 2 1 0 R KEYEN 1 0 RNV 5 2 SEC 1 0 W Reset F F F F F F F F Unimplemented or Reserved Figure 19 6 Flash Security Register FSEC Table 19 8 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor key access to the Flash module as shown in Table 19 9 5 2 RNV 5 2 R...

Page 570: ...set Module Base 0x0002 7 6 5 4 3 2 1 0 R 0 0 0 0 0 CCOBIX 2 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19 7 FCCOB Index Register FCCOBIX Table 19 11 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to See Section 19 3 2 11 Flash Common Command ...

Page 571: ...gle bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is det...

Page 572: ...Detect Interrupt Enable The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set see Section 19 3 2 8 0 SFDIE Single Bit Fault Detect Interrupt Enable The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash bloc...

Page 573: ...s no effect on ACCERR 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P Flash or D Flash memory during a command write sequence The FPVIOL bit is cleared by writing a 1 to FPVIOL Writing a 0 to the FPVIOL bit has no effect on FPVIOL While FPVIOL is set it i...

Page 574: ...he FPVIOL bit will be set in the FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected Table 19 16 FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits durin...

Page 575: ...rmine the size of the protected unprotected area in P Flash memory as shown inTable 19 19 The FPHS bits can only be written to while the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning with global address 0x7F_8000 0 Protection Unprotection enabled 1 ...

Page 576: ...0C during the reset sequence it can be changed by the user The P Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 19 20 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected Size 00 0x7F_8000 0x7F_83FF 1 Kbyte 01 0x7F_8000 0x7F_87FF 2 Kbytes ...

Page 577: ...HS 1 0 FPLS 1 0 3 2 1 0 FPHS 1 0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FLASH START FPOPEN 1 FPOPEN 0 ...

Page 578: ...ten from 1 protection disabled to 0 protection enabled If the DPOPEN bit is set the state of the DPS bits is irrelevant During the reset sequence the DFPROT register is loaded with the contents of the D Flash protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Flash memory see Table 19 3 as indicated by reset condition F in Figure 19 15 To change the D Flash p...

Page 579: ...n Size The DPS 4 0 bits determine the size of the protected area in the D Flash memory as shown in Table 19 23 Table 19 23 D Flash Protection Address Range DPS 4 0 Global Address Range Protected Size 0_0000 0x10_0000 0x10_00FF 256 bytes 0_0001 0x10_0000 0x10_01FF 512 bytes 0_0010 0x10_0000 0x10_02FF 768 bytes 0_0011 0x10_0000 0x10_03FF 1024 bytes 0_0100 0x10_0000 0x10_04FF 1280 bytes 0_0101 0x10_0...

Page 580: ...the user clears the CCIF bit in the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 0x10_16FF 5888 bytes 1_0111 0x10_0000 0x10_17FF 6144 bytes 1_1000 0x10_0000 0x10_18FF 6400 bytes 1_1001 0x10_0000 0x10_19FF 6656 bytes 1_1010 0x10_0000 0x10_1AFF 6912 bytes 1_1011 0x10_0000 0x10_1BFF 7168 bytes 1_1100 0x10_0000 0x10...

Page 581: ... the CCOB array contains the command code followed by the parameters for this specific Flash command For details on the FCCOB settings required by each command see the Flash command descriptions in Section 19 4 2 19 3 2 12 Flash Reserved0 Register FRSV0 This Flash register is reserved for factory testing All bits in the FRSV0 register read 0 and are not writable Table 19 24 FCCOB NVM Command Mode ...

Page 582: ... fault information has been stored no other fault information will be recorded until the specific ECC fault flag has been cleared In the event of simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault All FECCR bits are readable but not writable Offset Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved ...

Page 583: ...le Table 19 25 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8 Bit 7 Bits 6 0 000 Parity bits read from Flash block 0 Global address 22 16 001 Global address 15 0 010 Data 0 15 0 011 Data 1 15 0 P Flash only 100 Data 2 15 0 P Flash only 101 Data 3 15 0 P Flash only 110 Not used returns 0x0000 when read 111 Not used returns 0x0000 when read Table 19 26 FECCR Index 000 Bit Descripti...

Page 584: ...ing All bits in the FRSV2 register read 0 and are not writable 19 3 2 17 Flash Reserved3 Register FRSV3 This Flash register is reserved for factory testing All bits in the FRSV3 register read 0 and are not writable 19 3 2 18 Flash Reserved4 Register FRSV4 This Flash register is reserved for factory testing Table 19 27 FOPT Field Descriptions Field Description 7 0 NV 7 0 Nonvolatile Bits The NV 7 0...

Page 585: ...ite the FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz Table 19 7 shows recommended values for the FDIV field based on OSCCLK frequency NOTE Programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz Setting FDIV too high can destroy the Flash memory due to overstress Setting FDIV too low can result in incomplete programming or erasure of...

Page 586: ...ust be avoided while a Flash command is active CCIF 0 to prevent corruption of Flash register contents and Memory Controller behavior 19 4 1 2 1 Define FCCOB Contents The FCCOB parameter fields must be loaded with all required parameters for the Flash command being executed Access to the FCCOB parameter fields is controlled via the CCOBIX bits in the FCCOBIX register see Section 19 3 2 3 The conte...

Page 587: ...ccess Error and Protection Violation Read FSTAT register Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Completion Check yes CCIF Set to identify specific command parameter to load Write to FCCOB register to load required command parameter yes no More...

Page 588: ...nsecured Normal Expanded mode SS3 3 Unsecured Special Single Chip mode ST4 4 Unsecured Special Mode NS5 5 Secured Normal Single Chip mode NX6 6 Secured Normal Expanded mode SS7 7 Secured Special Single Chip mode ST8 8 Secured Special Mode 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P Flash Section 0x04 Read Once 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Block...

Page 589: ...ommand 0x09 Erase Flash Block Erase a P Flash or D Flash block An erase of the full P Flash block is only possible when FPLDIS FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command 0x0A Erase P Flash Sector Erase all bytes in a P Flash sector 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all P Flash and D Flash blocks and verifying that al...

Page 590: ...ta and parity fields set to all 0 If the ACCERR or FPVIOL bits are set in the FSTAT register the user must clear these bits before starting any command write sequence see Section 19 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash word or phrase is not allowed 19 4 2 1 Erase Verify All Blocks Command The Erase Ve...

Page 591: ...erify that a section of code in the P Flash memory is erased The Erase Verify P Flash Section command defines the starting point of the code to be verified and the number of phrases The section to be verified cannot cross a 128 Kbyte boundary in the P Flash memory space Table 19 32 Erase Verify All Blocks Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 000 ...

Page 592: ...t after the Read Once operation has completed Valid Table 19 35 Erase Verify P Flash Section Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x03 Global address 22 16 of a P Flash block 001 Global address 15 0 of the first phrase to be verified 010 Number of phrases to be verified Table 19 36 Erase Verify P Flash Section Command Error Handling Register Error Bit Error Condition FSTAT AC...

Page 593: ...ds to the supplied global address and will then proceed to verify the data words read back as expected The CCIF flag will set after the Program P Flash operation has completed Table 19 38 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 19 28 Set if an invalid phrase index...

Page 594: ...e information register accessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed Valid phrase index values for the Program Once command range from 0x0000 to 0x0007 During execution of the Program Once command any attempt to read addresses within P Flash block 0 will return invalid data Table 19 40 Program P Flash Command...

Page 595: ...RR Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 19 28 Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 1 If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF the Program Once command will be allowed to execute again on that same phrase FPVIOL None MGSTAT1 Set if any errors have...

Page 596: ...000 0x09 Global address 22 16 to identify Flash block 001 Global address 15 0 in Flash block to be erased Table 19 46 Erase Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 19 28 Set if an invalid global address 22 16 is supplied Set if the supplied P Flash address is no...

Page 597: ...kdoor Access Key command releases security if user supplied keys match those stored in the Flash security bytes of the Flash configuration field see Table 19 48 Erase P Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 19 28 Set if an invalid global address 22 16 is supp...

Page 598: ...ify Backdoor Access Key command are aborted set ACCERR until a reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed 19 4 2 12 Set User Margin Level Command The Set User Margin Level command causes the Memory Controller to set the margin level for future read operations of a specific P Flash or D Flash block Table 19 51 Verify Backdoor Access Key Command FC...

Page 599: ...alid in special modes only causes the Memory Controller to set the margin level specified for future read operations of a specific P Flash or D Flash block Table 19 54 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level1 1 Read margin to the erased state 0x0002 User Margin 0 Level2 2 Read margin to the programmed state Tab...

Page 600: ... erased and reprogrammed 19 4 2 14 Erase Verify D Flash Section Command The Erase Verify D Flash Section command will verify that a section of code in the D Flash is erased The Erase Verify D Flash Section command defines the starting point of the data to be verified and the number of words Table 19 57 Valid Set Field Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal ...

Page 601: ...0 FCCOB Parameters 000 0x10 Global address 22 16 to identify the D Flash block 001 Global address 15 0 of the first word to be verified 010 Number of words to be verified Table 19 60 Erase Verify D Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Table 19 28 Set if an invali...

Page 602: ...3 program value if desired Table 19 62 Program D Flash Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if CCOBIX 2 0 101 at command launch Set if command not available in current mode see Table 19 28 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied global address 0 0 Set if the requeste...

Page 603: ...FG Section 19 3 2 7 Flash Status Register FSTAT and Section 19 3 2 8 Flash Error Status Register FERSTAT The logic used for generating the Flash module interrupts is shown in Figure 19 27 Table 19 64 Erase D Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 19 28 Set if ...

Page 604: ...amming the security byte of the Flash configuration field This assumes that you are starting from a mode where the necessary P Flash erase and program commands are available and that the upper region of the P Flash is unprotected If the Flash security byte is successfully programmed its new value will take affect after the next MCU reset The following subsections describe these security related su...

Page 605: ...y byte can be erased and the Flash security byte can be reprogrammed to the unsecure state if desired In the unsecure state the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00 0x7F_FF07 in the Flash configuration field The security as defined in the Flash security byte 0x7F_FF0F is not changed by using the Verify Backdoor Access Key command sequence Th...

Page 606: ...he FOPT and FSEC registers The Flash module reverts to built in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence If a double bit fault is detected during the reset sequence both MGSTAT bits in the FSTAT register will be set CCIF remains clear throughout the reset sequence The Flash module holds off all CPU ...

Page 607: ...evision History Revision Number Revision Date Sections Affected Description of Changes V01 04 03 Jan 2008 Cosmetic changes V01 05 19 Dec 2008 20 1 20 607 20 4 2 4 20 642 20 4 2 6 20 644 20 4 2 11 20 64 8 20 4 2 11 20 64 8 20 4 2 11 20 64 8 Clarify single bit fault correction for P Flash phrase Add statement concerning code runaway when executing Read Once Program Once and Verify Backdoor Access Ke...

Page 608: ... to execute built in algorithms including program and erase on the Flash memory D Flash Memory The D Flash memory constitutes the nonvolatile memory store for data D Flash Sector The D Flash sector is the smallest portion of the D Flash memory that can be erased The D Flash sector consists of four 64 byte rows for a total of 256 bytes NVM Command Mode An NVM mode using the CPU to setup the FCCOB r...

Page 609: ...6 bytes Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verify and generation of ECC parity bits Fast sector erase and word program operation Protection scheme to prevent accidental program or erase of D Flash memory Ability to program up to four words in a burst sequence 20 1 2 3 Other Flash Module Features...

Page 610: ... FTMR64K1 Block Diagram 20 2 External Signal Description The Flash module contains no signals that connect off chip Oscillator Clock Divider Clock XTAL Command Interrupt Request FCLK Protection Security Registers Flash Interface 16bit internal bus sector 0 sector 1 sector 63 8Kx72 P Flash Error Interrupt Request CPU D Flash 2Kx22 sector 0 sector 1 sector 15 Scratch RAM 384x16bits Memory Controller...

Page 611: ...vered by these protectable regions are shown in the P Flash memory map The higher address region is mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 20 3 Table 20 2 P Flash Memory Addres...

Page 612: ...XS Family Reference Manual Rev 1 13 612 Freescale Semiconductor 2 0x7FF08 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F_FF0B reserved field should be programmed to 0xFF ...

Page 613: ...Flash Protected Unprotected Lower Region 1 2 4 8 Kbytes 0x7F_8000 0x7F_9000 0x7F_8400 0x7F_8800 0x7F_A000 P Flash END 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected Region 8 Kbytes up to 29 Kbytes 16 bytes 0x7F_FF00 0x7F_FF0F Flash Protected Unprotected Region 32 Kbytes P Flash START 0x7F_0000 ...

Page 614: ...Once Command 0x40_0140 0x40_01FF 192 Reserved Table 20 5 D Flash and Memory Controller Resource Fields Global Address Size Bytes Description 0x10_0000 0x10_0FFF 4 096 D Flash Memory 0x10_1000 0x11_FFFF 126 976 Reserved 0x12_0000 0x12_007F 128 D Flash Nonvolatile Information Register DFIFRON1 1 1 MMCCTL1 register bit 0x12_0080 0x12_0FFF 3 968 Reserved 0x12_1000 0x12_1FFF 4 096 Reserved 0x12_2000 0x...

Page 615: ...ing subsections CAUTION Writes to any Flash register must be avoided while a Flash command is active CCIF 0 to prevent corruption of Flash register contents and Memory Controller behavior Address Name 7 6 5 4 3 2 1 0 0x0000 FCLKDIV R FDIVLD FDIV6 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W Figure 20 4 FTMR64K1 Register Summary 0x12_FFFF 0x12_40...

Page 616: ...R 0 0 0 0 0 0 DFDIF SFDIF W 0x0008 FPROT R FPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0009 DFPROT R DPOPEN 0 0 DPS4 DPS3 DPS2 DPS1 DPS0 W 0x000A FCCOBHI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000B FCCOBLO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x000C FRSV0 R 0 0 0 0 0 0 0 0 W 0x000D FRSV1 R 0 0 0 0 0 0 0 0 W 0x000E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ...

Page 617: ... 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20 5 Flash Clock Divider Register FCLKDIV Table 20 6 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divide OSCCLK down to generate an internal Flas...

Page 618: ...amily Reference Manual Rev 1 13 618 Freescale Semiconductor CAUTION The FCLKDIV register should never be written while a Flash command is executing CCIF 0 The FCLKDIV register is writable during the Flash reset sequence even though CCIF is clear ...

Page 619: ... 5 25 6 30 0x05 37 80 38 85 0x24 6 30 7 35 0x06 38 85 39 90 0x25 7 35 8 40 0x07 39 90 40 95 0x26 8 40 9 45 0x08 40 95 42 00 0x27 9 45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A 12 60 13 65 0x0C 45 15 46 20 0x2B 13 65 14 70 0x0D 46 20 47 25 0x2C 14 70 15 75 0x0E 47 25 48 30 0x2D 15 75 16 80 0x0F 48 30 49 35 0x2E 16 80 17 85 0x10 49 35 50 40 0x2F ...

Page 620: ...ey access disabled Offset Module Base 0x0001 7 6 5 4 3 2 1 0 R KEYEN 1 0 RNV 5 2 SEC 1 0 W Reset F F F F F F F F Unimplemented or Reserved Figure 20 6 Flash Security Register FSEC Table 20 8 FSEC Field Descriptions Field Description 7 6 KEYEN 1 0 Backdoor Key Security Enable Bits The KEYEN 1 0 bits define the enabling of backdoor key access to the Flash module as shown in Table 20 9 5 2 RNV 5 2 Re...

Page 621: ...et Module Base 0x0002 7 6 5 4 3 2 1 0 R 0 0 0 0 0 CCOBIX 2 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20 7 FCCOB Index Register FCCOBIX Table 20 11 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Common Command Register Index The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to See Section 20 3 2 11 Flash Common Command O...

Page 622: ...le bit fault interrupt will not be generated 1 FDFD Force Double Bit Fault Detect The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine The FDFD bit is cleared by writing a 0 to FDFD The FECCR registers will not be updated during the Flash array read operation with FDFD set unless an actual double bit fault is dete...

Page 623: ...etect Interrupt Enable The DFDIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set see Section 20 3 2 8 0 SFDIE Single Bit Fault Detect Interrupt Enable The SFDIE bit controls interrupt generation when a single bit fault is detected during a Flash block...

Page 624: ... no effect on ACCERR 0 No access error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P Flash or D Flash memory during a command write sequence The FPVIOL bit is cleared by writing a 1 to FPVIOL Writing a 0 to the FPVIOL bit has no effect on FPVIOL While FPVIOL is set it is...

Page 625: ...e FPVIOL bit will be set in the FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected Table 20 16 FERSTAT Field Descriptions Field Description 1 DFDIF Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during...

Page 626: ...mine the size of the protected unprotected area in P Flash memory as shown inTable 20 19 The FPHS bits can only be written to while the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determines whether there is a protected unprotected area in a specific region of the P Flash memory beginning with global address 0x7F_8000 0 Protection Unprotection enabled 1 P...

Page 627: ...C during the reset sequence it can be changed by the user The P Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required Table 20 20 P Flash Protection Lower Address Range FPLS 1 0 Global Address Range Protected Size 00 0x7F_8000 0x7F_83FF 1 Kbyte 01 0x7F_8000 0x7F_87FF 2 Kbytes 1...

Page 628: ...S 1 0 FPLS 1 0 3 2 1 0 FPHS 1 0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined by FPLS defined by FPHS not defined by FPLS FPHS 0x7F_8000 0x7F_FFFF 0x7F_8000 0x7F_FFFF FLASH START FLASH START FPOPEN 1 FPOPEN 0 ...

Page 629: ...en from 1 protection disabled to 0 protection enabled If the DPOPEN bit is set the state of the DPS bits is irrelevant During the reset sequence the DFPROT register is loaded with the contents of the D Flash protection byte in the Flash configuration field at global address 0x7F_FF0D located in P Flash memory see Table 20 3 as indicated by reset condition F in Figure 20 15 To change the D Flash pr...

Page 630: ...h Protection Control 0 Enables D Flash memory protection from program and erase with protected address range defined by DPS bits 1 Disables D Flash memory protection from program and erase 4 0 DPS 4 0 D Flash Protection Size The DPS 4 0 bits determine the size of the protected area in the D Flash memory as shown in Table 20 23 Table 20 23 D Flash Protection Address Range DPS 4 0 Global Address Ran...

Page 631: ...e available for reading after the CCIF flag in the FSTAT register has been returned to 1 by the Memory Controller Writes to the unimplemented parameter fields CCOBIX 110 and CCOBIX 111 are ignored with reads from these fields returning 0x0000 Table 20 24 shows the generic Flash command format The high byte of the first word in the CCOB array contains the command code followed by the parameters for...

Page 632: ... bit and double bit faults The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits in the FECCRIX register see Section 20 3 2 4 Once ECC fault information has been stored no other 011 HI Data 1 15 8 LO Data 1 7 0 100 HI Data 2 15 8 LO Data 2 7 0 101 HI Data 3 15 8 LO Data 3 7 0 Offset Module Base 0x000C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 ...

Page 633: ... or Reserved Figure 20 21 Flash ECC Error Results Low Register FECCRLO Table 20 25 FECCR Index Settings ECCRIX 2 0 FECCR Register Content Bits 15 8 Bit 7 Bits 6 0 000 Parity bits read from Flash block 0 Global address 22 16 001 Global address 15 0 010 Data 0 15 0 011 Data 1 15 0 P Flash only 100 Data 2 15 0 P Flash only 101 Data 3 15 0 P Flash only 110 Not used returns 0x0000 when read 111 Not use...

Page 634: ...in the Flash configuration field at global address 0x7F_FF0E located in P Flash memory see Table 20 3 as indicated by reset condition F in Figure 20 22 If a double bit fault is detected while reading the P Flash phrase containing the Flash nonvolatile byte during the reset sequence all bits in the FOPT register will be set 20 3 2 16 Flash Reserved2 Register FRSV2 This Flash register is reserved fo...

Page 635: ...ash command operations are used to modify Flash memory contents The next sections describe How to write the FCLKDIV register that is used to generate a time base FCLK derived from OSCCLK for Flash program and erase command operations The command write sequence used to set Flash command parameters and launch execution Valid Flash commands available for execution Offset Module Base 0x0012 7 6 5 4 3 ...

Page 636: ...s entered using a command write sequence Before launching a command the ACCERR and FPVIOL bits in the FSTAT register must be clear see Section 20 3 2 7 and the CCIF flag should be tested to determine the status of the current command write sequence If CCIF is 0 the previous command write sequence is still active a new command write sequence cannot be started and all writes to the FCCOB register ar...

Page 637: ...cess Error and Protection Violation Read FSTAT register Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no Bit Polling for Command Completion Check yes CCIF Set to identify specific command parameter to load Write to FCCOB register to load required command parameter yes no More ...

Page 638: ...secured Normal Expanded mode SS3 3 Unsecured Special Single Chip mode ST4 4 Unsecured Special Mode NS5 5 Secured Normal Single Chip mode NX6 6 Secured Normal Expanded mode SS7 7 Secured Special Single Chip mode ST8 8 Secured Special Mode 0x01 Erase Verify All Blocks 0x02 Erase Verify Block 0x03 Erase Verify P Flash Section 0x04 Read Once 0x06 Program P Flash 0x07 Program Once 0x08 Erase All Blocks...

Page 639: ...mmand 0x09 Erase Flash Block Erase a P Flash or D Flash block An erase of the full P Flash block is only possible when FPLDIS FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command 0x0A Erase P Flash Sector Erase all bytes in a P Flash sector 0x0B Unsecure Flash Supports a method of releasing MCU security by erasing all P Flash and D Flash blocks and verifying that all...

Page 640: ...a and parity fields set to all 0 If the ACCERR or FPVIOL bits are set in the FSTAT register the user must clear these bits before starting any command write sequence see Section 20 3 2 7 CAUTION A Flash word or phrase must be in the erased state before being programmed Cumulative programming of bits within a Flash word or phrase is not allowed 20 4 2 1 Erase Verify All Blocks Command The Erase Ver...

Page 641: ...e Verify P Flash Section command defines the starting point of the code to be verified and the number of phrases The section to be verified cannot cross a 128 Kbyte boundary in the P Flash memory space Table 20 32 Erase Verify All Blocks Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 000 at command launch FPVIOL None MGSTAT1 Set if any errors have been enc...

Page 642: ...ers 000 0x03 Global address 22 16 of a P Flash block 001 Global address 15 0 of the first phrase to be verified 010 Number of phrases to be verified Table 20 36 Erase Verify P Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if command not available in current mode see Table 20 28 Set if an invalid global address 22 0 ...

Page 643: ...earing CCIF to launch the Program P Flash command the Memory Controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected The CCIF flag will set after the Program P Flash operation has completed Table 20 38 Read Once Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command l...

Page 644: ...ccessed by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed Valid phrase index values for the Program Once command range from 0x0000 to 0x0007 During execution of the Program Once command any attempt to read addresses within P Flash block 0 will return invalid data Table 20 40 Program P Flash Command Error Handling Register...

Page 645: ... at command launch Set if command not available in current mode see Table 20 28 Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 1 If a Program Once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF the Program Once command will be allowed to execute again on that same phrase FPVIOL None MGSTAT1 Set if any errors have been encountered during...

Page 646: ... block 001 Global address 15 0 in Flash block to be erased Table 20 46 Erase Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 20 28 Set if an invalid global address 22 16 is supplied1 1 As defined by the memory map for FTMR128K1 Set if the supplied P Flash address is not...

Page 647: ...Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 20 28 Set if an invalid global address 22 16 is supplied1 1 As defined by the memory map for FTMR128K1 Set if a misaligned phrase address is supplied global address 2 0 000 FPVIOL Set if the selected P Flash sector is protected MGSTAT1 Set if any errors have been en...

Page 648: ... the backdoor comparison key in the Flash configuration field with Key 0 compared to 0x7F_FF00 etc If the backdoor keys match security will be released If the backdoor keys do not match security is not released and all future attempts to execute the Verify Backdoor Access Key command are aborted set ACCERR until a reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has...

Page 649: ...s been detected Table 20 53 Set User Margin Level Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x0D Global address 22 16 to identify the Flash block 001 Margin level setting Table 20 54 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level1 1 Read margin to the erased state 0x0002 User Margin 0 Level2 2 Read ma...

Page 650: ...ry programming Table 20 56 Set Field Margin Level Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x0E Global address 22 16 to identify the Flash block 001 Margin level setting Table 20 57 Valid Set Field Margin Level Settings CCOB CCOBIX 001 Level Description 0x0000 Return to Normal Level 0x0001 User Margin 1 Level1 1 Read margin to the erased state 0x0002 User Margin 0 Level2 2 Read m...

Page 651: ... Section operation has completed 20 4 2 15 Program D Flash Command The Program D Flash operation programs one to four previously erased words in the D Flash block The Program D Flash operation will confirm that the targeted location s were successfully programmed upon completion Table 20 59 Erase Verify D Flash Section Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x10 Global address ...

Page 652: ...ess 22 16 to identify the D Flash block 001 Global address 15 0 of word to be programmed 010 Word 0 program value 011 Word 1 program value if desired 100 Word 2 program value if desired 101 Word 3 program value if desired Table 20 62 Program D Flash Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if CCOBIX 2 0 101 at command launch...

Page 653: ... anywhere within the sector to be erased See Section 20 1 2 2 for D Flash sector size Table 20 64 Erase D Flash Sector Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 at command launch Set if command not available in current mode see Table 20 28 Set if an invalid global address 22 0 is supplied Set if a misaligned word address is supplied global address...

Page 654: ...e completed before the CPU is allowed to enter stop mode 20 5 Security The Flash module provides security information to the MCU The Flash security state is defined by the SEC bits of the FSEC register see Table 20 10 During reset the Flash module initializes the FSEC register using data read from the security byte of the Flash configuration field at global address 0x7F_FF0F The security state out...

Page 655: ...unsecured and the SEC 1 0 bits in the FSEC register are forced to the unsecure state of 10 The Verify Backdoor Access Key command is monitored by the Memory Controller and an illegal key will prohibit future use of the Verify Backdoor Access Key command A reset of the MCU is the only method to re enable the Verify Backdoor Access Key command After the backdoor keys have been correctly matched the ...

Page 656: ...operating mode and security state as shown in Table 20 28 20 6 Initialization On each system reset the Flash module executes a reset sequence which establishes initial values for the Flash Block Configuration Parameters the FPROT and DFPROT protection registers and the FOPT and FSEC registers The Flash module reverts to built in default values that leave the module in a fully protected and secured...

Page 657: ...tomer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled C in the parameter tables where appropriate P Those parameters are guaranteed during production testing on each individual device C Those parameters are achieved by the design characterization by measurin...

Page 658: ... following context VDD35 is used for either VDDA VDDR and VDDX VSS35 is used for either VSSA and VSSX unless otherwise noted IDD35 denotes the sum of the currents flowing into the VDDA and VDDR pins The Run mode current in the VDDX domain is external load dependent VDD is used for VDD VSS is used for VSS1 VSS2 and VSS3 VDDPLL is used for VDDPLL VSSPLL is used for VSSPLL IDD is used for the sum of ...

Page 659: ...urrent This will be the greatest risk when the MCU is not consuming power e g if no system clock is present or if clock rate is very low which would reduce overall power consumption A 1 5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only A functional operation under or outside those maxima is not guaranteed Stress beyond those limits may affect the reliability or cause perm...

Page 660: ...ax Unit 1 I O regulator and analog supply voltage VDD35 0 3 6 0 V 2 Digital logic supply voltage2 2 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an external source VDD 0 3 2 16 V 3 PLL supply voltage2 VDDPLL 0 3 2 16 V 4 NVM supply voltage2 VDDF 0 3 3 6 V 5 Voltage dif...

Page 661: ...stance R1 1500 Ohm Storage capacitance C 100 pF Number of pulse per pin Positive Negative 1 1 Charged Device Number of pulse per pin Positive Negative 3 3 Latch up Minimum input voltage limit 2 5 V Maximum input voltage limit 7 5 V Table A 3 ESD and Latch Up Protection Characteristics Num C Rating Symbol Min Max Unit 1 C Human Body Model HBM VHBM 2000 V 2 C Charge Device Model CDM corner pins Char...

Page 662: ... fbus 0 5 40 MHz Temperature Option C Operating junction temperature range Operating ambient temperature range4 TJ TA 40 40 27 110 85 C Temperature Option V Operating junction temperature range Operating ambient temperature range4 TJ TA 40 40 27 130 105 C Temperature Option M Operating junction temperature range Operating ambient temperature range4 TJ TA 40 40 27 150 125 C 1 The device contains an...

Page 663: ...th VDDX whereby Two cases with internal voltage regulator enabled and disabled must be considered 1 Internal voltage regulator disabled 2 Internal voltage regulator enabled P D P INT P IO P INT Chip Internal Power Dissipation W P IO R DSON i I IOi 2 R DSON V OL I OL for outputs driven low R DSON V DD35 V OH I OH for outputs driven high P INT I DD V DD I DDPLL V DDPLL I DDA V DDA P INT I DDR V DDR ...

Page 664: ... D Thermal resistance QFP 80 double sided PCB with 2 internal planes3 θJA 45 C W 8 D Junction to Board QFP 80 θJB 29 C W 9 D Junction to Case QFP 804 4 Junction to case thermal resistance was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the case temperature This basic cold plate measurement technique is described by MIL ST...

Page 665: ... W 14 D Junction to Case LQFP 644 θJC 13 C W 15 D Junction to Package Top LQFP 645 ΨJT 2 C W 1 The values for thermal resistance are achieved by package simulations 2 Junction to ambient thermal resistance θJA was simulated to be equivalent to the JEDEC specification JESD51 2 in a horizontal configuration in natural convection 3 Junction to ambient thermal resistance θJA was simulated to be equiva...

Page 666: ...Temperature range 40 C to 150 C V Temperature range 40 C to 130 C C Temperature range 40 C to 110 C I in 1 0 75 0 5 1 0 75 0 5 µA 4b C Input leakage current pins in high impedance input mode Vin VDD35 or VSS35 40 C 27 C 70 C 85 C 100 C 105 C 110 C 120 C 125 C 130 C 150 C I in 1 1 8 14 26 32 40 60 74 92 240 nA 5 C Output high voltage pins in output mode Partial drive IOH 0 75 mA V OH VDD35 0 4 V 6 ...

Page 667: ... passed STOP tPULSE 4 tcyc 17 D IRQ pulse width edge sensitive mode STOP PWIRQ 1 tcyc 18 D XIRQ pulse width with X bit set STOP PWXIRQ 4 tosc 1 Maximum leakage current occurs at maximum operating temperature 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only applies in stop or pseudo stop mode Table A 7 3 3 V I O Characteristics Conditions are 3 13 V VDD35 3 6 V junction ...

Page 668: ...ns in high impedance input mode Vin VDD35 or VSS35 40 C 27 C 70 C 85 C 100 C 105 C 110 C 120 C 125 C 130 C 150 C I in 1 1 8 14 26 32 40 60 74 92 240 nA 5 C Output high voltage pins in output mode Partial drive IOH 2 mA V OH VDD35 0 8 V 6 P Output high voltage pins in output mode Full drive IOH 10 mA VOH VDD35 0 8 V 7 C Output low voltage pins in output mode Partial drive IOL 2 mA VOL 0 8 V 8 P Out...

Page 669: ... frequency from a 4MHz input Characterized parameters are derived using a 16 D Port H J P interrupt input pulse passed STOP tPULSE 4 tcyc 17 D IRQ pulse width edge sensitive mode STOP PWIRQ 1 tcyc 18 D XIRQ pulse width with X bit set STOP PWXIRQ 4 tosc 1 Maximum leakage current occurs at maximum operating temperature 2 Refer to Section A 1 4 Current Injection for more details 3 Parameter only appl...

Page 670: ...Run Supply VDDR VDDA Current VDD35 5 5V Peripheral Configuration S12XCPU 420 cycle loop 384 DBNE cycles plus subroutine entry to stimulate stacking RAM access MSCAN Configured to loop back mode using a bit rate of 1Mbit s SPI Configured to master mode continuously transmit data 0x55 or 0xAA at 4Mbit s SCI Configured into loop mode continuously transmit data 0x55 at speed of 57600 baud PWM Configur...

Page 671: ... SCI0 SCI1 CAN0 IDD35 22 12 5 7 mA 3 T T T Peripheral Set2 fosc 4MHz fbus 40MHz fosc 4MHz fbus 20MHz fosc 4MHz fbus 8MHz 2 The following peripherals are on ATD0 TIM PWM SPI0 SCI0 SCI1 21 12 7 4 T T T Peripheral Set3 fosc 4MHz fbus 40MHz fosc 4MHz fbus 20MHz fosc 4MHz fbus 8MHz 3 The following peripherals are on ATD0 TIM PWM SPI0 21 11 6 5 T T T Peripheral Set4 fosc 4MHz fbus 40MHz fosc 4MHz fbus 2...

Page 672: ... 300 400 µA Pseudo stop current API RTI and COP disabled PLL off FSP mode 10b P P P P P 40 C 27 C 110 C 130 C 150 C IDDPS 60 70 160 210 400 80 100 2400 2400 2400 µA Pseudo stop current API RTI and COP enabled PLL off LCP mode 11 C C C C C C 27 C 70 C 85 C 105 C 125 C 150 C IDDPS 186 209 245 270 383 487 µA Stop Current 12 P P C C C C C C P 40 C 27 C 70 C 85 C 105 C 110 C 125 C 130 C 150 C IDDS 20 2...

Page 673: ...l design measures are implemented to minimize the affect of output driver noise it Conditions are shown in Table A 4 unless otherwise noted supply voltage 3 13 V VDDA 5 5 V Num C Rating Symbol Min Typ Max Unit 1 D Reference potential Low High VRL VRH VSSA VDDA 2 VDDA 2 VDDA V V 2 D Voltage difference VDDX to VDDA VDDX 2 35 0 0 1 V 3 D Voltage difference VSSX to VSSA VSSX 0 1 0 0 1 V 4 C Differenti...

Page 674: ...rce Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage 1LSB 10 bit resilution then the external filter capacitor Cf 1024 CINS CINN A 2 2 4 Current Injection There are two cases to consider 1 A current is injected into the c...

Page 675: ...Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 C Max input source resistance1 1 Refer to A 2 2 2 for further information concerning source resistance RS 1 KΩ 2 D Total input capacitance Non sampling Total input capacitance Sampling CINN CINS 10 16 pF 3 D Input internal Resistance RINA 5 15 kΩ 4 C Disruptive analog input current INA 2 5 2 5 mA 5 C Co...

Page 676: ...2 3 1 ATD Accuracy Definitions For the following definitions see also Figure A 1 Differential non linearity DNL is defined as the difference between two adjacent switching steps The integral non linearity INL is defined as the sum of all DNLs DNL i V i V i 1 1LSB 1 INL n DNL i i 1 n V n V 0 1LSB n ...

Page 677: ... values refer to Table A 16 and Table A 17 1 5 Vin mV 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 65 70 75 80 60 0 3 2 5 4 7 6 45 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal Transfer Curve 10 Bit Transfer Curve 8 Bit Transfer Curve 55 10 Bit Absolute Error Boundary 8 Bit Absolute Error Boundary LSB Vi 1 Vi DNL 5000 ...

Page 678: ...nts 9 C Resolution 8 Bit LSB 20 mV 10 C Differential Nonlinearity 8 Bit DNL 0 5 0 3 0 5 counts 11 C Integral Nonlinearity 8 Bit INL 1 0 5 1 counts 12 C Absolute Error3 8 Bit AE 1 5 1 1 5 counts Conditions are shown in Table A 4 unless otherwise noted VREF VRH VRL 3 3V fATDCLK 8 0MHz The values are tested to be valid with no PortAD output drivers switching simultaneous with conversions Num C Rating...

Page 679: ...maximum fNVMBUS unless otherwise shown The maximum times are calculated for minimum fNVMOP A 3 1 1 Erase Verify All Blocks Blank Check FCMD 0x01 The time it takes to perform a blank check is dependant on the location of the first non blank word starting at relative address zero It takes one bus cycle per phrase to verify plus a setup of the command Assuming that no non blank location is found then...

Page 680: ...cy fNVMOP and can be calculated according to the following formulas The typical phrase programming time can be calculated using the following equation The maximum phrase programming time can be calculated using the following equation A 3 1 6 P Flash Program Once FCMD 0x07 The maximum P Flash Program Once time is given by A 3 1 7 Erase All Blocks FCMD 0x08 Erasing all blocks takes t 400 1 fNVMBUS t...

Page 681: ...10 Unsecure Flash FCMD 0x0B The maximum time for unsecuring the flash is given by A 3 1 11 Verify Backdoor Access Key FCMD 0x0C The maximum verify backdoor access key time is given by A 3 1 12 Set User Margin Level FCMD 0x0D The maximum set user margin level time is given by A 3 1 13 Set Field Margin Level FCMD 0x0E The maximum set field margin level time is given by t mass 100100 1 f NVMOP 70000 ...

Page 682: ...ing the following equation whereby Nw denotes the number of words BC 0 if no boundary is crossed and BC 1 if a boundary is crossed The maximum programming time can be calculated using the following equation A 3 1 16 Erase D Flash Sector FCMD 0x12 Typical D Flash sector erase times are those expected on a new device where no margin verify fails occur They can be calculated using the following equat...

Page 683: ...ith 40MHz bus and fNVMOP 1MHz unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D External oscillator clock fNVMOSC 2 401 1 Restrictions for oscillator in crystal mode apply MHz 2 D Bus frequency for programming or erase operations fNVMBUS 1 40 MHz 3 D Operating frequency fNVMOP 800 1050 kHz 4 D P Flash phrase programming tbwpgm 171 183 µs 6 P P Flash sector erase time tera 20 21 ms 7 ...

Page 684: ...nes Typical Data Retention please refer to Engineering Bulletin EB618 Years 2 C Data retention at an average junction temperature of TJavg 85 C3 after less than 100 program erase cycles 3 TJavg does not exceed 85 C in a typical temperature profile over the lifetime of a consumer industrial or automotive application tPNVMRET 20 1002 Years 3 C P Flash number of program erase cycles 40 C tj 150 C nPF...

Page 685: ...e only in Full Performance Mode Indicates I O ADC performance degradation due to low supply voltage VLVIA VLVID 4 04 4 19 4 23 4 38 4 40 4 49 V V 6 P VDDX Low Voltage Reset 2 3 Assert Level Deassert Level 2 Device functionality is guaranteed on power down to the LVR assert level 3 Monitors VDDX active only in Full Performance Mode MCU is monitored by the POR in RPM see Figure A 2 VLVRXA VLVRXD 3 0...

Page 686: ... A 5 3 Chip Power up and Voltage Drops LVI low voltage interrupt POR power on reset and LVRs low voltage reset handle chip power up or drops of the supply voltage Their function is shown in Figure A 2 Figure A 2 S12XS family Chip Power up and Voltage Drops not scaled Table A 21 S12XS family Capacitive Loads Num Characteristic Symbol Min Recommended Max Unit 1 VDD VDDF external capacitive load CDDe...

Page 687: ...ductor 687 Figure A 3 S12XS family Power Sequencing During power sequencing VDDA can be powered up before VDDR VDDX VDDR and VDDX must be powered up together adhering to the operating conditions differential VRH power up must follow VDDA to avoid current injection VDDR VDDA t V VDDX 0 ...

Page 688: ...m executing code when VDD35 is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG flags register has not been set A 6 1 3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset and the CPU starts fetching the reset vector without doing a clock quality check if there was a...

Page 689: ...nductor 689 A 6 1 5 Pseudo Stop and Wait Recovery The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both modes The controller can be woken up by internal or external interrupts After twrs the CPU starts fetching the interrupt vector ...

Page 690: ... 5 2 40 ms 4b C Oscillator start up time full swing Pierce 4MHz 3 tUPOSC 3 20 ms 4c C Oscillator start up time full swing Pierce 8MHz 3 tUPOSC 1 8 10 ms 4d C Oscillator start up time full swing Pierce 16MHz 3 tUPOSC 1 2 5 ms 4e C Oscillator start up time full swing Pierce 40MHz 3 tUPOSC 1 4 ms 5 D Clock Quality check time out tCQOUT 0 45 2 5 s 6 P Clock Monitor Failure Assert Frequency fCMFA 200 4...

Page 691: ...th no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure A 4 Figure A 4 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period and decreases towards zero for larger num...

Page 692: ...SCM 1 4 MHz 2 T VCO locking range fVCO 32 120 MHz 3 T Reference Clock fREF 1 40 MHz 4 D Lock Detection Lock 0 1 5 2 2 deviation from target frequency 5 D Un Lock Detection unl 0 5 2 5 2 7 C Time to lock tlock 214 150 256 fREF µs 8 C Jitter fit parameter 13 3 fOSC 4MHz fBUS 40MHz equivalent fPLL 80MHz REFDIV 00 REFRQ 01 SYNDIV 09 VCOFRQ 01 POSTDIV 00 j1 1 2 9 C Jitter fit parameter 23 j2 0 10 C Bus...

Page 693: ...cale Semiconductor 693 A 7 MSCAN Table A 25 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P MSCAN wakeup dominant pulse filtered tWUP 1 5 µs 2 P MSCAN wakeup dominant pulse pass tWUP 5 µs ...

Page 694: ...d Figure A 6 SPI Master Timing CPHA 0 Table A 26 Measurement Conditions Description Value Unit Drive mode Full drive mode Load capacitance CLOAD 1 on all outputs 1 Timing specified for equal load on all SPI output pins Avoid asymmetric load 50 pF Thresholds for delay measurement points 20 80 VDDX V SCK Output SCK Output MISO Input MOSI Output SS Output 1 9 5 6 MSB IN2 Bit MSB 1 1 LSB IN MSB OUT2 L...

Page 695: ...tbus 2 D Enable lead time tlead 1 2 tsck 3 D Enable lag time tlag 1 2 tsck 4 D Clock SCK high or low time twsck 1 2 tsck 5 D Data setup time inputs tsu 8 ns 6 D Data hold time inputs thi 8 ns 9 D Data valid after SCK edge tvsck 29 ns 10 D Data valid after SS fall CPHA 0 tvss 15 ns 11 D Data hold time outputs tho 20 ns 12 D Rise and fall time inputs trfi 8 ns 13 D Rise and fall time outputs trfo 8 ...

Page 696: ...n Figure A 9 the timing diagram for slave mode with transmission format CPHA 0 is depicted Figure A 9 SPI Slave Timing CPHA 0 1 2 1 4 fSCK fbus fbus MHz 10 20 30 40 15 25 35 5 SCK Input SCK Input MOSI Input MISO Output SS Input 1 9 5 6 MSB IN Bit MSB 1 1 LSB IN Slave MSB Slave LSB OUT Bit MSB 1 1 11 4 4 2 7 CPOL 0 CPOL 1 3 13 NOTE Not defined 12 12 11 See 13 Note 8 10 See Note ...

Page 697: ... time tlag 4 tbus 4 D Clock SCK high or low time twsck 4 tbus 5 D Data setup time inputs tsu 8 ns 6 D Data hold time inputs thi 8 ns 7 D Slave access time time to data active ta 20 ns 8 D Slave MISO disable time tdis 22 ns 9 D Data valid after SCK edge tvsck 29 0 5 tbus 1 1 0 5 tbus added due to internal synchronization delay ns 10 D Data valid after SS fall tvss 29 0 5 tbus 1 ns 11 D Data hold ti...

Page 698: ...Package Information S12XS Family Reference Manual Rev 1 13 698 Freescale Semiconductor Appendix B Package Information This section provides the physical dimensions of the S12XS family packages ...

Page 699: ...Package Information S12XS Family Reference Manual Rev 1 13 Freescale Semiconductor 699 B 1 112 pin LQFP Mechanical Dimensions Figure B 1 112 pin LQFP case no 987 page 1 ...

Page 700: ...Package Information S12XS Family Reference Manual Rev 1 13 700 Freescale Semiconductor Figure B 2 112 pin LQFP case no 987 page 2 ...

Page 701: ...Package Information S12XS Family Reference Manual Rev 1 13 Freescale Semiconductor 701 Figure B 3 112 pin LQFP case no 987 page 3 ...

Page 702: ...Package Information S12XS Family Reference Manual Rev 1 13 702 Freescale Semiconductor B 2 80 Pin QFP Mechanical Dimensions Figure B 4 80 pin QFP case no 841B page 1 ...

Page 703: ...Package Information S12XS Family Reference Manual Rev 1 13 Freescale Semiconductor 703 Figure B 5 80 pin QFP case no 841B page 2 ...

Page 704: ...Package Information S12XS Family Reference Manual Rev 1 13 704 Freescale Semiconductor Figure B 6 80 pin QFP case no 841B page 3 ...

Page 705: ...Package Information S12XS Family Reference Manual Rev 1 13 Freescale Semiconductor 705 B 3 64 Pin LQFP Mechanical Dimensions ...

Page 706: ...Package Information S12XS Family Reference Manual Rev 1 13 706 Freescale Semiconductor Figure B 7 64 pin LQFP case no 840F page 2 ...

Page 707: ...Package Information S12XS Family Reference Manual Rev 1 13 Freescale Semiconductor 707 Figure B 8 64 pin LQFP case no 840F page 3 ...

Page 708: ...AL as short as possible and occupied board area for C7 C8 and Q1 as small as possible Do not place other signals or supplies underneath area occupied by C7 C8 and Q1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins Example layouts are illustrated on the following pages Table C 1 Recommended Decoupling Capacitor Choice Component Purpose Type Value C1 VDD...

Page 709: ...ayout Guidelines S12XS Family Reference Manual Rev 1 13 Freescale Semiconductor 709 C 1 1 112 Pin LQFP Recommended PCB Layout Figure C 1 112 Pin LQFP Recommended PCB Layout Loop Controlled Pierce Oscillator ...

Page 710: ... Layout Guidelines S12XS Family Reference Manual Rev 1 13 710 Freescale Semiconductor C 1 2 80 Pin QFP Recommended PCB Layout Figure C 2 80 Pin QFP Recommended PCB Layout Loop Controlled Pierce Oscillator ...

Page 711: ...yout Guidelines S12XS Family Reference Manual Rev 1 13 Freescale Semiconductor 711 C 1 3 64 Pin LQFP Recommended PCB Layout Figure C 3 64 Pin LQFP Recommended PCB Layout Loop Controlled Pierce Oscillator TBD ...

Page 712: ... Memory Options of S12XS family Device Package Flash RAM Data Flash 9S12XS256 112 LQFP 256K 12K 8K 80 QFP 64 LQFP 9S12XS128 112 LQFP 128K 8K 8K 80 QFP 64 LQFP 9S12XS64 112 LQFP 64K 4K 4K 80 QFP 64 LQFP Table D 2 Peripheral Options of S12XS family Members Device Package CAN SCI SPI TIM PIT A D PWM 9S12XS256 112 LQFP 1 2 1 8ch 4ch 16ch 8ch 80 QFP 1 2 1 8ch 4ch 8ch 8ch 64 LQFP 1 2 1 8ch 4ch 8ch 8ch 9...

Page 713: ...W 0x0003 DDRB R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W 0x0004 Reserved R 0 0 0 0 0 0 0 0 W 0x0005 Reserved R 0 0 0 0 0 0 0 0 W 0x0006 Reserved R 0 0 0 0 0 0 0 0 W 0x0007 Reserved R 0 0 0 0 0 0 0 0 W 0x0008 PORTE R PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 W 0x0009 DDRE R DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 W 0x000A 0x000B Module Mapping Control S12XMMC Map 1 of 2 Address Name Bit 7 Bit 6 Bit ...

Page 714: ...0 0 0 0 0 0 0 0 W 0x0013 MMCCTL1 R MGRAMO N 0 DFIFRON PGMIFRO N 0 0 0 0 W 0x0014 Reserved R 0 0 0 0 0 0 0 0 W 0x0015 PPAGE R PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 W 0x0016 RPAGE R RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0 W 0x0017 EPAGE R EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 W 0x0018 0x001B Miscellaneous Peripheral Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0018 Reserved R 0 0 0 0 0 0 0 0 W...

Page 715: ... Bit 9 Bit 8 W 0x0025 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0026 DBGCNT R 0 CNT W 0x0027 DBGSCRX R 0 0 0 0 SC3 SC2 SC1 SC0 W 0x0027 DBGMFR R 0 0 0 0 MC3 MC2 MC1 MC0 W 0x00281 DBGXCTL COMPA C R 0 NDB TAG BRK RW RWE reserved COMPE W 0x00282 DBGXCTL COMPB D R SZE SZ TAG BRK RW RWE reserved COMPE W 0x0029 DBGXAH R 0 Bit 22 21 20 19 18 17 Bit 16 W 0x002A DBGXAM R Bit 15 14 13 12 ...

Page 716: ...d Reset Generator CRG Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0034 SYNR R VCOFRQ 1 0 SYNDIV 5 0 W 0x0035 REFDV R REFFRQ 1 0 REFDIV 5 0 W 0x0036 POSTDIV R 0 0 0 POSTDIV 4 0 W 0x0037 CRGFLG R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM W 0x0038 CRGINT R RTIE 0 0 LOCKIE 0 0 SCMIE 0 W 0x0039 CLKSEL R PLLSEL PSTP XCLKS 0 PLLWAI 0 RTIWAI COPWAI W 0x003A PLLCTL R CME PLLON FM1 FM...

Page 717: ... OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W 0x0049 TCTL2 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W 0x004A TCTL3 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W 0x004B TCTL4 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W 0x004C TIE R C7I C6I C5I C4I C3I C2I C1I C0I W 0x004D TSCR2 R TOI 0 0 0 TCRE PR2 PR1 PR0 W 0x004E TFLG1 R C7F C6F C5F C4F C3F C2F C1F C0F W 0x004F TFLG2 R TOF 0 0 0 0 0 0 0 W 0x0050 TC0H...

Page 718: ...Bit 11 Bit 10 Bit 9 Bit 8 W 0x005F TC7L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0060 PACTL R 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI W 0x0061 PAFLG R 0 0 0 0 0 0 PAOVF PAIF W 0x0062 PACNTH R PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 W 0x0063 PACNTL R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W 0x0064 0x006B Reserved R 0 0 0 0 0 0 0 0 W 0x006C OCPD R O...

Page 719: ...MAP 0 0 TXPOL RXPOL BRK13 TXDIR RAF W 0x00CE SCI0DRH R R8 T8 0 0 0 0 0 0 W 0x00CF SCI0DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 1 Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero 2 Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one 0x00D0 0x00D7 Asynchronous Serial Interface SCI1 Map Address Name Bit 7 Bit 6 Bit 5...

Page 720: ... SPPR0 0 SPR2 SPR1 SPR0 W 0x00DB SPI0SR R SPIF 0 SPTEF MODF 0 0 0 0 W 0x00DC SPI0DRH R R15 R14 R13 R12 R11 R10 R9 R8 W T15 T14 T13 T12 T11 T10 T9 T8 0x00DD SPI0DRL R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0x00DE Reserved R 0 0 0 0 0 0 0 0 W 0x00DF Reserved R 0 0 0 0 0 0 0 0 W 0x00E0 0x00FF Reserved Register Space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00E0 0x00FF...

Page 721: ...0x010B FCCOBLO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x010C Reserved R 0 0 0 0 0 0 0 0 W 0x010D Reserved R 0 0 0 0 0 0 0 0 W 0x010E FECCRHI R ECCR15 ECCR14 ECCR13 ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x010F FECCRLO R ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0 W 0x0110 FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x0111 Reserved R 0 0 0 0 0 0 0 0 W 0x0112 Reserved R 0 0 0 0 0 0 0 0 W 0...

Page 722: ...0 0 0 0 PRIOLVL 2 0 W 0x0129 INT_CFDATA1 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012A INT_CFDATA2 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012B INT_CFDATA3 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012C INT_CFDATA4 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012D INT_CFDATA5 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012E INT_CFDATA6 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012F INT_CFDATA7 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x00130 0x013F Reserved Register Space Add...

Page 723: ...IDHIT1 IDHIT0 W 0x014C Reserved R 0 0 0 0 0 0 0 0 W 0x014D CAN0MISC R 0 0 0 0 0 0 0 BOHOLD W 0x014E CAN0RXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W 0x014F CAN0TXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0150 0x0153 CAN0IDAR0 CAN0IDAR3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x0154 0x0157 CAN0IDMR0 CAN0IDMR3 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0158 0x015B...

Page 724: ...DB4 DB3 DB2 DB1 DB0 W 0xXXXC CANRxDLR R DLC3 DLC2 DLC1 DLC0 W 0xXXXD Reserved R W 0xXXXE CANxRTSRH R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 W 0xXXXF CANxRTSRL R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 W 0xXX10 Extended ID R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 CANxTIDR0 W Standard ID R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W 0xXX0x XX10 Extended ID R ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 ...

Page 725: ... 0 0x0240 PTT R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W 0x0241 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W 0x0242 DDRT R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x0243 RDRT R RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 W 0x0244 PERT R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W 0x0245 PPST R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W 0x0246 Reserved R 0 0 ...

Page 726: ...RM2 DDRM1 DDRM0 W 0x0253 RDRM R RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 W 0x0254 PERM R PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 W 0x0255 PPSM R PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 W 0x0256 WOMM R WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 W 0x0257 MODRR R MODRR7 MODRR6 0 MODRR4 0 0 0 0 W 0x0258 PTP R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W 0x0259 PTIP R PTIP7 PTI...

Page 727: ...RJ0 W 0x026B RDRJ R RDRJ7 RDRJ6 0 0 0 0 RDRJ1 RDRJ0 W 0x026C PERJ R PERJ7 PERJ6 0 0 0 0 PERJ1 PERJ0 W 0x026D PPSJ R PPSJ7 PPSJ6 0 0 0 0 PPSJ1 PPSJ0 W 0x026E PIEJ R PIEJ7 PIEJ6 0 0 0 0 PIEJ1 PIEJ0 W 0x026f PIFJ R PIFJ7 PIFJ6 0 0 0 0 PIFJ1 PIFJ0 W 0x0270 PT0AD0 R PT0AD0 7 PT0AD0 6 PT0AD0 5 PT0AD0 4 PT0AD0 3 PT0AD0 2 PT0AD0 1 PT0AD0 0 W 0x0271 PT1AD0 R PT1AD0 7 PT1AD0 6 PT1AD0 5 PT1AD0 4 PT1AD0 3 PT1...

Page 728: ...CH1 ETRIG CH0 W 0x02C2 ATD0CTL2 R 0 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE W 0x02C3 ATD0CTL3 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 W 0x02C4 ATD0CTL4 R SMP2 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 W 0x02C5 ATD0CTL5 R 0 SC SCAN MULT CD CC CB CA W 0x02C6 ATD0STAT0 R SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0 W 0x02C7 Reserved R 0 0 0 0 0 0 0 0 W 0x02C8 ATD0CMPEH R CMPE15 CMPE14 CMPE13 CMPE12 CMPE11 CMPE10 ...

Page 729: ... Bit15 14 13 12 11 10 9 Bit8 W 0x02D9 ATD0DR4L R Bit7 Bit6 0 0 0 0 0 0 W 0x02DA ATD0DR5H R Bit15 14 13 12 11 10 9 Bit8 W 0x02DB ATD0DR5L R Bit7 Bit6 0 0 0 0 0 0 W 0x02DC ATD0DR6H R Bit15 14 13 12 11 10 9 Bit8 W 0x02DD ATD0DR6L R Bit7 Bit6 0 0 0 0 0 0 W 0x02DE ATD0DR7H R Bit15 14 13 12 11 10 9 Bit8 W 0x02DF ATD0DR7L R Bit7 Bit6 0 0 0 0 0 0 W 0x02E0 ATD0DR8H R Bit15 14 13 12 11 10 9 Bit8 W 0x02E1 AT...

Page 730: ...V3 Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x02F0 VREGHTCL R 0 0 VSEL VAE HTEN HTDS HTIE HTIF W 0x02F1 VREGCTRL R 0 0 0 0 0 LVDS LVIE LVIF W 0x02F2 VREGAPICL R APICLK 0 0 APIFES APIEA APIFE APIE APIF W 0x02F3 VREGAPITR R APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 0 0 W 0x02F4 VREGAPIRH R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x02F5 VREGAPIRL R APIR7 APIR6 ...

Page 731: ... R 0 0 0 0 0 0 0 0 W 0x0307 PWMPRSC R 0 0 0 0 0 0 0 0 W 0x0308 PWMSCLA R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0309 PWMSCLB R Bit 7 6 5 4 3 2 1 Bit 0 W 0x030A PWMSCNTA R 0 0 0 0 0 0 0 0 W 0x030B PWMSCNTB R 0 0 0 0 0 0 0 0 W 0x030C PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x030D PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x030E PWMCNT2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x030F PW...

Page 732: ...x031F PWMDTY3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0320 PWMDTY4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0321 PWMDTY5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0322 PWMDTY6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0323 PWMDTY7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0324 PWMSDN R PWMIF PWMIE 0 PWMLVL 0 PWM7IN PWM7INL PWM7 ENA W PWM RSTRT 0x0325 Reserved R 0 0 0 0 0 0 0 0 W 0x0326 Reserved R 0 0 0 0 0 0 0 0 W 0x0327 Reserved R 0 0 0 0 0 0 0 0 W 0x0...

Page 733: ... PLD12 PLD11 PLD10 PLD9 PLD8 W 0x0349 PITLD0 lo R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x034A PITCNT0 hi R PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x034B PITCNT0 lo R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x034C PITLD1 hi R PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 W 0x034D PITLD1 lo R PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 W 0x034E PITCNT1 hi R PCNT15 PCNT14 ...

Page 734: ...CNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 W 0x0357 PITCNT3 lo R PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 W 0x0358 0x0367 Reserved R 0 0 0 0 0 0 0 0 W 0x0368 0x077F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0368 Reserved R 0 0 0 0 0 0 0 0 W Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ...

Page 735: ...he part number is 15 characters Due to this limitation in some situations some characters are omitted The mask identifier suffix and the Tape Reel suffix are often both omitted from the part number which is actually marked on the device For specific part numbers to order please contact your local sales office The below figure illustrates the structure of a typical mask specific ordering number for...

Page 736: ...Ordering Information S12XS Family Reference Manual Rev 1 13 736 Freescale Semiconductor ...

Page 737: ......

Page 738: ...s without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or ...

Page 739: ...256J0VAA NXP S9S12XS256J0CAL S9S12XS128J1CAA S9S12XS128J1CAL S9S12XS128J1CALR S9S12XS128J1MAA S9S12XS128J1MAE S9S12XS128J1MAL S9S12XS64J1CAE MC9S12XS128CAE MC9S12XS128MAA MC9S12XS128MAE MC9S12XS128MAL MC9S12XS64CAE MC9S12XS64MAE S9S12XS256J0VAE S9S12XS256J0CAE S9S12XS256J0CAA MC9S12XS128MAER S9S12XS128J1CAE S9S12XS64J1MAE S9S12XS128J1VAE S9S12XS64J1VAE S9S12XS128J1CAAR S9S12XS128J1MAAR S9S12XS128J...

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