
NTAK79 2.0 Mb PRI card
Page 753 of 906
Circuit Card
Description and Installation
The incoming serial bit stream is converted to 8-bit parallel bytes to be
directed to padding control.
The signaling bits are extracted and inserted by the A07 signaling interface
circuitry. The DS-30X timeslot number is mapped to the PCM-30 channel
number. Timeslots 0 and 16 are currently unused for PCM.
Digital PAD
Software selects A-Law or Mu-Law and one of 32 possible PAD values for
each channel. These values are provided in a PROM through which the data
is routed. The idle code for A-Law is 54H and for Mu-Law is 7FH. The
unequipped code is FFH for both A-Law and Mu-Law. As the idle code and
unequipped code can be country dependent, the software instructs the
NTAK79 to use different codes for each direction. The 32 digital pads
available are listed in Table 244. The values shown are attenuation levels;
1.0 dB is 1 dB of loss and –1.0 dB is 1 dB of gain.
Table 244
Digital pad values and offset allocations (Part 1 of 2)
PAD SET 0
PAD SET 1
Offset
PAD
Offset
PAD
0
0.6 dB
0
0.0 dB
1
1.0 dB
1
–1.0 dB
2
2.0 dB
2
–2.0 dB
3
3.0 dB
3
–3.0 dB
4
4.0 dB
4
–4.0 dB
5
5.0 dB
5
–5.0 dB
6
6.1 dB
6
–6.0 dB
7
7.0 dB
7
–7.0 dB
8
8.0 dB
8
–8.0 dB
9
9.0 dB
9
–9.0 dB
Summary of Contents for Circuit Card
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Page 4: ...Page 4 of 906 Revision history 553 3001 211 Standard 3 00 August 2005...
Page 18: ...Page 18 of 906 Contents 553 3001 211 Standard 3 00 August 2005...
Page 78: ...Page 78 of 906 Overview 553 3001 211 Standard 3 00 August 2005...
Page 100: ...Page 100 of 906 Acceptance tests 553 3001 211 Standard 3 00 August 2005...
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