
User’s Manual U13850EJ6V0UD
96
CHAPTER 3 CPU FUNCTIONS
The CPU of the V850/SB1 and V850/SB2 is based on RISC architecture and executes most instructions in one
clock cycle by using a 5-stage pipeline.
3.1 Features
•
Minimum instruction execution time V850/SB1 (A version, B version): 50 ns (@20 MHz internal operation)
V850/SB2 (A version, B version): 79 ns (@12.58 MHz internal operation)
V850/SB2 (H version): 53 ns (@18.87 MHz internal operation)
•
Address space: 16 MB linear
•
Thirty-two 32-bit general-purpose registers
•
Internal 32-bit architecture
•
Five-stage pipeline control
•
Multiplication/division instructions
•
Saturated operation instructions
•
One-clock 32-bit shift instruction
•
Load/store instruction with long/short format
•
Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1