
CHAPTER 3 CPU FUNCTIONS
User’s Manual U13850EJ6V0UD
127
(1) Command register (PRCMD)
The command register (PRCMD) is a register used when write-accessing the specific register to prevent incorrect
writing to the specific registers due to the erroneous program execution.
This register can be written in 8-bit units. It becomes undefined values in a read cycle.
Occurrence of illegal store operations can be checked by the PRERR bit of the SYS register.
After reset: Undefined W
Address: FFFFF170H
Symbol
7
6
5
4
3
2
1
0
PRCMD
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
REGn
Registration code
0/1
Any 8-bit data
Remark
n = 0 to 7
(2) System status register (SYS)
This register is allocated with status flags showing the operating state of the entire system. This register can be
read/written in 8-bit or 1-bit units.
After reset: 00H
R/W
Address: FFFFF078H
Symbol
7
6
5
<4>
3
2
1
0
SYS
0
0
0
PRERR
0
0
0
0
PRERR
Detection of protection error
0
Protection error does not occur
1
Protection error occurs
Operation conditions of PRERR flag are shown as follows.
(a) Set conditions (PRERR = 1)
(1)
When a write operation to the specific register took place in a state where the store instruction operation
for the recent peripheral I/O was not a write operation to the PRCMD register.
(2)
When the first store instruction operation following a write operation to the PRCMD register is to any
peripheral I/O register apart from specific registers.
(b) Reset conditions: (PRERR = 0)
(1)
When 0 is written to the PRERR flag of the SYS register. However, except for the case of
Remark 1
.
(2)
At system reset.
Remarks 1.
If 0 is written to the PRERR bit immediately after a write operation to the PRCMD register, the
PRERR bit is set to 1 (because the SYS register is not a specific register).
2.
If the PRCMD register is written again immediately after a write operation to the PRCMD register,
the PRERR bit of the SYS register is set to 1 (because the SYS register is not a specific register).