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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION

User’s Manual U13850EJ6V0UD

154

5.2.5 Edge detection function of NMI pin

The NMI pin valid edge can be selected from the following four types: falling edge, rising edge, both edges, or

neither edge.

Rising edge specification register 0 (EGP0) and falling edge specification register 0 (EGN0) specify the valid edge

of the non-maskable interrupt (NMI). These two registers can be read/written in 1-bit or 8-bit units.

After reset, the valid edge of the NMI pin is set to the “detect neither rising nor falling edge” state. Therefore, the

NMI pin functions as a normal port and an interrupt request cannot be acknowledged, unless a valid edge is specified

by using the EGP0 and EGN0 registers.

When using P00 as an output port, set the NMI valid edge to “detect neither rising nor falling edge”.

(1) Rising edge specification register 0 (EGP0)

After reset: 00H

R/W

Address: FFFFF0C0H

Symbol

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

EGP0

EGP07

EGP06

EGP05

EGP04

EGP03

EGP02

EGP01

EGP00

EGP0n

Rising edge valid control

No interrupt request signal occurred at the rising edge

Interrupt request signal occurred at the rising edge

n = 0: NMI pin control

n = 1 to 7: INTP0 to INTP6 pin control

(2) Falling edge specification register 0 (EGN0)

After reset: 00H

R/W

Address: FFFFF0C2H

Symbol

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

EGN0

EGN07

EGN06

EGN05

EGN04

EGN03

EGN02

EGN01

EGN00

EGN0n

Falling edge valid control

No interrupt request signal occurred at the falling edge

Interrupt request signal occurred at the falling edge

n = 0: NMI pin control

n = 1 to 7: INTP0 to INTP6 pin control

Summary of Contents for V850/SB1

Page 1: ...3036H µ µ µ µPD703033AY µ µ µ µPD703032BY µ µ µ µPD703037AY µ µ µ µPD703036HY µ µ µ µPD70F3032A µ µ µ µPD703033B µ µ µ µPD70F3035A µ µ µ µPD703037H µ µ µ µPD70F3032AY µ µ µ µPD703033BY µ µ µ µPD70F3035AY µ µ µ µPD703037HY µ µ µ µPD70F3033A µ µ µ µPD70F3030B µ µ µ µPD70F3037A µ µ µ µPD70F3035B µ µ µ µPD70F3033AY µ µ µ µPD70F3030BY µ µ µ µPD70F3037AY µ µ µ µPD70F3035BY µ µ µ µPD70F3032B µ µ µ µPD70F...

Page 2: ...User s Manual U13850EJ6V0UD 2 MEMO ...

Page 3: ...e differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS...

Page 4: ...afety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC El...

Page 5: ...1 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 Fax 6250 3583 J02 11 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en España Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Vélizy Villacoublay France Tel 01 30 67 58 00 Fax...

Page 6: ...tion of registers in 3 4 8 Peripheral I O registers p 126 Addition of description in 3 4 9 Specific registers p 126 Modification of Description example in 3 4 9 Specific registers p 126 Modification of Caution 2 in 3 4 9 Specific registers p 127 Addition of Remarks in 3 4 9 2 b Reset conditions PRERR 1 p 129 Addition of Note and Caution in 4 2 2 1 System control register SYC p 158 Addition of Rema...

Page 7: ... output with external trigger p 234 Addition of 7 3 1 Outline p 242 Change of Figure 7 32 Timing of Interval Timer Operation 3 3 p 246 Addition of description to Remarks in Figure 7 34 Square Wave Output Operation Timing p 248 Addition of description to Remarks in Figure 7 35 Timing of PWM Output p 253 Addition of registers and Caution in Figure 8 1 Block Diagram of Watch Timer p 254 Addition of r...

Page 8: ... 517 Addition of description in Figure 16 1 Regulator p 524 Addition of 18 1 1 2 V850 SB1 µ µ µ µPD70F3030B 70F3030BY V850 SB2 µ µ µ µPD70F3036H 70F3036HY p 526 Addition of Figure 18 1 Wiring Example of V850 SB1 and V850 SB2 Flash Writing Adapter FA 100GC 8EU p 527 Addition of Table 18 1 Table for Wiring of V850 SB1 and V850 SB2 Flash Writing Adapter FA 100GC 8EU p 528 Addition of Figure 18 2 Wiri...

Page 9: ...at and instruction set Interrupt and exception Pipeline operation How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering logic circuits and microcontrollers To find out the details of a register whose name is known Refer to APPENDIX B REGISTER INDEX To find out the details of a function etc whose name is known Refer to APP...

Page 10: ...igher addresses at the top and lower addresses at the bottom Note Footnote for items marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Number representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Prefixes indicating power of 2 address space memory capacity K kilo 2 10 1024 M mega 2 20 1024 2 G giga 2 30 1024 3 ...

Page 11: ...r U15026E CA850 Ver 2 40 or Later C Compiler Package Assembly Language U15027E ID850 Ver 2 40 Integrated Debugger Operation Windows Based U15181E SM850 Ver 2 40 System Simulator Operation Windows Based U15182E SM850 Ver 2 00 or Later System Simulator External Part User Open Interface Specifications U14873E Basic U13430E Installation U13410E RX850 Ver 3 13 or Later Real time OS Technical U13431E Ba...

Page 12: ...lds V850 SB2 A versions 54 1 4 3 Ordering information V850 SB2 A versions 55 1 4 4 Pin configuration top view V850 SB2 A versions 56 1 4 5 Function blocks V850 SB2 A versions 59 1 5 V850 SB2 B and H Versions 63 1 5 1 Features V850 SB2 B and H versions 63 1 5 2 Application fields V850 SB2 B and H versions 64 1 5 3 Ordering information V850 SB2 B and H versions 65 1 5 4 Pin configuration top view V8...

Page 13: ...ction 132 4 5 2 External wait function 133 4 5 3 Relationship between programmable wait and external wait 133 4 6 Idle State Insertion Function 134 4 7 Bus Hold Function 135 4 7 1 Outline of function 135 4 7 2 Bus hold procedure 136 4 7 3 Operation in power save mode 136 4 8 Bus Timing 137 4 9 Bus Priority 144 4 10 Memory Boundary Operation Conditions 145 4 10 1 Program space 145 4 10 2 Data space...

Page 14: ...d 177 5 8 1 Interrupt request valid timing after EI instruction 178 5 9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer 179 5 10 Key Interrupt Function 180 CHAPTER 6 CLOCK GENERATION FUNCTION 182 6 1 Outline 182 6 2 Configuration 183 6 3 Clock Output Function 183 6 3 1 Control registers 184 6 4 Power Save Functions 188 6 4 1 Outline 188 6 4 2 HALT mode 189 6 4 3 IDLE m...

Page 15: ...50 7 4 6 Cautions 252 CHAPTER 8 WATCH TIMER 253 8 1 Function 253 8 2 Configuration 254 8 3 Watch Timer Control Registers 255 8 4 Operation 258 8 4 1 Operation as watch timer 258 8 4 2 Operation as interval timer 258 8 4 3 Cautions 259 CHAPTER 9 WATCHDOG TIMER 260 9 1 Functions 260 9 2 Configuration 262 9 3 Watchdog Timer Control Register 262 9 4 Operation 265 9 4 1 Operation as watchdog timer 265 ...

Page 16: ... 10 4 6 Interrupt request INTIICn generation timing and wait control 378 10 4 7 Address match detection method 379 10 4 8 Error detection 379 10 4 9 Extension code 379 10 4 10 Arbitration 380 10 4 11 Wakeup function 382 10 4 12 Communication reservation 383 10 4 13 Cautions 388 10 4 14 Communication operations 389 10 4 15 Timing of data communication 392 10 5 Asynchronous Serial Interface UART0 UA...

Page 17: ...69 13 5 Usage 471 13 6 Operation 472 13 7 Cautions 473 CHAPTER 14 PORT FUNCTION 474 14 1 Port Configuration 474 14 2 Port Pin Function 474 14 2 1 Port 0 474 14 2 2 Port 1 479 14 2 3 Port 2 483 14 2 4 Port 3 488 14 2 5 Ports 4 and 5 492 14 2 6 Port 6 495 14 2 7 Ports 7 and 8 498 14 2 8 Port 9 500 14 2 9 Port 10 503 14 2 10 Port 11 507 14 3 Setting When Port Pin Is Used as Alternate Function 511 14 ...

Page 18: ...emory programming mode 538 18 6 3 Selection of communication mode 539 18 6 4 Communication command 539 18 6 5 Resources used 540 CHAPTER 19 IEBus CONTROLLER V850 SB2 541 19 1 IEBus Controller Function 541 19 1 1 Communication protocol of IEBus 541 19 1 2 Determination of bus mastership arbitration 542 19 1 3 Communication mode 542 19 1 4 Communication address 543 19 1 5 Broadcasting communication ...

Page 19: ...92 19 5 4 Slave reception 594 19 5 5 Interval of occurrence of interrupt for IEBus control 596 CHAPTER 20 ELECTRICAL SPECIFICATIONS 600 CHAPTER 21 PACKAGE DRAWINGS 635 CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS 637 APPENDIX A NOTES ON TARGET SYSTEM DESIGN 642 APPENDIX B REGISTER INDEX 644 APPENDIX C INSTRUCTION SET LIST 651 APPENDIX D INDEX 658 APPENDIX E REVISION HISTORY 664 ...

Page 20: ...d to 4 MB 114 3 18 Application of Wrap Around 117 3 19 Recommended Memory Map Flash Memory Version 118 4 1 Byte Access 8 Bits 130 4 2 Halfword Access 16 Bits 130 4 3 Word Access 32 Bits 130 4 4 Memory Block 131 4 5 Wait Control 133 4 6 Example of Inserting Wait States 133 4 7 Bus Hold Procedure 136 4 8 Memory Read 137 4 9 Memory Write 141 4 10 Bus Hold Timing 143 5 1 Non Maskable Interrupt Servici...

Page 21: ...h Both Edges Specified 218 7 14 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers 219 7 15 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with Rising Edge Specified 220 7 16 Control Register Settings for Pulse Width Measurement by Restarting 221 7 17 Timing of Pulse Width Measurement by Restarting with R...

Page 22: ...I O Mode 274 10 5 Block Diagram of I 2 C 276 10 6 Serial Bus Configuration Example Using I 2 C Bus 277 10 7 Pin Configuration Diagram 292 10 8 I 2 C Bus s Serial Data Transfer Timing 292 10 9 Start Condition 293 10 10 Address 293 10 11 Transfer Direction Specification 294 10 12 ACK Signal 295 10 13 Stop Condition 296 10 14 Wait Signal 297 10 15 Arbitration Timing Example 319 10 16 Communication Re...

Page 23: ...rial Interface Mode 408 10 48 BRGCn Setting Asynchronous Serial Interface Mode 409 10 49 BRGMCn0 and BRGMCn1 Settings Asynchronous Serial Interface Mode 410 10 50 Error Tolerance When k 16 Including Sampling Errors 412 10 51 Format of Transmit Receive Data in Asynchronous Serial Interface 413 10 52 Timing of Asynchronous Serial Interface Transmit Completion Interrupt 415 10 53 Timing of Asynchrono...

Page 24: ...ts DMA0 to DMA5 Are Generated Simultaneously 463 12 8 When Interrupt Servicing Occurs Twice During DMA Operation 464 13 1 Block Diagram of RTO 467 13 2 Configuration of Real Time Output Buffer Registers 468 13 3 Example of Operation Timing of RTO When EXTR 0 BYTE 0 472 14 1 Block Diagram of P00 to P07 478 14 2 Block Diagram of P10 to P12 P14 and P15 481 14 3 Block Diagram of P13 482 14 4 Block Dia...

Page 25: ...9 3 Slave Address Field 546 19 4 Control Field 548 19 5 Telegraph Length Field 550 19 6 Data Field 551 19 7 Bit Configuration of Slave Status 555 19 8 Configuration of Lock Address 556 19 9 Bit Format of IEBus 557 19 10 IEBus Controller Block Diagram 558 19 11 Interrupt Generation Timing for 1 3 and 4 567 19 12 Interrupt Generation Timing for 2 and 5 568 19 13 Timing of INTIE2 Interrupt Generation...

Page 26: ...ing Statuses in HALT Mode 190 6 2 Operating Statuses in IDLE Mode 192 6 3 Operating Statuses in Software STOP Mode 194 7 1 Configuration of Timers 0 and 1 202 7 2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 203 7 3 Valid Edge of TIn1 Pin and Capture Trigger of CRn0 203 7 4 TIn0 Pin Valid Edge and CRn1 Capture Trigger 204 7 5 Configuration of Timers 2 to 7 235 8 1 Interval Time of Interval T...

Page 27: ...eration When Real Time Output Buffer Registers Are Manipulated 468 13 3 Operation Mode and Output Trigger of Real Time Output Port 470 14 1 Pin I O Buffer Power Supplies 474 14 2 Port 0 Alternate Function Pins 475 14 3 Port 1 Alternate Function Pins 479 14 4 Port 2 Alternate Function Pins 483 14 5 Port 3 Alternate Function Pins 488 14 6 Alternate Function Pins of Ports 4 and 5 492 14 7 Port 6 Alte...

Page 28: ...cknowledge Signal Output Condition of Control Field 549 19 6 Contents of Telegraph Length Bit 550 19 7 Internal Registers of IEBus Controller 560 19 8 Reset Conditions of Flags in ISR Register 575 19 9 Interrupt Source List 585 19 10 Communication Error Source Processing List 586 22 1 Surface Mounting Type Soldering Conditions 637 C 1 Symbols in Operand Description 651 C 2 Symbols Used for Opcode ...

Page 29: ...g 3 to 5 V I O interface support and ROM correction For V850 SB2 based on the V850 SB1 the peripheral functions of automobile LAN IEBus Inter Equipment Bus are added In addition to high real time response characteristics and 1 clock pitch basic instructions the V850 SB1 and V850 SB2 have multiply saturation operation and bit manipulation instructions realized with a hardware multiplier for digital...

Page 30: ...k ROM µPD70F3032A No Flash memory µPD703032AY Mask ROM µPD70F3032AY Yes Flash memory 512 KB 24 KB 100 pin QFP 14 20 µPD703031B No µPD703031BY Yes Mask ROM 128 KB 8 KB 100 pin QFP 14 20 100 pin LQFP 14 14 µPD703033B Mask ROM µPD70F3033B No Flash memory µPD703033BY Mask ROM µPD70F3033BY Yes Flash memory 256 KB 16 KB 100 pin QFP 14 20 100 pin LQFP 14 14 µPD703030B Mask ROM µPD70F3030B No Flash memory...

Page 31: ... pin LQFP 14 14 µPD703036H Mask ROM µPD70F3036H No Flash memory µPD703036HY Mask ROM µPD70F3036HY Yes Flash memory 384 KB 24 KB 100 pin QFP 14 20 100 pin LQFP 14 14 µPD703037H Mask ROM µPD70F3037H No Flash memory µPD703037HY Mask ROM V850 SB2 µPD70F3037HY Yes Flash memory 512 KB 24 KB 100 pin QFP 14 20 Yes The part numbers of the V850 SB1 and V850 SB2 are described as follows in this manual A vers...

Page 32: ...30BY 703031A 703031AY 703031B 703031BY 703032A 703032AY 703032B 703032BY 703033A 703033AY 703033B 703033BY Mask ROM versions of the V850 SB2 µPD703034A 703034AY 703034B 703034BY 703035A 703035AY 703035B 703035BY 703036H 703036HY 703037A 703037AY 703037H 703037HY Y versions with on chip I 2 C Y versions of the V850 SB1 with on chip I 2 C µPD703030BY 703031AY 703031BY 703032AY 703032BY 703033AY 7030...

Page 33: ...ion function External bus interface 16 bit data bus address data multiplex Address bus separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703031A 703031AY mask ROM 128 KB RAM 12 KB µPD703033A 703033AY mask ROM 256 KB RAM 16 KB µPD703032A 703032AY mask ROM 512 KB RAM 24 KB µPD70F3033A 70F3033AY flash memory 256 KB RAM 16 KB µPD70F3032A 7...

Page 34: ...ls DMA controller Internal RAM on chip peripheral I O 6 channels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3 3 V Key return function 4 to 8 selecting enabled falling edge fixed Clock generator During main clock or subclock operation 5 level CPU clock including sub operations Power saving functions HALT...

Page 35: ...e pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 ...

Page 36: ...2 13 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 P105 RTP5 KR5 A10 P106 RTP6...

Page 37: ...I3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 P105 RTP5 KR5 A10 P106 RTP6 KR6 A11 P71 ANI1 P70 ANI0 AVSS AVREF AVDD P65 A21 P64 A20 P63 A19 P62 A18 P61 A17 P60 A16 P57 AD15 P56 AD14 P55 AD13 P54 AD12 P53 AD11 P...

Page 38: ...ceive data DSTB Data strobe SCK0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold request SO0 to SO4 Serial output IC Internally connected TI00 TI01 TI10 INTP0 to INTP6 Interrupt request from peripherals TI11 TI2 to TI5 Timer input KR0 to KR7 Key return TO0 to TO5 Timer output...

Page 39: ... P96 WAIT P110 UBEN P91 ALU 16 bit timer TM0 TM1 8 bit timer TM2 to TM7 TO0 TO1 DMAC 6 ch Watch timer P80 to P83 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1 Note 3 CSI2 I2 C1 Note 4 SCK2 SCL1 Note 3 SO3 TXD1 SI3 RXD1 CSI3 UART1 SCK3 ASCK1 Key return KR0 to KR7 ROM correction VPP Note 5 Regulator REGC IC Note 6 3...

Page 40: ...03031AY 128 KB mask ROM µPD703033A 703033AY 256 KB mask ROM µPD70F3033A 70F3033AY 256 KB flash memory µPD703032A 703032AY 512 KB mask ROM µPD70F3032A 70F3032AY 512 KB flash memory ROM can be accessed by the CPU in one clock cycle during instruction fetch d RAM The RAM capacity and mapping addresses vary depending on the product The RAM capacity of each product is shown below µPD703031A 703031AY 12...

Page 41: ... interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 C0 I 2 C1 comprise five channels Two of these channels are switchable between the UART and CSI and another two switchable between CSI and I 2 C For UART0 and UART1 data is transferred via the TXD0 TXD1 RXD0 and RXD1 pins For CSI0 to CSI3 data ...

Page 42: ...ial interface Port 2 8 bit I O Serial interface timer I O Port 3 8 bit I O Timer I O external address bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O External address bus Port 7 8 bit input A D converter analog input Port 8 4 bit input Port 9 7 bit I O External bus interface control signal I O Port 10 8 bit I O Real time output port external addres...

Page 43: ...multiplex Address bus separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703031B 703031BY mask ROM 128 KB RAM 8 KB µPD703033B 703033BY mask ROM 256 KB RAM 16 KB µPD703030B 703030BY mask ROM 384 KB RAM 24 KB µPD703032B 703032BY mask ROM 512 KB RAM 24 KB µPD70F3033B 70F3033BY flash memory 256 KB RAM 16 KB µPD70F3030B 70F3030BY flash memor...

Page 44: ... 12 channels DMA controller Internal RAM on chip peripheral I O 6 channels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3 3 V Key return function 4 to 8 selecting enabled falling edge fixed Clock generator During main clock or subclock operation 5 level CPU clock including sub operations Power saving func...

Page 45: ...LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pi...

Page 46: ...7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 P105 RTP5 KR5 ...

Page 47: ...2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 P105 RTP5 KR5 A10 P106 RTP6 KR6 A11 P71 ANI1 P70 ANI0 AVSS AVREF AVDD P65 A21 P64 A20 P63 A19 P62 A18 P61 A17 P60 A16 P57 AD15 P56 AD14 P55 AD13 P54 AD1...

Page 48: ...ceive data DSTB Data strobe SCK0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold request SO0 to SO4 Serial output IC Internally connected TI00 TI01 TI10 INTP0 to INTP6 Interrupt request from peripherals TI11 TI2 to TI5 Timer input KR0 to KR7 Key return TO0 to TO5 Timer output...

Page 49: ...atch timer P80 to P83 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1 Note 3 CSI2 I2 C1 Note 4 SCK2 SCL1 Note 3 SO3 TXD1 SI3 RXD1 CSI3 UART1 SCK3 ASCK1 Key return KR0 to KR7 ROM correction VPP Note 5 Regulator REGC IC Note 6 3 3 V Notes 1 µPD703031B 703031BY 128 KB mask ROM µPD703033B 703033BY 256 KB mask ROM µPD703...

Page 50: ...oduct The ROM capacity of each product is shown below µPD703031B 703031BY 128 KB mask ROM µPD703033B 703033BY 256 KB mask ROM µPD70F3033B 70F3033BY 256 KB flash memory µPD703030B 703030BY 384 KB mask ROM µPD70F3030B 70F3030BY 384 KB flash memory µPD703032B 703032BY 512 KB mask ROM µPD70F3032B 70F3032BY 512 KB flash memory ROM can be accessed by the CPU in one clock cycle during instruction fetch d...

Page 51: ...request INTWDT after an overflow occurs When used as an interval timer it generates a maskable interrupt request INTWDTM after an overflow occurs j Serial interface SIO The V850 SB1 includes three kinds of serial interfaces asynchronous serial interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 ...

Page 52: ...I O Port Function Control Function Port 0 8 bit I O NMI external interrupt A D converter trigger RTP trigger Port 1 6 bit I O Serial interface Port 2 8 bit I O Serial interface timer I O Port 3 8 bit I O Timer I O external address bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O External address bus Port 7 8 bit input A D converter analog input Port...

Page 53: ...t data bus address data multiplex Address bus separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703034A 703034AY mask ROM 128 KB RAM 12 KB µPD703035A 703035AY mask ROM 256 KB RAM 16 KB µPD703037A 703037AY mask ROM 512 KB RAM 24 KB µPD70F3035A 70F3035AY flash memory 256 KB RAM 16 KB µPD70F3037A 70F3037AY flash memory 512 KB RAM 24 KB In...

Page 54: ... 6 channels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3 0 V Key return function 4 to 8 selecting enabled falling edge fixed Clock generator During main clock or subclock operation 5 level CPU clock including sub operations Power saving functions HALT IDLE STOP modes IEBus controller 1 ch Package 100 pi...

Page 55: ...B µPD703035AYGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 Mask ROM 256 KB µPD703035AYGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 256 KB µPD703037AGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 512 KB µPD703037AYGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 512 KB µPD70F3035AGC 8EU 100 pin plastic LQFP fine pitch 14 14 Flash memory 256 KB µPD70F3035AGF 3BA 100 pin plastic QFP 14 20 Flash memor...

Page 56: ...14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 IERX P105 RTP5 KR5 A10 IETX P106...

Page 57: ...4 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 IERX P105 RTP5 KR5 A10 IETX P106 RTP6 KR6 A11 P71 ANI1 P70 ANI0 AVSS AVREF AVDD P65 A21 P64 A20 P63 A19 P62 A18 P61 A17 P60 A16 P57 AD15 P56 AD14 P55 AD13 P54 AD12 P53 A...

Page 58: ...K0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold request SO0 to SO4 Serial output IC Internally connected TI00 TI01 TI10 IERX IEBus receive data TI11 TI2 to TI5 Timer input IETX IEBus transmit data TO0 to TO5 Timer output INTP0 to INTP6 Interrupt request from peripherals TX...

Page 59: ...91 ALU 16 bit timer TM0 TM1 8 bit timer TM2 to TM7 TO0 TO1 DMAC 6 ch Watch timer P80 to P83 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1Note 3 CSI2 I2 C1 Note 4 SCK2 SCL1Note 3 SO3 TXD1 SI3 RXD1 CSI3 UART1 SCK3 ASCK1 Key return KR0 to KR7 ROM correction VPP Note 6 Regulator REGC ICNote 6 3 0 V IEBus IETX IERX Not...

Page 60: ...03034AY 128 KB mask ROM µPD703035A 703035AY 256 KB mask ROM µPD70F3035A 70F3035AY 256 KB flash memory µPD703037A 703037AY 512 KB mask ROM µPD70F3037A 70F3037AY 512 KB flash memory ROM can be accessed by the CPU in one clock cycle during instruction fetch d RAM The RAM capacity and mapping addresses vary depending on the product The RAM capacity of each product is shown below µPD703034A 703034AY 12...

Page 61: ... interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 C0 I 2 C1 comprise five channels Two of these channels are switchable between the UART and CSI and another two switchable between CSI and I 2 C For UART0 and UART1 data is transferred via the TXD0 TXD1 RXD0 and RXD1 pins For CSI0 to CSI3 data ...

Page 62: ...ess bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O External address bus Port 7 8 bit input A D converter analog input Port 8 4 bit input Port 9 7 bit I O External bus interface control signal I O Port 10 8 bit I O Real time output port external address bus key return input IEBus data I O Port 11 4 bit I O General purpose port Wait control external...

Page 63: ...able to 4 MB Memory block allocation function 2 MB per block Programmable wait function Idle state insertion function External bus interface 16 bit data bus address data multiplex Address bus separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory µPD703034B 703034BY mask ROM 128 KB RAM 8 KB µPD703035B 703035BY mask ROM 256 KB RAM 16 KB µPD7030...

Page 64: ...dicated baud rate generator 3 channels A D converter 10 bit resolution 12 channels DMA controller Internal RAM on chip peripheral I O 6 channels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3 0 V Key return function 4 to 8 selecting enabled falling edge fixed Clock generator During main clock or subclock ...

Page 65: ...036HYGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 Mask ROM 384 KB µPD703036HYGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 384 KB µPD703037HGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 512 KB µPD703037HYGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 512 KB µPD70F3035BGC 8EU 100 pin plastic LQFP fine pitch 14 14 Flash memory 256 KB µPD70F3035BGF 3BA 100 pin plastic QFP 14 20 Flash memory 256 KB...

Page 66: ...8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 IERX P105 RTP5 K...

Page 67: ... P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7 P103 RTP3 KR3 A8 P104 RTP4 KR4 A9 IERX P105 RTP5 KR5 A10 IETX P106 RTP6 KR6 A11 P71 ANI1 P70 ANI0 AVSS AVREF AVDD P65 A21 P64 A20 P63 A19 P62 A18 P61 A17 P60 A16 P57 AD15 P56 AD14 P55 AD1...

Page 68: ...strobe SCK0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold request SO0 to SO4 Serial output IC Internally connected TI00 TI01 TI10 IERX IEBus receive data TI11 TI2 to TI5 Timer input IETX IEBus transmit data TO0 to TO5 Timer output INTP0 to INTP6 Interrupt request from perip...

Page 69: ...3 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1Note 3 CSI2 I2 C1 Note 4 SCK2 SCL1Note 3 SO3 TXD1 SI3 RXD1 CSI3 UART1 SCK3 ASCK1 Key return KR0 to KR7 ROM correction VPP Note 6 Regulator REGC ICNote 7 Note 5 IEBus IETX IERX Notes 1 µPD703034B 703034BY 128 K mask ROM µPD703035B 703035BY 256 K mask ROM µPD703036H 703...

Page 70: ...oduct The ROM capacity of each product is shown below µPD703034B 703034BY 128 KB mask ROM µPD703035B 703035BY 256 KB mask ROM µPD70F3035B 70F3035BY 256 KB flash memory µPD703036H 703036HY 384 KB mask ROM µPD70F3036H 70F3036HY 384 KB flash memory µPD703037H 703037HY 512 KB mask ROM µPD70F3037H 70F3037HY 512 KB flash memory ROM can be accessed by the CPU in one clock cycle during instruction fetch d...

Page 71: ...request INTWDT after an overflow occurs When used as an interval timer it generates a maskable interrupt request INTWDTM after an overflow occurs j Serial interface SIO The V850 SB2 includes three kinds of serial interfaces asynchronous serial interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 ...

Page 72: ...RTP trigger Port 1 6 bit I O Serial interface Port 2 8 bit I O Serial interface timer I O Port 3 8 bit I O Timer I O external address bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O External address bus Port 7 8 bit input A D converter analog input Port 8 4 bit input Port 9 7 bit I O External bus interface control signal I O Port 10 8 bit I O Real ...

Page 73: ...hose for 4 0 to 5 5 V Differences in pins between the V850 SB1 and V850 SB2 are shown below Table 2 2 Differences in Pins Between V850 SB1 and V850 SB2 V850 SB1 V850 SB2 Pin µPD703031A µPD703032A µPD703033A µPD703030B µPD703031B µPD703032B µPD703033B µPD70F3032A µPD70F3033A µPD70F3030B µPD70F3032B µPD70F3033B µPD703031AY µPD703032AY µPD703033AY µPD703030BY µPD703031BY µPD703032BY µPD703033BY µPD70...

Page 74: ...rt Input output mode can be specified in 1 bit units INTP6 P10 SI0 SDA0 P11 SO0 P12 SCK0 SCL0 P13 SI1 RXD0 P14 SO1 TXD0 P15 I O Yes Port 1 6 bit I O port Input output mode can be specified in 1 bit units SCK1 ASCK0 P20 SI2 SDA1 P21 SO2 P22 SCK2 SCL1 P23 SI3 RXD1 P24 SO3 TXD1 P25 SCK3 ASCK1 P26 TI2 TO2 P27 I O Yes Port 2 8 bit I O port Input output mode can be specified in 1 bit units TI3 TO3 Remar...

Page 75: ...t units TI5 TO5 P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 I O No Port 4 8 bit I O port Input output mode can be specified in 1 bit units AD7 P50 AD8 P51 AD9 P52 AD10 P53 AD11 P54 AD12 P55 AD13 P56 AD14 P57 I O No Port 5 8 bit I O port Input output mode can be specified in 1 bit units AD15 P60 A16 P61 A17 P62 A18 P63 A19 P64 A20 P65 I O No Port 6 6 bit I O port Input output mode c...

Page 76: ...W WRH P93 DSTB RD P94 ASTB P95 HLDAK P96 I O No Port 9 7 bit I O port Input output mode can be specified in 1 bit units HLDRQ P100 RTP0 A5 KR0 P101 RTP1 A6 KR1 P102 RTP2 A7 KR2 P103 RTP3 A8 KR3 P104 RTP4 A9 KR4 IERX P105 RTP5 A10 KR5 IETX P106 RTP6 A11 KR6 P107 I O Yes Port 10 8 bit I O port Input output mode can be specified in 1 bit units RTP7 A12 KR7 P110 A1 WAIT P111 A2 P112 A3 P113 I O Yes Po...

Page 77: ... strobe signal output P94 AVDD Positive power supply for A D converter and alternate function port AVREF Input Reference voltage input for A D converter AVSS Ground potential for A D converter and alternate function port BVDD Positive power supply for bus interface and alternate function port BVSS Ground potential for bus interface and alternate function port CLKOUT Output Internal system clock ou...

Page 78: ...utput Yes Real time output port P106 A11 KR6 P107 A12 KR7 RTPTRG Input Yes RTP external trigger input P06 INTP5 R W Output No External read write status output P92 WRH RXD0 P13 SI1 RXD1 Input Yes Serial receive data input for UART0 and UART1 P23 SI3 SCK0 P12 SCL0 SCK1 P15 ASCK0 SCK2 P22 SCL1 SCK3 Serial clock I O 3 wire type for CSI0 to CSI3 P25 ASCK1 SCK4 I O Yes Serial clock I O for variable len...

Page 79: ... External count clock input for TM5 P37 TO5 TO0 TO1 Pulse signal output for TM0 TM1 P34 A13 SCK4 P35 A14 TO2 Pulse signal output for TM2 P26 TI2 TO3 Pulse signal output for TM3 P27 TI3 TO4 Pulse signal output for TM4 P36 TI4 A15 TO5 Output Yes Pulse signal output for TM5 P37 TI5 TXD0 P14 SO1 TXD1 Output Yes Serial transmit data output for UART0 and UART1 P24 SO3 UBEN Output No Higher byte enable s...

Page 80: ...atingNote 4 OperatingNote 4 Notes 1 Pins except the CLKOUT pin are used as port pins input mode after reset 2 The bus cycle inactivation timing occurs when the internal memory area is specified by the program counter PC in the external expansion mode 3 When the external memory area has not been accessed even once after reset is released and the external expansion mode is set Undefined When the bus...

Page 81: ... a Port function P00 to P07 can be set to input or output in 1 bit units using the port 0 mode register PM0 b Alternate functions i NMI Non maskable interrupt request input This is a non maskable interrupt request signal input pin ii INTP0 to INTP6 Interrupt request from peripherals input These are external interrupt request input pins iii ADTRG A D trigger input input This is the A D converter s ...

Page 82: ... input pins of CSI0 and CSI1 ii SO0 SO1 Serial output 0 1 output These are the serial transmit data output pins of CSI0 and CSI1 iii SCK0 SCK1 Serial clock 0 1 3 state I O These are the serial clock I O pins for CSI0 and CSI1 iv SDA0 Serial data 0 I O This is the serial transmit receive data I O pin of I 2 C0 Y versions products with on chip I 2 C only v SCL0 Serial clock 0 I O This is the serial ...

Page 83: ...e are the serial transmit data output pins of CSI2 and CSI3 iii SCK2 SCK3 Serial clock 2 3 3 state I O These are the serial clock I O pins of CSI2 and CSI3 iv SDA1 Serial data 1 I O This is the serial transmit receive data I O pin of I 2 C1 Y versions products with on chip I 2 C only v SCL1 Serial clock I O This is the serial clock I O pin of I 2 C1 Y versions products with I 2 C only vi RXD1 Rece...

Page 84: ...ternal count clock input pins of timer 0 timer 1 timer 4 and timer 5 ii TO0 TO1 TO4 TO5 Timer output 0 1 4 5 output These are the pulse signal output pins of timer 0 timer 1 timer 4 and timer 5 iii A13 to A15 Address bus 13 to 15 output These comprise an address bus that is used for external access These pins operate as the A13 to A15 bit address output pins within a 22 bit address The output chan...

Page 85: ...h state within the bus cycle When the timing sets the bus cycle to inactive these pins go into a high impedance state 6 P50 to P57 Port 5 3 state I O P50 to P57 constitute an 8 bit I O port that can be set to input or output in 1 bit units P50 to P57 can also function as I O port pins and as a time division address data buses AD8 to AD15 when memory is expanded externally The I O signal level uses...

Page 86: ...The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle When the timing sets the bus cycle to inactive the previous bus cycle s address is retained 8 P70 to P77 Port 7 P80 to P83 Port 8 input P70 to P77 constitute an 8 bit input only port in which all the pins are fixed to input mode P80 to P83 constitute a 4 bit input only port in which all the pin...

Page 87: ... the bus cycle When the timing sets the bus cycle as inactive the previous bus cycle s address is retained ii UBEN Upper byte enable output This is an upper byte enable signal output pin for the external 16 bit data bus During byte access of even numbered addresses these pins are set as inactive high level The output changes in synchronization with the rising edge of the clock in the T1 state of t...

Page 88: ... input This is an input pin by which an external device requests the V850 SB1 and V850 SB2 to release the address bus data bus and control bus This pin accepts asynchronous input for CLKOUT When this pin is active the address bus data bus and control bus are set to high impedance status This occurs either when the V850 SB1 and V850 SB2 complete execution of the current bus cycle or immediately if ...

Page 89: ...7 output These pins comprise a real time output port ii A5 to A12 Address bus 5 to 12 output These comprise the address bus that is used for external access These pins operate as the A5 to A12 bit address output pins within a 22 bit address The output changes in synchronization with the rising edge of the clock in the T1 state of the bus cycle When the timing sets the bus cycle as inactive the pre...

Page 90: ...2 or TW state of the bus cycle ON OFF switching of the wait function is performed by the port alternate function control register PAC Caution Because the supply voltage to the I O buffer of the WAIT pin is EVDD if the voltage of EVDD and that of BVDD differ use EVDD as the voltage of the external wait signal instead of BVDD 12 RESET Reset input The RESET pin is an asynchronous input and inputs a s...

Page 91: ... O ports and alternate function pins except for the alternate function ports of the bus interface 23 EVSS Ground for port This is the ground pin for I O ports and alternate function pins except for the alternate function ports of the bus interface 24 VDD Power supply This is the positive power supply pin All VDD pins should be connected to a positive power supply 25 VSS Ground This is the ground p...

Page 92: ...1 ASCK0 EVDD 10 A P20 SI2 SDA1 10 A P21 SO2 26 P22 SCK2 SCL1 10 A P23 SI3 RXD1 8 A P24 SO3 TXD1 26 P25 SCK3 ASCK1 10 A P26 P27 TI2 TO2 TI3 TO3 EVDD 8 A P30 P31 TI00 TI01 P32 TI10 SI4 8 A P33 TI11 SO4 P34 TO0 A13 SCK4 10 A P35 TO1 A14 5 A P36 TI4 TO4 A15 P37 TI5 TO5 EVDD 8 A Input Independently connect to EVDD or EVSS via a resistor Output Leave open P40 to P47 AD0 to AD7 P50 to P57 AD8 to AD15 P60...

Page 93: ...RTP0 A5 KR0 to RTP3 A8 KR3 P104 RTP4 A9 KR4 IERX P105 RTP5 A10 KR5 IETX P106 P107 RTP6 A11 KR6 RTP7 A12 KR7 EVDD 10 A P110 A1 WAIT P111 to P113 A2 to A4 EVDD 5 A Input Independently connect to EVDD or EVSS via a resistor Output Leave open AVREF Connect to AVSS via a resistor CLKOUT BVDD 4 Leave open RESET EVDD 2 X1 X2 XT1 16 Connect to VSS via a resistor XT2 16 Leave open VPP Note 1 Connect to VSS...

Page 94: ...hat can be set for high impedance output both P ch and N ch off Type 8 A Type 5 Type 9 Pullup enable Input enable IN OUT Data Output disable N ch P ch P ch VDD VDD IN OUT Output disable N ch Data P ch VDD Pullup enable IN OUT Data Output disable N ch P ch P ch VDD VDD Output disable Input enable IN OUT Data N ch P ch VDD N ch P ch Input enable VREF threshold voltage Comparator ...

Page 95: ...Manual U13850EJ6V0UD 95 2 2 Type 10 A Type 26 Type 16 Pullup enable IN OUT Data Open drain Output disable N ch P ch P ch VDD VDD Pullup enable IN OUT Data Open drain Output disable N ch P ch P ch VDD VDD P ch XT1 XT2 Feedback cut off ...

Page 96: ...0 MHz internal operation V850 SB2 A version B version 79 ns 12 58 MHz internal operation V850 SB2 H version 53 ns 18 87 MHz internal operation Address space 16 MB linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction Load store instruction w...

Page 97: ...Manual Figure 3 1 CPU Register Set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Address Register Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter PSW Program Status Word ECR Exception Cause Register FEPC FEPSW Fatal Error PC Fatal Error PSW EIP...

Page 98: ... Usage Operation r0 Zero register Always holds 0 r1 Assembler reserved register Working register for generating 32 bit immediate r2 Address data variable register when r2 is not used by the real time OS r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text areaNo...

Page 99: ... exception maskable interrupt or NMI occurs this register will contain information referencing the interrupt source The higher 16 bits of this register are called FECC to which exception code of NMI is set The lower 16 bits are called EICC to which exception code of exception interrupt is set 5 PSW Program status word A program status word is a collection of flags that indicate program status inst...

Page 100: ...e acknowledged when this bit is set For details refer to 5 4 3 EP flag ID Maskable interrupt servicing specification 0 Maskable interrupt acknowledgment enabled EI 1 Maskable interrupt acknowledgment disabled DI This flag is set 1 when a maskable interrupt request is acknowledged For details refer to 5 3 6 ID flag SATNote Saturation detection of operation result of saturation operation instruction...

Page 101: ...of a saturation processed operation is determined by the contents of the OV and S bits in the saturation operation Simply setting 1 the OV bit will set 1 the SAT bit in a saturation operation Flag status Status of operation result SAT OV S Saturation processed operation result Maximum positive value exceeded 1 1 0 7FFFFFFFH Maximum negative value exceeded 1 1 1 80000000H Positive not exceeding the...

Page 102: ... of the internal ROM and instruction processing written in the internal ROM is started However external expansion mode that connects external device to external memory area is enabled by setting in the memory expansion mode register MM by instruction 2 Flash memory programming mode This mode is provided only in the flash memory versions The internal flash memory is programmable or erasable when th...

Page 103: ...d support up to 4 GB of linear address space data space during operand addressing data access When referencing instruction addresses linear address space program space of up to 16 MB is supported The CPU address space is shown below Figure 3 2 CPU Address Space FFFFFFFFH CPU address space Program area 16 MB linear Data area 4 GB linear 01000000H 00FFFFFFH 00000000H ...

Page 104: ...ause the higher 8 bits of a 32 bit CPU address are ignored and the CPU address is only seen as a 24 bit external physical address the physical location xx000000H is equally referenced by multiple address values 00000000H 01000000H 02000000H FE000000H FF000000H Figure 3 3 Image on Address Space FFFFFFFFH FF000000H FEFFFFFFH Image CPU address space Image Image Image Image FE000000H FDFFFFFFH 0200000...

Page 105: ...sses Caution No instruction can be fetched from the 4 KB area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I O area Therefore do not execute any branch operation instructions in which the destination address will reside in any part of this area Figure 3 4 Program Space 00FFFFFEH 00FFFFFFH 00000000H 00000001H Program space Program space direction direction 2 Data space The r...

Page 106: ... Map xxFFFFFFH On chip peripheral I O area Internal RAM area Reserved On chip flash memory ROM area On chip peripheral I O area Internal RAM area External memory area On chip flash memory ROM area Single chip mode Single chip mode external expansion mode 16 MB 1 MB 4 KB xxFFF000H xxFFEFFFH xx100000H xx0FFFFFH xx000000H xxFF8000H xxFF7FFFH 28 KB ...

Page 107: ...an access prohibited area Figure 3 7 Internal ROM Area 128 KB xx0FFFFFH xx020000H xx01FFFFH xx000000H Access prohibited area Internal ROM b V850 SB1 µ µ µ µPD703033A 703033AY 70F3033A 70F3033AY 703033B 703033BY 70F3033B 70F3033BY V850 SB2 µ µ µ µPD703035A 703035AY 70F3035A 70F3035AY 703035B 703035BY 70F3035B 70F3035BY 256 KB are available for the addresses xx000000H to xx03FFFFH Addresses xx040000...

Page 108: ... KB xx0FFFFFH xx060000H xx05FFFFH xx000000H Access prohibited area Internal ROM flash memory d V850 SB1 µ µ µ µPD703032A 703032AY 70F3032A 70F3032AY 703032B 703032BY 70F3032B 70F3032BY V850 SB2 µ µ µ µPD703037A 703037AY 70F3037A 70F3037AY 703037H 703037HY 70F3037H 70F3037HY 512 KB are available for the addresses xx000000H to xx07FFFFH Addresses xx080000H to xx0FFFFFH are an access prohibited area ...

Page 109: ...n Source 00000000H RESET 000001D0H INTTM6 00000010H NMI 000001E0H INTTM7 00000020H INTWDT 000001F0H INTIIC0Note INTCSI0 00000040H TRAP0n n 0 to F 00000200H INTSER0 00000050H TRAP1n n 0 to F 00000210H INTSR0 INTCSI1 00000060H ILGOP 00000220H INTST0 00000080H INTWDTM 00000230H INTCSI2 00000090H INTP0 00000240H INTIIC1Note 000000A0H INTP1 00000250H INTSER1 000000B0H INTP2 00000260H INTSR1 INTCSI3 000...

Page 110: ...esses xxFF8000H to xxFFCFFFH are an access prohibited area Figure 3 11 Internal RAM Area 8 KB xxFFEFFFH xxFFD000H xxFFCFFFH xxFF8000H Access prohibited area Internal RAM b V850 SB1 µ µ µ µPD703031A 703031AY V850 SB2 µ µ µ µPD703034A 703034AY 12 KB are available for the addresses xxFFC000H to xxFFEFFFH Addresses xxFF8000H to xxFFBFFFH are an access prohibited area Figure 3 12 Internal RAM Area 12 K...

Page 111: ...ernal RAM Area 16 KB xxFFEFFFH xxFFB000H xxFFAFFFH xxFF8000H Access prohibited area Internal RAM d V850 SB1 µ µ µ µPD703030B 703030BY 70F3030B 70F3030BY 703032A 703032AY 70F3032A 70F3032AY 703032BY 70F3032B 70F3032BY V850 SB2 µ µ µ µPD703036H 703036HY 70F3036H 70F3036HY 703037A 703037AY 70F3037A 70F3037AY 703037H 703037HY 70F3037H 70F3037HY 24 KB are available for the addresses xxFF9000H to xxFFEF...

Page 112: ... the peripheral I O area is referenced accessed in byte units the register at the next lowest even address 2n will be accessed 2 If a register that can be accessed in byte units is accessed in halfword units the higher 8 bits become undefined if the access is a read operation If a write access is made only the data in the lower 8 bits is written to the register 3 If a register with n address that ...

Page 113: ...ated when the external expansion mode is specified In the area of other than the physical external memory the image of the physical external memory can be seen The internal RAM area and on chip peripheral I O area are not subject to external memory access Figure 3 16 External Memory Area When Expanded to 64 K 256 K or 1 MB xxFFFFFFH xx000000H Physical external memory xFFFFH 00000H On chip peripher...

Page 114: ... register MM The address bus A1 to A15 is set to multiplexed output with data bus D1 to D15 though separate output is also available by setting the memory address output mode register MAM see the User s Manual of relevant in circuit emulator about debugging when using the separate bus Caution Because the A1 pin and WAIT pin are alternate function pins the wait function by the WAIT pin cannot be us...

Page 115: ... in 8 bit or 1 bit units However bits 4 to 7 are fixed to 0 After reset 00H R W Address FFFFF04CH Symbol 7 6 5 4 3 2 1 0 MM 0 0 0 0 MM3 MM2 MM1 MM0 MM3 P95 and P96 operation modes 0 Port mode 1 External expansion mode HLDAK P95 HLDRQ P96 MM2 MM1 MM0 Address space Port 4 Port 5 Port 6 Port 9 0 0 0 Port mode 0 1 1 64 KB AD0 to AD8 to LBEN expansion mode AD7 AD15 UBEN 1 0 0 256 KB A16 R W DSTB expans...

Page 116: ... in circuit emulator is not available Also setting the MAM register by software cannot switch to the separate bus For details refer to the relevant User s Manual of in circuit emulator Remark For details of the operation of each port see 2 3 Description of Pin Functions The separate path outputs are output from P34 to P36 P100 to P107 and P110 to P113 The procedure for performing separate path out...

Page 117: ...ts are valid Therefore a continuous 16 MB space starting from address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources to be performed through the wrap around feature of the data space the continuous 8 MB address spaces 00000000H to 007FFFFFH and FF800000H to FFFFFFFFH of the 4 GB CPU are used as the data space With the V8...

Page 118: ...ernal memory Internal ROM xxFFFFFFH xxFFF400H xxFFF3FFH xxFFF000H xxFFEFFFH xxFFB000H xxFFAFFFH xxFF8000H xxFF7FFFH xx100000H xx0FFFFFH xx040000H xx03FFFFH xx800000H xx7FFFFFH xx000000H FFFFF000H FFFFEFFFH FFFF8000H FFFF7FFFH FF800000H FF7FFFFFH 01000000H 00FFFFFFH 00FFF000H 00FFEFFFH 00FF8000H 00FF7FFFH 00800000H 007FFFFFH 00100000H 000FFFFFH 00040000H 0003FFFFH Note This area cannot be used as a...

Page 119: ...r PM6 3FH FFFFF032H Port 9 mode register PM9 7FH FFFFF034H Port 10 mode register PM10 FFH FFFFF036H Port 11 mode register PM11 1FH FFFFF040H Port alternate function control register PAC FFFFF04CH Memory expansion mode register MM 00H FFFFF060H Data wait control register DWC FFFFH FFFFF062H Bus cycle control register BCC AAAAH FFFFF064H System control register SYC R W FFFFF068H Memory address outpu...

Page 120: ...FFFF10EH Interrupt control register PIC6 FFFFF118H Interrupt control register WTNIIC FFFFF11AH Interrupt control register TMIC00 FFFFF11CH Interrupt control register TMIC01 FFFFF11EH Interrupt control register TMIC10 FFFFF120H Interrupt control register TMIC11 FFFFF122H Interrupt control register TMIC2 FFFFF124H Interrupt control register TMIC3 FFFFF126H Interrupt control register TMIC4 FFFFF128H ...

Page 121: ... DRA0 FFFFF184H DMA byte count register 0 DBC0 Undefined FFFFF186H DMA channel control register 0 DCHC0 00H FFFFF190H DMA peripheral I O address register 1 DIOA1 FFFFF192H DMA internal RAM address register 1 DRA1 FFFFF194H DMA byte count register 1 DBC1 Undefined FFFFF196H DMA channel control register 1 DCHC1 00H FFFFF1A0H DMA peripheral I O address register 2 DIOA2 FFFFF1A2H DMA internal RAM addr...

Page 122: ...ister 10 PRM10 FFFFF218H 16 bit timer mode control register 1 TMC1 FFFFF21AH Capture compare control register 1 CRC1 FFFFF21CH Timer output control register 1 TOC1 FFFFF21EH Prescaler mode register 11 PRM11 R W 00H FFFFF240H 8 bit counter 2 TM2 R FFFFF242H 8 bit compare register 2 CR20 FFFFF244H Timer clock selection register 20 TCL20 00H FFFFF246H 8 bit timer mode control register 2 TMC2 R W 04H ...

Page 123: ...de connection only TM67 R FFFFF28CH 16 bit compare register 67 during cascade connection only CR67 0000H FFFFF28EH Timer clock selection register 61 TCL61 R W FFFFF290H 8 bit counter 7 TM7 R FFFFF292H 8 bit compare register 7 CR70 FFFFF294H Timer clock selection register 70 TCL70 00H FFFFF296H 8 bit timer mode control register 7 TMC7 04H FFFFF29EH Timer clock selection register 71 TCL71 FFFFF2A0H ...

Page 124: ...eception buffer register 1 RXB1 R FFH FFFFF31EH Baud rate generator mode control register 10 BRGMC10 FFFFF320H Baud rate generator mode control register 01 BRGMC01 FFFFF322H Baud rate generator mode control register 11 BRGMC11 FFFFF33CH IIC flag register 0Note 1 IICF0 FFFFF33EH IIC flag register 1Note 1 IICF1 FFFFF340H IIC control register 0Note 2 IICC0 R W FFFFF342H IIC state register 0Note 2 IIC...

Page 125: ...annel specification register ADS R W FFFFF3C4H A D conversion result register ADCR 0000H FFFFF3C6H A D conversion result register H higher 8 bits ADCRH R FFFFF3C8H A D converter mode register 2 ADM2 FFFFF3D0H Key return mode register KRM FFFFF3D4H Noise elimination control register NCC FFFFF3DEH IEBus high speed clock selection register V850 SB2 IEHCLKNote2 FFFFF3E0H IEBus control register V850 SB...

Page 126: ...ions 7 If necessary enable DMA operation No special sequence is required when reading the specific registers Cautions 1 If an interrupt request or a DMA request is accepted between the time PRCMD is generated 3 and the specific register write operation 4 that follows immediately after the write operation to the specific register is not performed and a protection error PRERR bit of SYS register is ...

Page 127: ... 0 0 PRERR 0 0 0 0 PRERR Detection of protection error 0 Protection error does not occur 1 Protection error occurs Operation conditions of PRERR flag are shown as follows a Set conditions PRERR 1 1 When a write operation to the specific register took place in a state where the store instruction operation for the recent peripheral I O was not a write operation to the PRCMD register 2 When the first...

Page 128: ...ontrol Pins External Bus Interface Function Corresponding Port Pins Address data bus AD0 to AD7 Port 4 P40 to P47 Address data bus AD8 to AD15 Port 5 P50 to P57 Address bus A1 to A4 Port 11 P110 to P113 Address bus A5 to A12 Port 10 P100 to P107 Address bus A13 to A15 Port 3 P34 to P36 Address bus A16 to A21 Port 6 P60 to P65 Read write control LBEN UBEN R W DSTB WRL WRH RD Port 9 P90 to P93 Addre...

Page 129: ...f the BIC bit setting in the external expansion mode set by the memory expansion mode register MM Caution In the V850 SB1 and V850 SB2 when using port 9 as an I O port set the BIC bit of the system control register SYC to 0 Note that the BIC bit is 0 after system reset 4 3 Bus Access 4 3 1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows Table ...

Page 130: ...te data External data bus a Access to even address 0 7 0 7 8 15 Byte data External data bus b Access to odd address 2 Halfword access 16 bits In halfword access to external memory data is dealt with as is because the data bus is fixed to 16 bits Figure 4 2 Halfword Access 16 Bits 0 0 15 15 Halfword data External data bus 3 Word access 32 bits In word access to external memory the lower halfword is...

Page 131: ... Memory Block Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 On chip peripheral I O area Internal RAM area External memory area FFFFFFH F00000H EFFFFFH E00000H DFFFFFH D00000H CFFFFFH C00000H BFFFFFH B00000H AFFFFFH A00000H 9FFFFFH 900000H 8FFFFFH 800000H 7FFFFFH 700000H 6FFFFFH 600000H 5FFFFFH 500000H 4FFFFFH 4...

Page 132: ...F060H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DWC Number of wait states to be inserted 0 0 0 0 1 1 1 0 2 1 1 3 n Blocks into which wait states are inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 15 Block 0 is reserved for the internal ROM area It is not subject to programmable wait control regardless of the setting of DWC and...

Page 133: ...1 pin and WAIT pin are alternate function pins the wait function by the WAIT pin cannot be used when using a separate bus programmable wait can be used however Similarly a separate bus cannot be used when the wait function by the WAIT pin is being used 4 5 3 Relationship between programmable wait and external wait A wait cycle is inserted as a result of an OR operation between the wait cycle speci...

Page 134: ...ll memory blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units After reset AAAAH R W Address FFFFF062H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCC Idle state insertion specification 0 Not inserted 1 Inserted n Blocks into which idle state is inserted 0 Blocks 0 1 1 Blocks 2 3 2 Blocks 4 5 3 Blocks 6 7 4 Blocks 8 9 5 Blocks 10 11 6 Blocks 12 13 7 Blocks 14 ...

Page 135: ...ve high indicating that the request for the bus is cleared these pins are driven again During the bus hold period the internal operation continues until the next external memory access The bus hold status can be recognized by the HLDAK pin becoming active low This feature can be used to design a system where two or more bus masters exist such as when a multi processor configuration is used and whe...

Page 136: ...HLDAK 1 8 Clears pending bus cycle start requests 9 Start of bus cycle Normal status Bus hold status Normal status 4 7 3 Operation in power save mode In the IDLE or software STOP mode the system clock is stopped Consequently the bus hold status is not set even if the HLDRQ pin becomes active In the HALT mode the HLDAK pin immediately becomes active when the HLDRQ pin becomes active and the bus hol...

Page 137: ...et these modes by using the BIC bit of the system control register SYC see 4 2 2 1 System control register SYC Figure 4 8 Memory Read 1 4 a 0 waits T1 T2 T3 CLKOUT output A16 to A21 output AD0 to AD15 I O Address Data Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output H A1 to A15 output Address Remarks 1 indicates the sampling timing when the number of program...

Page 138: ... output A16 to A21 output AD0 to AD15 I O Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data H A1 to A15 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 1 2 The broken line indicates the high impedance state ...

Page 139: ...CLKOUT output A1 to A15 output AD0 to AD15 I O Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output H TI Data A16 to A21 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 140: ...KOUT output A1 to A15 output AD0 to AD15 I O Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data TI H A16 to A21 output Address Remarks 1 indicates the sampling timing when the number of programmable waits is set to 1 2 The broken line indicates the high impedance state ...

Page 141: ...t R W output DSTB output UBEN LBEN output WAIT input RD output WRH WRL output H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 0 2 The broken line indicates the high impedance state ...

Page 142: ...utput UBEN LBEN output WAIT input RD output WRH WRL output T3 DataNote Address H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 output invalid data when even address byte data is accessed Remarks 1 indicates the sampling timing when the number of programmable waits is set to 1 2 The broken line indicates the high impedance state ...

Page 143: ... Address ASTB output Undefined Address Note 1 Note 2 Address Notes 1 If the HLDRQ signal is inactive high level at this sampling timing the bus hold state is not entered 2 If the bus hold status is entered after a write cycle a high level may be output momentarily from the R W pin immediately before the HLDAK signal changes from high level to low level Remarks 1 indicates the sampling timing when ...

Page 144: ...mory access instruction fetch branch and instruction fetch continuous in that order The instruction fetch cycle may be inserted between the read access and write access in a read modify write access No instruction fetch cycle is inserted between the lower halfword access and higher halfword access of word access operations Table 4 3 Bus Priority External Bus Cycle Priority Bus hold 1 Memory access...

Page 145: ...rnal memory 2 A prefetch operation straddling over the on chip peripheral I O area invalid fetch does not take place if a branch instruction exists at the upper limit address of the internal RAM area 4 10 2 Data space Only the address aligned at the halfword boundary when the least significant bit of the address is 0 word boundary when the lowest 2 bits of the address are 0 boundary is accessed by...

Page 146: ...askable interrupts 2 sources Maskable interrupts the number of maskable interrupt sources differs depending on the product V850 SB1 µPD703030B 703031A 703031B 703032A 703032B 703033A 703033B 70F3030B 70F3032A 70F3032B 70F3033A 70F3033B 37 sources µPD703030BY 703031AY 703031BY 703032AY 703032BY 703033AY 703033BY 70F3030BY 70F3032AY 70F3032BY 70F3033AY 70F3033BY 38 sources V850 SB2 µPD703034A 703034...

Page 147: ...TP5 INTP5 pin Pin 00E0H 000000E0H nextPC PIC5 7 INTP6 INTP6 pin Pin 00F0H 000000F0H nextPC PIC6 8 INTWTNI Watch timer prescaler WT 0140H 00000140H nextPC WTNIIC 9 INTTM00 INTTM00 TM0 0150H 00000150H nextPC TMIC00 10 INTTM01 INTTM01 TM0 0160H 00000160H nextPC TMIC01 11 INTTM10 INTTM10 TM1 0170H 00000170H nextPC TMIC10 12 INTTM11 INTTM11 TM1 0180H 00000180H nextPC TMIC11 13 INTTM2 TM2 compare match ...

Page 148: ...er end DMA2 02E0H 000002E0H nextPC DMAIC2 35 INTDMA3 DMA3 transfer end DMA3 02F0H 000002F0H nextPC DMAIC3 36 INTDMA4 DMA4 transfer end DMA4 0300H 00000300H nextPC DMAIC4 37 INTDMA5 DMA5 transfer end DMA5 0310H 00000310H nextPC DMAIC5 38 INTWTN Watch timer OVF WT 0320H 00000320H nextPC WTNIC Maskable Interrupt 39 INTKR Key return interrupt KR 0330H 00000330H nextPC KRIC Notes 1 Available only in th...

Page 149: ...s the non maskable interrupt INTWDT only in the state in which the WDTM4 bit of the watchdog timer mode register WDTM is set to 1 While the service routine of a non maskable interrupt is being executed PSW NP 1 the acknowledgment of another non maskable interrupt request is held pending The pending NMI is acknowledged after the original service routine of the non maskable interrupt under execution...

Page 150: ...on codes 0010H and 0020H to the higher halfword FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Loads the handler address 00000010H 00000020H of the non maskable interrupt routine to the PC and transfers control Figure 5 1 Non Maskable Interrupt Servicing NMI input Non maskable interrupt request Interrupt servicing Interrupt request pending FEPC FEPSW ECR FECC PSW NP PSW E...

Page 151: ...uest NMI request PSW NP 1 NMI request held pending because PSW NP 1 Pending NMI request processed b If a new NMI request is generated twice while an NMI service routine is being executed Main routine NMI request NMI request Held pending because NMI service program is being processed Held pending because NMI service program is being processed NMI request Only one NMI request is acknowledged even th...

Page 152: ...bit of the PSW is 1 2 Transfers control back to the address of the restored PC and PSW How the RETI instruction is processed is shown below Figure 5 3 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt servicin...

Page 153: ... 5 4 3 2 1 0 PSW 0 NP EP ID SAT CY OV S Z NP NMI servicing state 0 No NMI interrupt servicing 1 NMI interrupt currently being serviced 5 2 4 Noise eliminator of NMI pin NMI pin noise is eliminated by the noise eliminator using analog delay Therefore a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period The edge is detected after a certain...

Page 154: ...e is specified by using the EGP0 and EGN0 registers When using P00 as an output port set the NMI valid edge to detect neither rising nor falling edge 1 Rising edge specification register 0 EGP0 After reset 00H R W Address FFFFF0C0H Symbol 7 6 5 4 3 2 1 0 EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00 EGP0n Rising edge valid control 0 No interrupt request signal occurred at the rising edge 1 ...

Page 155: ...interrupts with the same priority level cannot be nested To use multiple interrupts it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction When the WDTM4 bit of the watchdog timer mode register WDTM is set to 0 the watchdog timer overflow interru...

Page 156: ... accepted CPU processing Mask Yes No PSW ID 0 Priority higher than that of interrupt currently serviced Interrupt request pending PSW NP PSW ID Interrupt request pending No No No No 1 0 1 0 INT input Yes Yes Yes Yes Priority higher than that of other interrupt request Highest default priority of interrupt requests with the same priority Interrupt enable mode Restored PC PSW Exception code 0 1 Hand...

Page 157: ...f PSW is 0 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 5 RETI Instruction Processing RETI instruction Restores original processing PC PSW EIPC EIPSW PSW EP 1 0 1 0 PC PSW FEPC FEPSW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during maskable interrupt servicing in order to...

Page 158: ...ority level specified by xxPRn are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level before hand For more information refer to Table 5 1 Programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag Note that when an interrupt re...

Page 159: ...is held pending even if interrupts are enabled because its priority is the same as that of g Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled Although the priority of interrupt request d is higher than that of c d is held p...

Page 160: ...1 Servicing of p Servicing of q Servicing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status Pending interrupt requests are acknowledged after...

Page 161: ...rupt request c Servicing of interrupt request a Interrupt request b and c are acknowledged first according to their priorities Because the priorities of b and c are the same b is acknowledged first because it has the higher default priority NMI request Notes 1 Higher default priority 2 Lower default priority Remarks 1 a b and c in the above figure are the names of interrupt requests shown for the ...

Page 162: ...n as the interrupt request flag xxIFn is generated DMA is started during execution of a bit manipulation instruction corresponding to the interrupt request flag xxIFn Two workarounds using software are shown below Insert a DI instruction before the software based bit manipulation instruction and an EI instruction after it so that jumping to an interrupt immediately after the bit manipulation instr...

Page 163: ...ag 0 Interrupt servicing enabled 1 Interrupt servicing disabled pending xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 highest 0 0 1 Specifies level 1 0 1 0 Specifies level 2 0 1 1 Specifies level 3 1 0 0 Specifies level 4 1 0 1 Specifies level 5 1 1 0 Specifies level 6 1 1 1 Specifies level 7 lowest Note Automatically reset by hardware when an interrupt request ...

Page 164: ... TMPR61 TMPR60 FFFFF12CH TMIC7 TMIF7 TMMK7 0 0 0 TMPR72 TMPR71 TMPR70 FFFFF12EH CSIC0 CSIF0 CSMK0 0 0 0 CSPR02 CSPR01 CSPR00 FFFFF130H SERIC0 SERIF0 SERMK0 0 0 0 SERPR02 SERPR01 SERPR00 FFFFF132H CSIC1 CSIF1 CSMK1 0 0 0 CSPR12 CSPR11 CSPR10 FFFFF134H STIC0 STIF0 STMK0 0 0 0 STPR02 STPR01 STPR00 FFFFF136H CSIC2 CSIF2 CSMK2 0 0 0 CSPR22 CSPR21 CSPR20 FFFFF138H IICIC1Note 1 IICIF1 IICMK1 0 0 0 IICPR1...

Page 165: ...tly acknowledged 0 Interrupt request with priority n not acknowledged 1 Interrupt request with priority n acknowledged Remark n 0 to 7 priority level 5 3 6 ID flag The interrupt disable status flag ID of the PSW controls the enabling and disabling of maskable interrupt requests As a status flag it also displays the current maskable interrupt acknowledgment status After reset 00000020H Symbol 31 8 ...

Page 166: ...that functions using analog delay Therefore a signal input to each pin is not detected as an edge unless it maintains its input level for a certain period An edge is detected after a certain period has elapsed 2 Noise elimination of INTP4 and INTP5 pins The INTP4 and INTP5 pins incorporate a digital noise eliminator If the input level of the INTP pin is detected by the sampling clock fXX and the s...

Page 167: ... eliminator For that reason if an INTP6 valid edge was input within these 3 clocks an interrupt request may occur Therefore be careful of the following when using the interrupt and DMA functions When using the interrupt function after 3 sampling clocks have elapsed enable interrupts after the interrupt request flag bit 7 of PIC6 has been cleared When using the DMA function after 3 sampling clocks ...

Page 168: ...validity of the falling edge is controlled by falling edge specification register 0 EGN0 Refer to 5 2 5 Edge detection function of NMI pin for details of EGP0 and EGN0 After reset the valid edge of the NMI pin is set to the detect neither rising nor falling edge state Therefore the NMI pin functions as a normal port and an interrupt request cannot be acknowledged unless a valid edge is specified b...

Page 169: ... processing and transfers control to the handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower 16 bits EICC of ECR interrupt source 4 Sets the EP and ID bits of the PSW 5 Loads the handler address 00000040H or 00000050H of the software exception routine in the PC and transfers control How a software exception is processed is shown ...

Page 170: ...f the PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 9 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception process in or...

Page 171: ...ered as an exception trap Illegal opcode exception Occurs if the sub opcode field of the instruction to be executed next is not a valid opcode 5 5 1 Illegal opcode definition An illegal opcode is defined to be a 32 bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B to 1111B Figure 5 10 Illegal Opcode 15 16 17 23 22 x 21 x 20 x x x x x x x x x x x x x x x 1 1 1 1 1 1 x x x x x 2...

Page 172: ...Manual U13850EJ6V0UD 172 How the exception trap is processed is shown below Figure 5 11 Exception Trap Processing Exception trap ILGOP occurs EIPC EIPSW ECR EICC PSW EP PSW ID PC Restored PC PSW Exception code 1 1 00000060H CPU processing Exception processing ...

Page 173: ...t of the PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 12 RETI Instruction Processing RETI instruction Jump to PC PC PSW EIPC EIPSW PSW EP 1 0 1 0 PC PSW FEPC FEPSW PSW NP Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the exception trap process in order to restore the...

Page 174: ...ing is a function that allows the nesting of interrupts If a higher priority interrupt is generated and acknowledged it will be allowed to stop a current interrupt service routine in progress Execution of the original routine will resume once the higher priority interrupt routine is completed If an interrupt with a lower or equal priority is generated and a service routine is currently in progress...

Page 175: ...register EI instruction enables interrupt acknowledgment DI instruction disables interrupt acknowledgment Restore saved value to EIPSW Restore saved value to EIPC RETI instruction Save EIPC to memory or register Save EIPSW to memory or register EI instruction enables interrupt acknowledgment TRAP instruction Illegal opcode Restore saved value to EIPSW Restore saved value to EIPC RETI instruction A...

Page 176: ...name of each peripheral unit refer to Table 5 2 n Number of each peripheral unit refer to Table 5 2 Priorities of maskable interrupts High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt servicing that has been suspended as a result of multiple interrupt servicing is resumed after the interrupt servicing of the higher priority has been completed and the RETI instructi...

Page 177: ...nowledgment processing IFX Invalid instruction fetch IDX Invalid instruction decode Interrupt Latency Time System Clock Internal interrupt External interrupt Condition Minimum 11 13 Maximum 18 20 Time to eliminate noise 2 system clocks is also necessary for external interrupts except when In IDLE STOP mode External bus is accessed Two or more interrupt request non sample instructions are executed ...

Page 178: ...ows an example of program processing Program processing example DI MK flag 0 Interrupt request occurs IF flag 1 EI EI instruction executed NOP 1 system clock NOP 1 system clock NOP 1 system clock NOP 1 system clock JR LP1 3 system clocks branch to LP1 routine LP1 LPI routine DI After EI instruction execution NOP instruction is executed four times and DI instruction is executed at the eighth clock ...

Page 179: ...errupt request is acknowledged b When DI instruction is executed at seventh clock after EI instruction execution interrupt request is not acknowledged ei signal intrq signal ei signal intrq signal intrq signal is generated intrq signal is not generated 5 9 Interrupt Control Register Bit Manipulation Instructions During DMA Transfer To manipulate the bits of the interrupt control register xxICn in ...

Page 180: ...its 1 Key return mode register KRM After reset 00H R W Address FFFFF3D0H 7 6 5 4 3 2 1 0 KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KRMn Key return mode control 0 Do not detect key return signal 1 Detect key return signal Caution If the key return mode register KRM is changed an interrupt request flag may be set To avoid setting this flag change the KRM register after disabling interrupts and then enable ...

Page 181: ... 5 INTERRUPT EXCEPTION PROCESSING FUNCTION User s Manual U13850EJ6V0UD 181 Figure 5 15 Key Return Block Diagram INTKR Key return mode register KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0 ...

Page 182: ...lock timer without using the subclock oscillator Cautions 1 When the main oscillator is stopped by inputting a reset or executing a STOP instruction the oscillation stabilization time is secured after the stop mode is released This oscillation stabilization time is set via the oscillation stabilization time selection register OSTS The watchdog timer is used as the timer that counts the oscillation...

Page 183: ... Clock Output Function This function outputs the CPU clock via the CLKOUT pin When clock output is enabled the CPU clock is output via the CLKOUT pin When it is disabled a low level signal is output via the CLKOUT pin Output is stopped in the IDLE or STOP mode fixed to low level This function is controlled via the DCLK1 and DCLK0 bits in the power save control register PSC The high impedance statu...

Page 184: ...peration of main clock main clock 0 Operating 1 Stopped CK2Notes 1 2 CK1 CK0 Selection of CPU clock 0 0 0 fXX 0 0 1 fXX 2 0 1 0 fXX 4 0 1 1 fXX 8 1 X X fXT subclock Notes 1 If manipulating CK2 do so in 1 bit units In the case of 8 bit manipulation do not change the values of CK1 and CK0 2 When the CPU operates on the subclock CK2 1 do not set the HALT or software STOP mode Cautions 1 While CLKOUT ...

Page 185: ... clock frequency before setting subclock frequency 2 Therefore insert the wait described above using a program 3 MCK 1 Only when the main clock is stopped b Example of subclock operation main clock operation setup 1 MCK 0 Main clock oscillation start 2 Insert a wait using a program and wait until the main clock oscillation stabilization time elapses 3 CK2 0 Bit manipulation instructions are recomm...

Page 186: ...dress FFFFF070H 7 6 5 4 3 2 1 0 PSC DCLK1 DCLK0 0 0 0 IDLE STP 0 DCLK1 DCLK0 Specification of CLKOUT pin s operation 0 0 Output enabled 0 1 Setting prohibited 1 0 Setting prohibited 1 1 Output disabled when reset IDLE IDLE mode setting 0 Normal mode 1 IDLE modeNote 1 STP STOP mode setting 0 Normal mode 1 STOP modeNote 2 Notes 1 When IDLE mode is released this bit is automatically reset to 0 2 When...

Page 187: ...reset 04H R W Address FFFFF380H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time fXX OSTS2 OSTS1 OSTS0 Clock 20 MHzNote 12 58 MHz 0 0 0 214 fxx 819 2 µs 1 3 ms 0 0 1 216 fXX 3 3 ms 5 2 ms 0 1 0 217 fXX 6 6 ms 10 4 ms 0 1 1 218 fXX 13 1 ms 20 8 ms 1 0 0 219 fXX 26 2 ms 41 6 ms Other than above Setting prohibited Note Only in the V850 SB1 ...

Page 188: ...ies a clock to the on chip peripheral functions When this mode is released there is no need for the oscillator to wait for the oscillation stabilization time so normal operation can be resumed quickly When the IDLE bit of the power saving control register PSC is set to 1 the system switches to IDLE mode 3 Software STOP mode This mode stops the entire system by stopping the main clock oscillator Th...

Page 189: ... CPU is operating on the main clock The operating statuses in the HALT mode are listed in Table 6 1 2 Release of HALT mode HALT mode can be released by an NMI request an unmasked maskable interrupt request or RESET input a Release by interrupt request HALT mode is released regardless of the priority level when an NMI request or an unmasked maskable interrupt request occurs However the following oc...

Page 190: ...it timer TM1 Operating 8 bit timer TM2 Operating 8 bit timer TM3 Operating 8 bit timer TM4 Operating 8 bit timer TM5 Operating 8 bit timer TM6 Operating 8 bit timer TM7 Operating Watch timer Operates when main clock is selected for count clock Operating Watchdog timer Operating interval timer only CSI0 to CSI3 Operating I2 C0Note I2 C1Note Operating UART0 UART1 Operating Serial interface CSI4 Oper...

Page 191: ...erating External interrupt request INTP6 Operating Key return function Operating AD0 to AD15 High impedanceNote A16 to A21 HeldNote high impedance when HLDAK 0 LBEN UBEN HeldNote high impedance when HLDAK 0 R W DSTB WRL WRH RD ASTB High level outputNote high impedance when HLDAK 0 In external expansion mode HLDAK Operating Note Even when the HALT instruction has been executed the instruction fetch...

Page 192: ...e Settings Item When Subclock Exists When Subclock Does Not Exist CPU Stopped ROM correction Stopped Clock generator Both main clock and subclock oscillator Clock supply to CPU and on chip peripheral functions is stopped 16 bit timer TM0 Operates when INTWTNI is selected as count clock fXT is selected for watch timer Stopped 16 bit timer TM1 Stopped 8 bit timer TM2 Stopped 8 bit timer TM3 Stopped ...

Page 193: ...xists When Subclock Does Not Exist External bus interface Stopped NMI Operating INTP0 to INTP3 Operating INTP4 and INTP5 Stopped External interrupt request INTP6 Operates when fXT is selected for sampling clock Stopped Key return Operating AD0 to AD15 A16 to A21 LBEN UBEN R W DSTB WRL WRH RD ASTB In external expansion mode HLDAK High impedance Item ...

Page 194: ...errupt an unmasked interrupt request or RESET input When the STOP mode is released the oscillation stabilization time is secured Table 6 3 Operating Statuses in Software STOP Mode 1 2 Item When Subclock Exists When Subclock Does Not Exist CPU Stopped ROM correction Stopped Clock generator Oscillation for main clock is stopped and oscillation for subclock continues Clock supply to CPU and on chip p...

Page 195: ...tput Operates when INTTM4 or INTTM5 has been selected when TM4 or TM5 is operating Stopped Port function Held External bus interface Stopped NMI Operating INTP0 to INTP3 Operating INTP4 and INTP5 Stopped External interrupt request INTP6 Operates when fXT is selected for the noise eliminator Stopped Key return Operating AD0 to AD15 A16 to A21 LBEN UBEN R W DSTB WRL WRH RD ASTB In external expansion...

Page 196: ...ust elapse for stabilization of the oscillator s clock output The oscillation stabilization time is set by the oscillation stabilization time select register OSTS Oscillation stabilization time WDT count time After the specified amount of time has elapsed system clock output starts and processing branches to the interrupt handler address Figure 6 2 Oscillation Stabilization Time STOP mode is set O...

Page 197: ...0 6 Insert NOP instructions 2 or 5 instructions 7 If DMA operation is necessary enable DMA operation Cautions 1 Insert two NOP instructions if the ID bit value of the PSW is not changed by the execution of the instruction that clears the NP bit to 0 5 and insert five NOP instructions 6 if it is changed The following shows a description example Description example When using PSC register LDSR rX 5 ...

Page 198: ...nt instruction is executed while an interrupt request is being held pending after the power save mode has been released Conditions in which an interrupt request is held pending If the NP flag of the PSW register is 1 during NMI servicing set by software If the ID flag of the PSW register is 1 during interrupt request servicing DI instruction set by software If the power save mode is released by an...

Page 199: ... PSW ST B r0 PRCMD r0 Writes data to PRCMD ST B rD PSC r0 Sets PSC register LDSR rY 5 Returns value of PSW NOP Six NOP instructions or more NOP NOP NOP NOP BR 2 Eliminates discrepancy of PC Remark It is assumed that the following values have already been set rD PSC set value rX Value written to PSW rY Value written back to PSW ...

Page 200: ...d support of edge specification Timer output operated by match detection 1 each TOn When using the P34 TO0 and P35 TO1 pins as TO0 and TO1 timer outputs set the value of port 3 P3 to 0 port mode output and the port 3 mode register PM3 to 0 The logical sum ORed value of the output of the port and the timer is output Remark n 0 1 7 1 2 Function TM0 and TM1 have the following functions Interval timer...

Page 201: ...Mn0 3 Timer output control register n TOCn fXX 2 Selector Selector Selector Selector PRMn2 Prescaler mode register n1 PRMn1 Noise eliminator Noise eliminator Note The count clock is set by the PRMn0 and PRMn1 registers Remark n 0 1 1 Interval timer Generates an interrupt at predetermined time intervals 2 PPG output Can output a square wave whose frequency and output pulse width can be changed arbi...

Page 202: ...RMn0 PRMn1 1 16 bit timer registers 0 1 TM0 TM1 TMn is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of the input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count value is reset to 0000H in the following cases 1 At RESET inpu...

Page 203: ... is specified as the capture trigger refer to Table 7 3 Table 7 2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 ESn01 ESn00 Valid Edge of TIn0 Pin CRn0 Capture Trigger 0 0 Falling edge Rising edge 0 1 Rising edge Falling edge 1 0 Setting prohibited Setting prohibited 1 1 Both rising and falling edges No capture operation Remark n 0 1 Table 7 3 Valid Edge of TIn1 Pin and Capture Trigger of CRn...

Page 204: ...d as the valid edge of TIn0 the relationship between the TIn0 valid edge and the CRn1 capture trigger is as follows Table 7 4 TIn0 Pin Valid Edge and CRn1 Capture Trigger ESn01 ESn00 TIn0 Pin Valid Edge CRn1 Capture Trigger 0 0 Falling edge Falling edge 0 1 Rising Edge Rising Edge 1 0 Setting prohibited Setting prohibited 1 1 Both rising and falling edges Both rising and falling edges Remark n 0 1...

Page 205: ...16 bit timer register n TMn 16 bit capture compare registers n0 n1 CRn0 CRn1 1 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of 16 bit timer register n TMn TMCn is set by an 8 bit or 1 bit memory manipulation instruction RESET input clears TMC0 and TMC1 to 00H Caution 16 bit timer regi...

Page 206: ...0 1 1 0 Clears and starts on match between TMn and CRn0 Match between TMn and CRn0 or match between TMn and CRn1 1 1 1 Match between TMn and CRn0 match between TMn and CRn1 or valid edge of TIn0 OVFn Detection of overflow of 16 bit timer register n 0 Did not overflow 1 Overflowed Cautions 1 When a bit other than the OVFn bit is written be sure to stop the timer operation 2 The valid edge of the TI...

Page 207: ... in reverse phase of valid edge of TIn0 CRCn0 Selection of operation mode of CRn0 0 Operates as compare register 1 Operates as capture register Cautions 1 Before setting CRCn be sure to stop the timer operation 2 When the mode in which the timer is cleared and started on a match between TMn and CRn0 is selected by 16 bit timer mode control register n TMCn do not specify CRn0 as a capture register ...

Page 208: ...tion 0 Successive pulse output 1 One shot pulse outputNote TOCn4 Control of timer output F F on match between CRn1 and TMn 0 Reverse timer output F F disabled 1 Reverse timer output F F disabled LVSn LVRn Setting of status of timer output F F of timer n 0 0 Not affected 0 1 Resets timer output F F 0 1 0 Sets timer output F F 1 1 1 Setting prohibited TOCn1 Control of timer output F F on match betwe...

Page 209: ...00 Count clock 20 MHzNote 2 12 58 MHz 0 0 0 fXX 2 100 ns 158 ns 0 0 1 fXX 16 800 ns 1 3 µs 0 1 0 INTWTNI 0 1 1 TI00 valid edgeNote 1 1 0 0 fXX 4 200 ns 318 ns 1 0 1 fXX 64 3 2 µs 5 1 µs 1 1 0 fXX 256 12 8 µs 20 3 µs 1 1 1 Setting prohibited Notes 1 The external clock requires a pulse longer than twice that of the internal clock fXX 2 2 Only in the V850 SB1 Cautions 1 When selecting the valid edge ...

Page 210: ... clock 20 MHzNote 2 12 58 MHz 0 0 0 fXX 2 100 ns 158 ns 0 0 1 fXX 4 200 ns 318 ns 0 1 0 fXX 16 800 ns 1 3 µs 0 1 1 TI10 valid edgeNote 1 1 0 0 fXX 32 1 6 µs 2 5 µs 1 0 1 fXX 128 6 4 µs 10 2 µs 1 1 0 fXX 256 12 8 µs 20 3 µs 1 1 1 Setting prohibited Notes 1 The external clock requires a pulse longer than twice that of the internal clock fXX 2 2 Only in the V850 SB1 Cautions 1 When selecting the vali...

Page 211: ...est signal INTTMn0 is generated The count clock of the 16 bit timer event counter can be selected by the PRMn0 and PRMn1 bits of prescaler mode register n0 PRMn0 and by the PRMn2 bit of prescaler mode register n1 PRMn1 Figure 7 2 Control Register Settings When TMn Operates as Interval Timer a 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 1 0 Clears and...

Page 212: ... 7 4 Timing of Interval Timer Operation TMn count value CRn0 0000H 0001H N N N N N N N 0000H 0001H 0000H 0001H Count start Clear Clear Interrupt acknowledgment Interrupt acknowledgment INTTMn0 TOn Interval time Interval time Interval time Count clock t Remarks 1 Interval time N 1 t N 0001H to FFFFH 2 n 0 1 TIn0 Noise eliminator 16 bit capture compare register n0 CRn0 Count clockNote Selector 16 bi...

Page 213: ...Operation a 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 0 Clears and starts on match between TMn and CRn0 b Capture compare control registers 0 1 CRC0 CRC1 CRCn2 CRCn1 CRCn0 CRCn 0 0 0 0 0 0 0 CRn0 used as compare register CRn1 used as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0...

Page 214: ...r 16 bit timer register n TMn Clear circuit Output controller Note The count clock is set by the PRMn0 and PRMn1 registers Remarks 1 indicates a signal that can be directly connected to a port 2 n 0 1 Figure 7 7 PPG Output Operation Timing t 0000H 0000H 0001H 0001H M 1 TOn N M M N 1 N Count clock TMn count value Value loaded to CRn0 Value loaded to CRn1 Clear Count starts Pulse width M 1 t 1 cycle...

Page 215: ...er mode register n0 PRMn0 The rising edge falling edge or both the rising and falling edges can be selected The valid edge is detected by sampling at the count clock cycle selected by prescaler mode register n0 n1 PRMn0 PRMn1 and a capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be eliminated Figure 7 8 Control Register Se...

Page 216: ... connected to a port 2 n 0 1 Figure 7 10 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with Both Edges Specified t Value loaded to CRn1 TIn0 pin input TMn count value 0000H 0001H D0 FFFFH D1 0000H D2 D3 INTTMn1 D0 OVFn D1 D0 t 10000H D1 D2 t Count clock D1 D2 D3 D3 D2 t D0 1 D1 1 Remark n 0 1 16 bit capture compare register n1 CRn1 16 bit timer register n TMn...

Page 217: ...he ESn10 and ESn11 bits of PRMn0 respectively The rising falling or both rising and falling edges can be specified The valid edge is detected by sampling at the count clock cycle selected by prescaler mode register n0 n1 PRMn0 PRMn1 and a capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be eliminated Figure 7 11 Control Reg...

Page 218: ...ge Specified Count clock TMn TIn0 CRn1 INTTMn1 N 1 N N 1 N 2 N 3 N Rising edge detection Remark n 0 1 Figure 7 13 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Specified t Value loaded to CRn1 D1 D0 t 10000H D1 D2 t D3 D2 t 10000H D1 D2 1 t 0000H 0001H D0 Count clock TMn count value TIn0 pin input INTTMn1 TIn1 pin input INTTMn0 OVFn Value loaded to CRn0 D0 1 D1 D1 1 F...

Page 219: ...unt clock cycle selected by prescaler mode register n0 n1 PRMn0 PRMn1 and a capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be eliminated Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges capture compare register n0 CRn0 cannot perform its capture operation Figure 7 14 Control R...

Page 220: ...be measured by clearing 16 bit timer register n TMn once and then resuming counting after loading the count value of TMn to 16 bit capture compare register n1 CRn1 See Figure 7 17 The edge is specified by the ESn00 and ESn01 bits of prescaler mode register n0 PRMn0 The rising or falling edge can be specified The valid edge is detected by sampling at the count clock cycle selected by prescaler mode...

Page 221: ...res to CRn0 at edge reverse to valid edge of TIn0 CRn1 used as capture register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used along with the pulse width measurement function For details refer to 7 1 4 1 16 bit timer mode control registers 0 1 TMC0 TMC1 and 7 1 4 2 Capture compare control registers 0 1 CRC0 CRC1 Figure 7 17 Timing of Pulse Width Measurement by Re...

Page 222: ...rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle of fXX 2 and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be removed Figure 7 18 Control Register Settings in External Event Counter Mode a 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn3 TMCn2 TMCn1 ...

Page 223: ...t Counter Operation with Rising Edge Specified TIn0 pin input TMn count value CRn0 INTTMn0 0001H 0000H N 1 N N 0003H 0002H 0005H 0004H 0001H 0000H 0003H 0002H Caution Read TMn when reading the count value of the external event counter Remark n 0 1 7 2 5 Operation to output square wave TMn can be used to output a square wave with any frequency at the interval specified by the count value set in adv...

Page 224: ...tput control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 0 0 0 1 0 1 1 1 Enables TOn output Reverses output on match between TMn and CRn0 Specifies initial value of TOn output F F Does not reverse output on match between TMn and CRn1 Disables one shot pulse output Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used along with the square wav...

Page 225: ...16 bit timer output control register n TOCn as shown in Figure 7 23 and by setting the OSPTn bit of TOCn by software By setting OSPTn to 1 the 16 bit timer event counter is cleared and started and its output is asserted at the count value N set in advance to 16 bit capture compare register n1 CRn1 After that the output is deasserted at the count value M set in advance to 16 bit capture compare reg...

Page 226: ...rs 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Reverses output on match between TMn and CRn0 Specifies initial value of TOn output F F Reverses output on match between TMn and CRn1 Sets one shot pulse output mode Set to 1 for output Caution Do not set CRn0 and CRn1 to 0000H Remark 0 1 When these bits are reset to 0 or set to 1 other functions ca...

Page 227: ...t control register n TOCn as shown in Figure 7 25 and by using the valid edge of the TIn0 pin as an external trigger The valid edge of the TIn0 pin is specified by bits 4 and 5 ESn00 and ESn01 of prescaler mode register n0 PRMn0 The rising falling or both the rising and falling edges can be specified When the valid edge of the TIn0 pin is detected the 16 bit timer event counter is cleared and star...

Page 228: ... output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Reverses output on match between TMn and CRn0 Specifies initial value of TOn output F F Reverses output on match between TMn and CRn1 Sets one shot pulse output mode Caution Do not set CRn0 and CRn1 to 0000H Remark 0 1 When these bits are reset to 0 or set to 1 other functions...

Page 229: ...ified Count clock TMn count value 0000H 0001H N 1 M 2 N 2 M 1 M 1 M Value to set CRn1 N Value to set CRn0 M TIn0 pin input INTTMn1 INTTMn0 TOn pin output Sets 08H to TMCn TMn count starts 0000H N M 2 N M N M N M Caution 16 bit timer register n starts operating as soon as TMCn2 and TMCn3 have been set to values other than 0 0 operation stop mode Remark n 0 1 N M ...

Page 230: ... pulse count operation is disabled when these registers are used as event counters 3 Setting compare register during timer count operation If the value to which the current value of 16 bit capture compare register n0 CRn0 has been changed is less than the value of 16 bit timer register n TMn TMn continues counting overflows and starts counting again from 0 If the new value of CRn0 M is less than t...

Page 231: ...nd TMCn3 bits of 16 bit timer mode control register n to 0 0 Set the valid edge by using the ESn00 and ESn01 bits of prescaler mode register n0 PRMn0 6 Re triggering one shot pulse a One shot pulse output by software When a one shot pulse is being output do not set OSPTn to 1 Do not output the one shot pulse again until the current one shot pulse output ends b One shot pulse output with external t...

Page 232: ...re trigger input conflict When 16 bit capture compare registers n0 and n1 CRn0 CRn1 are used as capture registers if the read period and capture trigger input conflict the capture trigger has priority The read data of CRn0 and CRn1 is undefined b If the match timings of the write period and TMn conflict When 16 bit capture compare registers n0 and n1 CRn0 CRn1 are used as capture registers because...

Page 233: ...1 Compare operation a When rewriting CRn0 and CRn1 during timer operation When rewriting 16 bit timer capture compare registers n0 and n1 CRn0 CRn1 if the value is close to or larger than the timer value the match interrupt request generation or clear operation may not be performed correctly b When CRn0 and CRn1 are set to compare mode When CRn0 and CRn1 are set to compare mode they do not perform...

Page 234: ...Functions 8 bit timer n has the following two modes n 2 to 7 Mode using timer alone individual mode Mode using cascade connection 16 bit resolution cascade connection mode Caution Do not access following registers when not using the cascade connection 16 bit counters TM23 TM45 TM67 16 bit compare registers CR23 CR45 CR67 The two modes are described next 1 Mode using timer alone individual mode The...

Page 235: ...n connecting in cascade Registers 8 bit compare registers 2 to 7 CR20 to CR70 16 bit compare registers 23 45 67 CR23 CR45 CR67 Only when connecting in cascade Timer outputs TO2 to TO5 Control registers Timer clock selection registers 20 to 70 and 21 to 71 TCL20 to TCL70 and TCL21 to TCL71 8 bit timer mode control registers 2 to 7 TMC2 to TMC7 8 bit compare register n CRn0 8 bit counter n TMn Match...

Page 236: ...r timers TM2 TM4 TM6 is cleared Remark n 2 to 7 m 2 4 6 2 8 bit compare registers 2 to 7 CR20 to CR70 The CRn0 register is set by an 8 bit memory manipulation instruction The value set in CRn0 is always compared to the count in 8 bit counter n TMn If the two values match an interrupt request INTTMn is generated except in the PWM mode The value of CRn0 can be set in the range of 00H to FFH and can ...

Page 237: ...t clock 20 MHzNote 12 58 MHz 0 0 0 0 TIn falling edge 0 0 0 1 TIn rising edge 0 0 1 0 fXX 4 200 ns 318 ns 0 0 1 1 fXX 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 µs 0 1 0 1 fXX 32 1 6 µs 2 5 µs 0 1 1 0 fXX 128 6 4 µs 10 2 µs 0 1 1 1 fXX 512 25 6 µs 40 7 µs 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 fXX 64 3 2 µs 5 1 µs 1 0 1 1 fXX 256 12 8 µs 20 3 µs 1 1 0 0 Setting prohibited 1 1...

Page 238: ...0 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 µs 0 1 0 1 fXX 32 1 6 µs 2 5 µs 0 1 1 0 fXX 128 6 4 µs 10 2 µs 0 1 1 1 fXT Subclock 30 5 µs 30 5 µs 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 fXX 64 3 2 µs 5 1 µs 1 0 1 1 fXX 256 12 8 µs 20 3 µs 1 1 0 0 Setting prohibited 1 1 0 1 Setting prohibited 1 1 1 0 Setting prohibited 1 1 1 1 Setting prohibited Note Only in the V850 SB1 Cautions 1 Wh...

Page 239: ... 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 µs 0 1 0 1 fXX 32 1 6 µs 2 5 µs 0 1 1 0 fXX 64 3 2 µs 5 1 µs 0 1 1 1 fXX 128 6 4 µs 10 2 µs 1 0 0 0 Setting prohibited 1 0 0 1 Setting prohibited 1 0 1 0 fXX 256 12 8 µs 20 3 µs 1 0 1 1 fXX 512 25 6 µs 40 7 µs 1 1 0 0 Setting prohibited 1 1 0 1 Setting prohibited 1 1 1 0 Setting prohibited 1 1 1 1 TM0 overflow signal Note Only in the V850 SB1 Cautions 1 W...

Page 240: ...erating mode of 8 bit counter n TMn 3 Selects the individual mode or cascade connection mode 4 Sets the state of the timer output flip flop 5 Controls the timer flip flop or selects the active level in the PWM free running mode 6 Controls timer output TMCn is set by an 8 bit or 1 bit memory manipulation instruction RESET input sets these registers to 04H although the state of hardware is initializ...

Page 241: ...ode connection to lower timer LVSm LVRm Setting state of timer output flip flop 0 0 Not change 0 1 Reset timer output flip flop to 0 1 0 Set timer output flip flop to 1 1 1 Setting prohibited Other than PWM free running mode TMCn6 0 PWM free running mode TMCn6 1 TMCm1 Control of timer F F Selection of active level 0 Disable inversion operation Active high 1 Enable inversion operation Active low TO...

Page 242: ... the TCLn3 bit of timer clock selection register n1 TCLn1 n 2 to 7 Setting method 1 Set each register TCLn0 TCLn1 Select the count clock CRn0 Compare value TMCn Selects the clear and start mode when TMn and CRn0 match TMCn 0000xx11B x is don t care 2 When TCEn 1 is set counting starts 3 When the values of TMn and CRn0 match INTTMn is generated TMn is cleared to 00H 4 Then INTTMn is repeatedly gene...

Page 243: ...eration 2 3 When CRn0 00H Remark n 2 to 7 m 2 to 5 When CRn0 FFH 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Count clock TMn CRn0 TCEn INTTMn TOm Interrupt acknowledgment Interval time t Interrupt acknowledgment Remark n 2 to 7 m 2 to 5 Count clock CRn0 TCEn INTTMn TOm TMn 00H 00H 00H 00H 00H Interval time t ...

Page 244: ...on 3 3 Operated by CRn0 transition M N CRn0 transition TMn overflows since M N 00H 00H M M N N FFH 00H M Count clock TMn CRn0 TCEn INTTMn TOm Remark n 2 to 7 m 2 to 5 Operated by CRn0 transition M N CRn0 transition N 1 01H 00H 00H M N N M 1 01H N M Count clock TMn CRn0 TCEn INTTMn TOm Remark n 2 to 7 m 2 to 5 ...

Page 245: ...s incremented The edge setting can be selected as either the rising or falling edge If the total of TMn and the value of 8 bit compare register n CRn0 match TMn is cleared to 0 and an interrupt request signal INTTMn is generated INTTMn is generated each time the TMn value matches the CRn0 value Remark n 2 to 5 Figure 7 33 Timing of External Event Counter Operation with Rising Edge Specified TIn TM...

Page 246: ...Clear and start mode when TMn and CRn0 match LVSn LVRn Setting State of Timer Output Flip Flop 1 0 High level output 0 1 Low level output Inversion of timer output flip flop enabled Timer output enabled TOEn 1 2 When TCEn 1 is set the counter starts operating 3 If the values of TMn and CRn0 match the timer output flip flop inverts Also INTTMn is generated and TMn is cleared to 00H 4 Then the timer...

Page 247: ...WM mode Remark n 2 to 5 1 Basic operation of the PWM output Setting method 1 Set the port latch and port mode register n to 0 2 Set the active level width in 8 bit compare register n CRn0 3 Select the count clock using timer clock selection register n0 n1 TCLn0 TCLn1 4 Set the active level in TMCn1 bit of TMCn 5 If TCEn bit of TMCn is set to 1 counting starts When counting stops set TCEn to 0 PWM ...

Page 248: ...1H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N t When CRn0 00H Count clock TMn CRn0 TCEn INTTMn TOn Inactive level Inactive level 00H 01H FFH 00H 01H 02H N N 1 N 2 FFH 00H 01H 02H M 00H 00H t When CRn0 FFH Count clock TMn CRn0 TCEn INTTMn TOn Inactive level Inactive level Active level Active level Inactive level 00H 01H FFH 00H 01H 02H N N 1 N 2 FFH 00H 01H 02H M 00H FFH t Remarks 1 PWM frequenc...

Page 249: ...transition N M M 1 M N M H M 2 02H 01H 00H FFH M 1 M M 2 When the CRn0 value changes from N to M after TMn overflows INTTMn N 1 02H 01H 00H FFH N N 2 TMn CRn0 TCEn TOn Count clock CRn0 transition N M N 1 N N M H N 2 02H 01H 00H FFH M 1 M M 2 03H N When the CRn0 value changes from N to M within two clocks 00H 01H immediately after TMn overflows INTTMn N 1 02H 01H 00H FFH N N 2 TMn CRn0 TCEn TOn Cou...

Page 250: ...od TM2 TM3 cascade connection 1 Setting registers TCL20 TCL21 Select the count clock for TM2 setting not necessary for TM3 because of cascade connection CR20 CR30 Compare value 00H to FFH can be set for compare values TMC2 Selects clear start mode on a match of TM2 and CR2 x don t care TM2 TMC2 0000xxx0B TM3 TMC3 0001xxx0B 2 Set the TCE3 bit of TMC3 to 1 After that set the TCE2 bit of TMC2 to 1 to...

Page 251: ...low Figure 7 37 Cascade Connection Mode with 16 Bit Resolution N 1 N 00H 01H TMn Count clock Enable operation starting count 00H FFH FFH 01H 00H FFH 00H 00H N 01H 00H A 00H TMn 1 01H M M 1 02H 00H 00H B CRn0 N CR n 1 0 M TCEn TCEn 1 INTTMn TOm Interval time Operation stopped Interrupt generation Level inverted Counter cleared Remark n 2 4 6 m 2 4 ...

Page 252: ...nting starts again from 0 Consequently when the value after CRn0 changes M is less than the value before the change N and less than the count value of the TMn register the timer must restart after CRn0 changes n 2 to 5 Figure 7 39 Timing After Compare Register Changes During Timer Count Operation TMn count value N Count pulse CRn0 X 1 X FFH 00H 01H 02H M Remarks 1 N X M 2 n 2 to 7 Caution Except w...

Page 253: ... fW 210 fW 211 fW 29 fXT 4 11 bit prescaler Clear Clear INTWTN INTWTNI WTNM0 WTNM1 WTNM2 WTNM3 WTNM4 WTNM5 WTNM6 WTNM7 Watch timer clock selection register WTNCS WTNCS0 WTNCS1 Watch timer high speed clock selection register WTNHC WTNCS2 5 bit counter fW Selector Selector Selector Selector Caution The WTNHC register is available only in the B versions of the V850 SB1 µ µ µ µPD703036H 703036HY 70303...

Page 254: ...7 µs 26 1 fW 1 95 ms 27 1 fW 3 91 ms 28 1 fW 7 81 ms 29 1 fW 15 6 ms 210 1 fW 31 2 ms 211 1 fW 62 4 ms Remark fW Watch timer clock frequency 8 2 Configuration The watch timer includes the following hardware Table 8 2 Configuration of Watch Timer Item Configuration Counter 5 bits 1 Prescaler 11 bits 1 Control registers Watch timer mode control register WTNM Watch timer high speed clock selection re...

Page 255: ...ts the set time of the watch flag WTNM is set by an 8 bit or 1 bit memory manipulation instruction RESET input clears WTNM to 00H After reset 00H R W Address FFFFF360H 7 6 5 4 3 2 1 0 WTNM WTNM7 WTNM6 WTNM5 WTNM4 WTNM3 WTNM2 WTNM1 WTNM0 WTNM6 WTNM5 WTNM4 Selection interval time of prescaler 0 0 0 24 fW 488 µs 0 0 1 25 fW 977 µs 0 1 0 26 fW 1 95 ms 0 1 1 27 fW 3 91 ms 1 0 0 28 fW 7 81 ms 1 0 1 29 f...

Page 256: ...NM7 bit of the WTNM register and the WTNCS1 and WTNCS0 bits of the watch timer clock selection register WTNCS WTNHC is set using an 8 bit memory manipulation instruction RESET input clears WTNHC to 00H 0 WTNHC 0 0 0 0 0 0 WTNCS2 After reset 00H R W Address FFFFF366H Caution The WTNHC register is available only in the B versions of the V850 SB1 µPD703036H 703036HY 703037H 703037HY 70F3036H 70F3036H...

Page 257: ...fXX 27 fXT subclock fXX 3 26 fXX 28 Setting prohibited Setting prohibited fXX 3 27 fXX 29 fXX 32 26 Setting prohibited Other than above WTNCS2Note 0 0 0 0 0 0 0 0 1 Selection of count clock 4 194 MHz 6 291 MHz 8 388 MHz 12 582 MHz 16 777 MHz 18 874 MHz Main clock frequency WTNCS 0 0 0 0 0 WTNCS1 WTNCS0 WTNCS1 0 0 0 0 1 1 1 1 0 WTNCS0 0 0 1 1 0 0 1 1 1 WTNM7 0 1 0 1 0 1 0 1 0 After reset 00H R W Ad...

Page 258: ... up to 15 6 ms may occur The interval timer can be cleared by setting the WTNM0 bit to 0 However because the 5 bit counter is cleared at the same time an error of up to 0 5 seconds may occur when the watch timer overflows INTWTN 8 4 2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set ...

Page 259: ...al timer interrupt INTWTNI nT nT Remark fW Watch timer clock frequency fW 32 768 kHz n Interval timer operation count 8 4 3 Cautions It takes some time to generate the first watch timer interrupt request INTWTN after operation is enabled WRNM1 and WTNM0 bits of WTNM register 1 Figure 8 3 Watch Timer Interrupt Request INTWTN Generation Interrupt Period 0 5 s It takes 0 515625 s to generate the firs...

Page 260: ...er WDTM to select the watchdog timer mode or the interval timer mode Figure 9 1 Block Diagram of Watchdog Timer Internal bus OSTS0 OSTS1 OSTS2 OSTS WDTM4 RUN WDTM WDCS WDCS0 WDCS1 WDCS2 3 INTWDTNote 1 INTWDTMNote 2 3 Output controller Prescaler Selector fXX 222 fXX 210 fXX 220 fXX 219 fXX 218 fXX 217 fXX 216 fXX 215 fXX 214 RUN Clear OSC Selector Notes 1 In watchdog timer mode 2 In interval timer ...

Page 261: ... 3 ms 215 fXX 1 6 ms 2 6 ms 216 fXX 3 3 ms 5 2 ms 217 fXX 6 6 ms 10 4 ms 218 fXX 13 1 ms 20 8 ms 219 fXX 26 2 ms 41 6 ms 220 fXX 52 4 ms 83 3 ms 222 fXX 209 7 ms 333 4 ms Note Only in the V850 SB1 2 Interval timer mode Interrupts are generated at a preset time interval Table 9 2 Interval Time of Interval Timer Interval Time Clock fXX 20 MHzNote fXX 12 58 MHz 214 fXX 819 2 µs 1 3 ms 215 fXX 1 6 ms ...

Page 262: ...ster WDCS Watchdog timer mode register WDTM 1 Oscillation stabilization time selection register OSTS This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until the oscillation is stable OSTS is set by an 8 bit memory manipulation instruction RESET input sets OSTS to 04H After reset 04H R W Address FFFFF380H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OS...

Page 263: ...ter reset 00H R W Address FFFFF382H 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 Watchdog timer interval timer overflow time fXX WDCS2 WDCS1 WDCS0 Clock 20 MHzNote 12 58 MHz 0 0 0 214 fXX 819 2 µs 1 3 ms 0 0 1 215 fXX 1 6 ms 2 6 ms 0 1 0 216 fXX 3 3 ms 5 2 ms 0 1 1 217 fXX 6 6 ms 10 4 ms 1 0 0 218 fXX 13 1 ms 20 8 ms 1 0 1 219 fXX 26 2 ms 41 6 ms 1 1 0 220 fXX 52 4 ms 83 3 ms 1 1 1 222 fXX 209...

Page 264: ...ount 1 Clear count and start counting WDTM4 Operating mode selection for the watchdog timerNote 2 0 Interval timer mode If an overflow occurs the maskable interrupt INTWDTM is generated 1 Watchdog timer mode 1 If an overflow occurs the non maskable interrupt INTWDT is generated Notes 1 Once RUN is set 1 the register cannot be cleared 0 by software Therefore when counting starts counting cannot be ...

Page 265: ...dog timer stops running in the IDLE mode and STOP mode Consequently set RUN to 1 and clear the watchdog timer before entering the IDLE mode or STOP mode Do not set the watchdog timer when operating the HALT mode since the watchdog timer running in HALT mode Cautions 1 The actual inadvertent program loop detection time may be up to 2 10 fXX seconds less than the set time 2 When the subclock is sele...

Page 266: ...n the IDLE mode and STOP mode Therefore before entering the IDLE mode STOP mode set the RUN bit of the WDTM register to 1 and clear the interval timer Then set the IDLE mode STOP mode Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 selecting the watchdog timer mode the interval timer mode is not entered as long as RESET is not input 2 The interval time immediately after being set by WDTM may be up...

Page 267: ...0H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fXX OSTS2 OSTS1 OSTS0 Clock 20 MHzNote 12 58 MHz 0 0 0 214 fXX 819 2 µs 1 3 ms 0 0 1 216 fXX 3 3 ms 5 2 ms 0 1 0 217 fXX 6 6 ms 10 4 ms 0 1 1 218 fXX 13 1 ms 20 8 ms 1 0 0 219 fXX after reset 26 2 ms 41 6 ms Other than above Setting prohibited Note Only in the V850 SB1 Caution The wait time at the release ...

Page 268: ...ial I O CSI0 to CSI3 CSIn n 0 to 3 has the following two modes 1 Operation stop mode This mode is used when serial transfers are not performed 2 3 wire serial I O mode fixed to MSB first This is an 8 bit data transfer mode using three lines a serial clock line SCKn serial output line SOn and serial input line SIn Since simultaneous transmit and receive operations are enabled in 3 wire serial I O m...

Page 269: ...ws When n 0 or 3 TM2 When n 1 or 2 TM3 1 Serial I O shift registers 0 to 3 SIO0 to SIO3 SIOn is an 8 bit register that performs parallel serial conversion and serial transmission reception shift operations synchronized with the serial clock SIOn is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIEn of serial operation mode register n CSIMn a serial operation can be starte...

Page 270: ...ration mode registers 0 to 3 CSIM0 to CSIM3 The CSISn register is used to set serial interface channel n s serial clock The CSISn register can be set by an 8 bit memory manipulation instruction RESET input clears the CSISn register to 00H The CSIMn register is used to enable or disable serial interface channel n s serial clock operation modes and specific operations The CSIMn register can be set b...

Page 271: ...tput 0 Transmit receive mode SIOn write Normal output 1 Receive only mode SIOn read Port function SCLn2 SCLn1 SCLn0 Clock selection 0 0 0 External clock input SCKn 0 0 1 at n 0 3 Output of TO2 at n 1 2 Output of TO3 0 1 0 fXX 8 0 1 1 fXX 16 1 0 0 Setting prohibited 1 0 1 Setting prohibited 1 1 0 fXX 32 1 1 1 fXX 64 Notes 1 The SIn SOn and SCKn pins are used as port function pins when CSIEn 0 SIOn ...

Page 272: ... SCKn pin are also used as I O ports they can be used as normal I O ports as well a Register settings Operation stop mode is set via the CSIEn bit of serial operation mode register n CSIMn Figure 10 2 CSIMn Setting Operation Stop Mode After reset 00H R W Address CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H CSIM3 FFFFF2D2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 to 3 SIOn opera...

Page 273: ... FFFFF2D2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 to 3 SIOn operation enable disable specification CSIEn Shift register operation Serial counter Port 1 Operation enable Count operation enable Serial function port function Transfer operation mode flag MODEn Operation mode Transfer start trigger SOn output 0 Transmit receive mode Write to SIOn Normal output 1 Receive only mode Rea...

Page 274: ...4 DI3 DI2 DI1 DI0 INTCSIn Serial clock 1 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 3 4 5 6 7 8 Transfer completion Transfer starts in synchronization with the serial clock s falling edge c Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I O shift register n SIOn The SIOn operation control bit CSIEn 1 After an 8 bit ...

Page 275: ...en serial transfers are not performed It can therefore be used to reduce power consumption 2 I 2 C bus mode multimaster support This mode is used for 8 bit data transfers with several devices via two lines a serial clock SCLn line and a serial data bus SDAn line This mode complies with the I 2 C bus format and the master device can output start condition data and stop condition data to the slave d...

Page 276: ... time correction circuit ACK detector Wakeup controller ACK detector Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller Prescaler INTIICn fXX TMx output LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn Start condition detector Internal bus CLDn DADn SMCn DFCn CLn1 CLn0 CLXn IICCEn1 II...

Page 277: ...ation example is shown below Figure 10 6 Serial Bus Configuration Example Using I 2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N Master CPU1 Slave CPU1 Address 1 Serial data bus Serial clock Master CPU2 Slave CPU2 Address 2 ...

Page 278: ...read operations to IICn are used to control the actual transmit and receive operations IICn is set by an 8 bit memory manipulation instruction RESET input clears IIC0 and IIC1 to 00H 2 Slave address registers 0 and 1 SVA0 SVA1 SVAn sets local addresses when in slave mode SVAn is set by an 8 bit memory manipulation instruction n 0 1 RESET input clears SVA0 and SVA1 to 00H 3 SO latch The SO latch is...

Page 279: ... n 0 1 2 WTIMn bit Bit 3 of IIC control register n IICCn SPIEn bit Bit 4 of IIC control register n IICCn 8 Serial clock controller In master mode this circuit generates the clock output via the SCLn pin from a sampling clock n 0 1 9 Serial clock wait controller This circuit controls the wait timing 10 ACK output circuit stop condition detector start condition detector and ACK detector These circui...

Page 280: ...ers 0 1 IICC0 IICC1 IICCn is used to enable disable I 2 C operations set wait timing and set other I 2 C operations IICCn can be set by an 8 bit or 1 bit memory manipulation instruction n 0 1 RESET input clears IICCn to 00H Caution In I 2 C0 I 2 C1 bus mode set the port 1 mode register PM1 port 2 mode register PM2 port 1 function register PF1 and port 2 function register PF2 as follows In addition...

Page 281: ... locally irrelevant extension code has been received The SCLn and SDAn lines are set to high impedance The following flags are cleared STDn ACKDn TRCn COIn EXCn MSTSn STTn SPTn The standby mode following exit from communications remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode An address match or extension co...

Page 282: ... After input of eight clocks the clock is set to low level and wait is set for the master device 1 Interrupt request is generated at the ninth clock s falling edge Master mode After output of nine clocks clock output is set to low level and wait is set Slave mode After input of nine clocks the clock is set to low level and wait is set for the master device This bit s setting is invalid during an a...

Page 283: ...hen bus is not used This trigger functions as a start condition reserve flag When set it releases the bus and then automatically generates a start condition In the wait state when master device Generate a restart condition after releasing the wait Cautions concerning set timing For master reception Cannot be set during transfer Can be set only when ACKEn has been set to 0 and slave has been notifi...

Page 284: ...n is set during the wait period that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock When a ninth clock must be output WTIMn should be changed from 0 to 1 during the wait period following output of eight clocks and SPTn should be set during the wait period that follows output of the ninth clock Condition for clearing SPTn ...

Page 285: ...setting MSTSn 1 When a stop condition is detected When ALDn 1 Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is generated ALDn Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arbitration result was a loss MSTSn is cleared Condition for clearing A...

Page 286: ...eceive status 0 Receive status other than transmit status The SDAn line is set to high impedance 1 Transmit status The value in the SO latch is enabled for output to the SDAn line valid starting at the falling edge of the first byte s ninth clock Condition for clearing TRCn 0 Condition for setting TRCn 1 When a stop condition is detected Cleared by LRELn 1 When IICEn changes from 1 to 0 Cleared by...

Page 287: ...for clearing STDn 0 Condition for setting STDn 1 When a stop condition is detected At the rising edge of the next byte s first clock following address transfer Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is detected SPDn Detection of stop condition 0 Stop condition was not detected 1 Stop condition was detected The master device s communication is t...

Page 288: ...SCLn line was detected at high level Condition for clearing CLDn 0 Condition for setting CLDn 1 When the SCLn line is at low level When IICEn 0 When RESET is input When the SCLn line is at high level DADn Detection of SDAn line level valid only when IICEn 1 0 SDAn line was detected at low level 1 SDAn line was detected at high level Condition for clearing DADn 0 Condition for setting DADn 1 When t...

Page 289: ...n Set the IICCEn1 and IICCEn0 bits in combination with the SMCn CLn1 and CLn0 bits of IIC clock selection register n IICCLn and the CLXn bit of IIC function expansion register n IICXn see 10 3 2 6 I 2 Cn transfer clock setting method n 0 1 RESET input clears these registers to 00H 6 I 2 Cn transfer clock setting method The I 2 Cn transfer clock frequency fSCL is calculated using the following expr...

Page 290: ...to 4 19 MHz x x 0 1 0 x fXX 24 4 0 MHz to 8 38 MHz x x 0 1 1 0 fXX 48 8 0 MHz to 16 67 MHz 0 1 0 1 1 1 fXX 36 12 0 MHz to 13 4 MHz 1 0 0 1 1 1 fXX 54 16 0 MHz to 20 0 MHzNote n 0 TM2 output 18 TM2 setting 0 0 0 1 1 1 n 1 TM3 output 18 TM3 setting High speed mode SMCn 1 x x 0 0 0 0 fXX 44 2 0 MHz to 4 19 MHz x x 0 0 0 1 fXX 86 4 19 MHz to 8 38 MHz x x 0 0 1 0 fXX 172 8 38 MHz to 16 67 MHz 0 1 0 0 1...

Page 291: ...ode functions 1 Pin configuration The serial clock pin SCLn and serial data bus pin SDAn are configured as follows n 0 1 SCLn This pin is used for serial clock input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input SDAn This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices I...

Page 292: ...the start condition data and stop condition output via the I 2 C bus s serial data bus is shown below Figure 10 8 I 2 C Bus s Serial Data Transfer Timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 SCL SDA Start condition Address R W ACK Data Data Stop condition ACK ACK The master device outputs the start condition slave address and stop condition The acknowledge signal ACK can be output by either the master...

Page 293: ...1 2 Address The 7 bits of data that follow the start condition are defined as an address An address is a 7 bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines Therefore each slave device connected via the bus lines must have a unique address The slave devices include hardware that detects the start condition and checks w...

Page 294: ... 7 bit address data the master device sends 1 bit that specifies the transfer direction When this transfer direction specification bit has a value of 0 it indicates that the master device is transmitting data to a slave device When the transfer direction specification bit has a value of 1 it indicates that the master device is receiving data from a slave device Figure 10 11 Transfer Direction Spec...

Page 295: ...a bits causes bit 3 TRCn of IIC status register n IICSn to be set When this TRCn bit s value is 0 it indicates receive mode Therefore ACKEn should be set to 1 n 0 1 When the slave device is receiving when TRCn 0 if the slave device does not need to receive any more data after receiving several bytes setting ACKEn to 0 will prevent the master device from starting transmission of the subsequent data...

Page 296: ...master device outputs to the slave device when serial transfer has been completed The slave device includes hardware that detects stop conditions Figure 10 13 Stop Condition H SCL SDA Remark n 0 1 A stop condition is generated when bit 0 SPTn of IIC control register n IICCn is set to 1 When the stop condition is detected bit 0 SPDn of IIC status register n IICSn is set to 1 and INTIICn is generate...

Page 297: ...ed for both the master and slave devices the next data transfer can begin n 0 1 Figure 10 14 Wait Signal 1 2 a When master device has a nine clock wait and slave device has an eight clock wait master transmission slave reception and ACKEn 1 SCL 6 SDA 7 8 9 1 2 3 SCL IIC0 6 H 7 8 1 2 3 D2 D1 D0 ACK D7 D6 D5 9 IIC0 SCL ACKE Master Master returns to high impedance but slave is in wait state low level...

Page 298: ...t according to previously set ACKE value Transfer lines Remarks 1 ACKEn Bit 2 of IIC control register n IICCn WRELn Bit 5 of IIC control register n IICCn 2 n 0 1 A wait may be automatically generated depending on the setting for bit 3 WTIMn of IIC control register n IICCn n 0 1 Normally when bit 5 WRELn of IICCn is set to 1 or when FFH is written to IIC shift register n IICn the wait status is can...

Page 299: ...a Data Stop normal transmission reception 1 When WTIMn 0 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXX000B 3 IICSn 10XXX000B WTIMn 0 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 10XXX110B 2 IICSn 10XXX10...

Page 300: ...000B WTIMn 1 3 IICSn 10XXXX00B WTIMn 0 4 IICSn 10XXX110B WTIMn 0 5 IICSn 10XXX000B WTIMn 1 6 IICSn 10XXXX00B 7 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 STTn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXXX00B 3 IICSn 10XXX110B 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark...

Page 301: ... 2 3 4 5 1 IICSn 1010X110B 2 IICSn 1010X000B 3 IICSn 1010X000B WTIMn 1 4 IICSn 1010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1010X110B 2 IICSn 1010X100B 3 IICSn 1010XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 302: ... AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X100B 3 IICSn 0001XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 ...

Page 303: ...ICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0001X110B 4 IICSn 0001XX00B 5 IICSn 00000001B Remark Always generated Genera...

Page 304: ...10B 2 IICSn 0001X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0010X010B 4 IICSn 0010X110B 5 IICSn 0010XX00B 6 IICSn 00000001B Remark Alway...

Page 305: ... AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated G...

Page 306: ... D7 to D0 AK SP 1 2 3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 307: ...10B 2 IICSn 0010X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0001X110B 5 IICSn 0001XX00B 6 IICSn 00000001B Remark Always generat...

Page 308: ...0010X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 7 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0010X010B 5 IICSn 0010X110B 6 IICSn 0010XX00B 7 IICSn 00000001B Rema...

Page 309: ...3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 00000X10B 5 IICSn 00000001B Remark Always ge...

Page 310: ...sion of slave address data 1 When WTIMn 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn is read during interrupt servicing 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn i...

Page 311: ...is read during interrupt servicing 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated G...

Page 312: ...P 1 2 1 IICSn 01000110B Example when ALDn is read during interrupt servicing 2 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 b When arbitration loss occurs during transmission of extension code ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 2 IICSn 00000001B ...

Page 313: ...ICSn 10001110B 2 IICSn 01000000B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 1 IICSn 10001110B 2 IICSn 01000100B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 ...

Page 314: ...n 01000110B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 2 Extension code ST AD6 to AD0 RW AK D7 to Dn ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 1 IICSn 1000X110B 2 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 3 IICSn 00000001B Re...

Page 315: ...ed only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 f When arbitration loss occurs due to low level data when attempting to generate a restart condition When WTIMn 1 STTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000100B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B Remark Always generated Generated o...

Page 316: ... 3 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 h When arbitration loss occurs due to low level data when attempting to generate a stop condition When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000000B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B ...

Page 317: ... of slave address register n SVAn neither INTIICn nor a wait occurs Remarks 1 The numbers in the table indicate the number of the serial clock signals Interrupt requests and wait control are both synchronized with the falling edge of these clock signals 2 n 0 1 1 During address transmission reception Slave device operation Interrupt and wait timing are determined regardless of the WTIMn bit Master...

Page 318: ...ion error is judged as having occurred when the compared data values do not match n 0 1 10 3 9 Extension code 1 When the higher 4 bits of the receive address are either 0000 or 1111 the extension code flag EXCn is set for extension code reception and an interrupt request INTIICn is issued at the falling edge of the eighth clock n 0 1 The local address stored in slave address register n SVAn is not...

Page 319: ...lled arbitration n 0 1 When one of the master devices loses in arbitration an arbitration loss flag ALDn in IIC status register n IICSn is set at the timing by which the arbitration loss occurred and the SCLn and SDAn lines are both set for high impedance which releases the bus n 0 1 The arbitration loss is detected based on the timing of the next interrupt request the eighth or ninth clock when a...

Page 320: ...ansfer Note 1 When SCLn is at low level while attempting to output a restart condition Notes 1 When WTIMn bit 3 of the IIC control register n IICCn 1 an interrupt request occurs at the falling edge of the ninth clock When WTIMn 0 and the extension code s slave address is received an interrupt request occurs at the falling edge of the eighth clock n 0 1 2 When there is a possibility that arbitratio...

Page 321: ...ected when a stop condition is detected writing to IIC shift register n IICn causes the master s address transfer to start At this point bit 4 SPIEn of IICCn should be set n 0 1 When STTn has been set the operation mode as start condition or as communication reservation is determined according to the bus status n 0 1 If the bus has been released a start condition is generated If the bus has not be...

Page 322: ...tership IICn IIC shift register n STTn Bit 1 of IIC control register n IICCn STDn Bit 1 of IIC status register n IICSn SPDn Bit 0 of IIC status register n IICSn Remark n 0 1 Communication reservations are acknowledged at the following timing After bit 1 STDn of IIC status register n IICSn is set to 1 a communication reservation can be made by setting bit 1 STTn of IIC control register n IICCn to 1...

Page 323: ... MSTSn 0 Communication reservation Note Generate start condition Sets STT flag communication reservation Gets wait period set by software see Table 10 7 Confirmation of communication reservation Clear user flag IICn write operation Defines that communication reservation is in effect defines and sets user flag to any part of RAM Note The communication reservation operation executes a write to IIC s...

Page 324: ...irst generate a stop condition to release the bus then perform master device communication When using multiple masters it is not possible to perform master device communication when the bus has not been released when a stop condition has not been detected Use the following sequence for generating a stop condition a Set IIC clock selection register n IICCLn b Set bit 7 IICEn of IIC control register...

Page 325: ...n H IICEn SPIEn WTIMn 1 Start IICn write transfer Start IICn write transfer WRELn 1 Start reception Generate stop condition no slave with matching address Generate restart condition or stop condition START Data processing Data processing ACKEn 0 No Yes No No No No No No Yes Yes Yes Yes Yes INTIICn 1 WTIMn 0 ACKEn 1 INTIICn 1 Transfer completed INTIICn 1 ACKDn 1 TRCn 1 INTIICn 1 ACKDn 1 Stop condit...

Page 326: ...ICCn H IICEn 1 WRELn 1 Start reception START ACKEn 0 Data processing Data processing LRELn 1 No Yes No No No receive No No No No Yes No Yes Yes Yes transmit Yes Yes Yes WTIMn 0 ACKEn 1 INTIICn 1 Yes Communicate Transfer completed INTIICn 1 WTIMn 1 Start IICn write transfer INTIICn 1 EXCn 1 COIn 1 TRCn 1 ACKDn 1 End START or STOP STOP stop condition detection Remark n 0 1 ...

Page 327: ...vice transmits the TRCn bit bit 3 of IIC status register n IICSn that specifies the data transfer direction and then starts serial communication with the slave device The shift operation of IIC bus shift register n IICn is synchronized with the falling edge of the serial clock SCLn The transmit data is transferred to the SO latch and is output MSB first via the SDAn pin Data input via the SDAn pin...

Page 328: ...H H L L L L H H H L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4 D5 D6 D7 IICn address IICn data IICn FFH Transmit Start condition Receive When EXC 1 Note Note Note To cancel slave wait write...

Page 329: ...L L L L L H H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 IICn data IICn FFH Note IICn FFH Note IICn data Transmit Receive Note Note Note To cancel slave wait write FFH to IICn ...

Page 330: ... ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn data IICn address IICn FFH Note IICn FFH Note Stop condition Start condition Transmit Note Note When SPIEn 1 Receive When SPIEn 1 Note To cancel slave ...

Page 331: ... SPDn WTIMn H H L L H H L ACKEn MSTSn STTn L L SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2 D5 D6 D7 IICn address IICn FFH Note Note IICn data Start condition Note To cancel master wait write FFH to IICn ...

Page 332: ... L L L H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Note Note Receive Transmit IICn data IICn data IICn FFH Note IICn FFH Note Note To cancel master wait write FFH to I...

Page 333: ...H L L L H H ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn address IICn FFH Note Note IICn data Stop condition Start condition When SPIEn 1 N ACK When SPIEn 1 Note To cancel master wait write FFH to ...

Page 334: ...de This mode is used when serial transfers are not performed It can therefore be used to reduce power consumption 2 I 2 C bus mode multimaster support This mode is used for 8 bit data transfers with several devices via two lines a serial clock SCLn line and a serial data bus SDAn line This mode complies with the I 2 C bus format and the master device can output start condition data and stop condit...

Page 335: ...condition generator ACK output circuit Wakeup controller ACK detector Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller Prescaler INTIICn fxx TMx output LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn Start condition detector Internal bus CLDn DADn SMCn DFCn CLn1 CLn0 CLXn IIC clock...

Page 336: ...ation example is shown below Figure 10 24 Serial Bus Configuration Example Using I 2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N Master CPU1 Slave CPU1 Address 1 Serial data bus Serial clock Master CPU2 Slave CPU2 Address 2 ...

Page 337: ...smission and reception n 0 1 Write and read operations to IICn are used to control the actual transmit and receive operations IICn is set by an 8 bit memory manipulation instruction RESET input clears IIC0 and IIC1 to 00H 2 Slave address registers 0 and 1 SVA0 SVA1 SVAn sets local addresses when in slave mode SVAn is set by an 8 bit memory manipulation instruction n 0 1 RESET input clears SVA0 and...

Page 338: ...ition detector and ACK detector These circuits are used to output and detect various control signals 11 Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock 12 Start condition generator This circuit generates a start condition when the STTn bit is set However in the communication reservation disabled status IICRSVn 1 ...

Page 339: ...IC control registers 0 1 IICC0 IICC1 IICCn is used to enable disable I 2 C operations set wait timing and set other I 2 C operations IICCn can be set by an 8 bit or 1 bit memory manipulation instruction n 0 1 RESET input clears IICCn to 00H Caution In I 2 C0 I 2 C1 bus mode set the port 1 mode register PM1 port 2 mode register PM2 port 1 function register PF1 and port 2 function register PF2 as fo...

Page 340: ...locally irrelevant extension code has been received The SCLn and SDAn lines are set to high impedance The following flags are cleared STDn ACKDn TRCn COIn EXCn MSTSn STTn SPTn The standby mode following exit from communications remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode An address match or extension cod...

Page 341: ... mode After input of eight clocks the clock is set to low level and wait is set for master device 1 Interrupt request is generated at the ninth clock s falling edge Master mode After output of nine clocks clock output is set to low level and wait is set Slave mode After input of nine clocks the clock is set to low level and wait is set for master device This bit s setting is invalid during an addr...

Page 342: ...ter the bus is released When communication reservation function is disabled IICRSVn 1 The STCFn bit is set No start condition is generated In the wait state when master device Generates a restart condition after releasing the wait Cautions concerning set timing For master reception Cannot be set during transfer Can be set only when ACKEn has been set to 0 and slave has been notified of final recep...

Page 343: ...the wait period that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock When a ninth clock must be output WTIMn should be changed from 0 to 1 during the wait period following output of eight clocks and SPTn should be set during the wait period that follows output of the ninth clock Condition for clearing SPTn 0 Condition for ...

Page 344: ...setting MSTSn 1 When a stop condition is detected When ALDn 1 Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is generated ALDn Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arbitration result was a loss MSTSn is cleared Condition for clearing A...

Page 345: ...t receive status 0 Receive status other than transmit status The SDAn line is set for high impedance 1 Transmit status The value in the SO latch is enabled for output to the SDAn line valid starting at the falling edge of the first byte s ninth clock Condition for clearing TRCn 0 Condition for setting TRCn 1 When a stop condition is detected Cleared by LRELn 1 When IICEn changes from 1 to 0 Cleare...

Page 346: ...for clearing STDn 0 Condition for setting STDn 1 When a stop condition is detected At the rising edge of the next byte s first clock following address transfer Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is detected SPDn Detection of stop condition 0 Stop condition was not detected 1 Stop condition was detected The master device s communication is t...

Page 347: ... can be read n 0 RESET input clears IICFn to 00H When IICFn 00H these registers operate in the same way as the A versions 1 2 7 STCFn Condition for clearing STCFn 0 Clearing by setting STTn 1 RESET input Condition for setting STCFn 1 Clearing of STTn when communication reservation is disabled IICRSVn 1 STCFn 0 1 Generate start condition Clear STTn bit STTn bit clear IICFn n 0 1 6 IICBSYn 5 0 4 0 3...

Page 348: ...for setting IICRSVn 1 Setting by instruction IICRSVn 0 1 Enable communication reservation Disable communication reservation Communication reservation function disable bit Cautions 1 Write to the STCENn bit only when the operation is stopped IICEn 0 2 As the bus release status IICBSYn 0 is recognized immediately after I 2 C operation is enabled regardless of the actual bus status when STCENn 1 when...

Page 349: ...CLn line was detected at high level Condition for clearing CLDn 0 Condition for setting CLDn 1 When the SCLn line is at low level When IICEn 0 When RESET is input When the SCLn line is at high level DADn Detection of SDAn line level valid only when IICEn 1 0 SDAn line was detected at low level 1 SDAn line was detected at high level Condition for clearing DADn 0 Condition for setting DADn 1 When th...

Page 350: ... Set the IICCEn1 and IICCEn0 bits in combination with the SMCn CLn1 and CLn0 bits of IIC clock selection register n IICCLn and the CLXn bit of IIC function expansion register n IICXn see 10 4 2 7 I 2 Cn transfer clock setting method n 0 1 RESET input clears these registers to 00H 7 I 2 Cn transfer clock setting method The I 2 Cn transfer clock frequency fSCL is calculated using the following expre...

Page 351: ... 4 19 MHz x x 0 1 0 x fXX 24 4 0 MHz to 8 38 MHz x x 0 1 1 0 fXX 48 8 0 MHz to 16 67 MHz 0 1 0 1 1 1 fXX 36 12 0 MHz to 13 4 MHz 1 0 0 1 1 1 fXX 54 16 0 MHz to 20 0 MHzNote n 0 TM2 output 18 TM2 setting 0 0 0 1 1 1 n 1 TM3 output 18 TM3 setting High speed mode SMCn 1 x x 0 0 0 0 fXX 44 2 0 MHz to 4 19 MHz x x 0 0 0 1 fXX 86 4 19 MHz to 8 38 MHz x x 0 0 1 0 fXX 172 8 38 MHz to 16 67 MHz 0 1 0 0 1 1...

Page 352: ...ode functions 1 Pin configuration The serial clock pin SCLn and serial data bus pin SDAn are configured as follows n 0 1 SCLn This pin is used for serial clock input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input SDAn This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices I...

Page 353: ...the start condition data and stop condition output via the I 2 C bus s serial data bus is shown below Figure 10 26 I 2 C Bus s Serial Data Transfer Timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 SCL SDA Start condition Address R W ACK Data Data Stop condition ACK ACK The master device outputs the start condition slave address and stop condition The acknowledge signal ACK can be output by either the maste...

Page 354: ...2 Addresses The 7 bits of data that follow the start condition are defined as an address An address is a 7 bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines Therefore each slave device connected via the bus lines must have a unique address The slave devices include hardware that detects the start condition and checks w...

Page 355: ... 7 bit address data the master device sends 1 bit that specifies the transfer direction When this transfer direction specification bit has a value of 0 it indicates that the master device is transmitting data to a slave device When the transfer direction specification bit has a value of 1 it indicates that the master device is receiving data from a slave device Figure 10 29 Transfer Direction Spec...

Page 356: ... data was received When the receiving device sets the SDAn line to low level during the ninth clock the ACK signal becomes active normal receive response When bit 2 ACKEn of IIC control register n IICCn is set to 1 automatic ACK signal generation is enabled n 0 1 Transmission of the eighth bit following the 7 address data bits causes bit 3 TRCn of IIC status register n IICSn to be set When this TR...

Page 357: ... When 9 clock wait is selected ACK signal is automatically output at the falling edge of the SCLn s eighth clock if ACKEn has already been set to 1 5 Stop condition When the SCLn pin is at high level changing the SDAn pin from low level to high level generates a stop condition n 0 1 A stop condition is a signal that the master device outputs to the slave device when serial transfer has been comple...

Page 358: ... for both the master and slave devices the next data transfer can begin n 0 1 Figure 10 32 Wait Signal 1 2 a When master device has a nine clock wait and slave device has an eight clock wait master transmission slave reception and ACKEn 1 SCL 6 SDA 7 8 9 1 2 3 SCL IIC0 6 H 7 8 1 2 3 D2 D1 D0 ACK D7 D6 D5 9 IIC0 SCL ACKE Master Master returns to high impedance but slave is in wait state low level W...

Page 359: ...t according to previously set ACKE value Transfer lines Remarks 1 ACKEn Bit 2 of IIC control register n IICCn WRELn Bit 5 of IIC control register n IICCn 2 n 0 1 A wait may be automatically generated depending on the setting for bit 3 WTIMn of IIC control register n IICCn n 0 1 Normally when bit 5 WRELn of IICCn is set to 1 or when FFH is written to IIC shift register n IICn the wait status is can...

Page 360: ...a Data Stop normal transmission reception 1 When WTIMn 0 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXX000B 3 IICSn 10XXX000B WTIMn 0 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 10XXX110B 2 IICSn 10XXX10...

Page 361: ...000B WTIMn 1 3 IICSn 10XXXX00B WTIMn 0 4 IICSn 10XXX110B WTIMn 0 5 IICSn 10XXX000B WTIMn 1 6 IICSn 10XXXX00B 7 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 STTn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXXX00B 3 IICSn 10XXX110B 4 IICSn 10XXXX00B 5 IICSn 00000001B Remark...

Page 362: ... 2 3 4 5 1 IICSn 1010X110B 2 IICSn 1010X000B 3 IICSn 1010X000B WTIMn 1 4 IICSn 1010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1010X110B 2 IICSn 1010X100B 3 IICSn 1010XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 363: ... AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X100B 3 IICSn 0001XX00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 ...

Page 364: ...ICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0001X110B 4 IICSn 0001XX00B 5 IICSn 00000001B Remark Always generated Genera...

Page 365: ...10B 2 IICSn 0001X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 0010X010B 4 IICSn 0010X110B 5 IICSn 0010XX00B 6 IICSn 00000001B Remark Alway...

Page 366: ... AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001XX00B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated G...

Page 367: ... D7 to D0 AK SP 1 2 3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 ...

Page 368: ...10B 2 IICSn 0010X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0001X110B 5 IICSn 0001XX00B 6 IICSn 00000001B Remark Always generat...

Page 369: ...0010X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 7 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 0010X010B 5 IICSn 0010X110B 6 IICSn 0010XX00B 7 IICSn 00000001B Rema...

Page 370: ...3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0010X010B 2 IICSn 0010X110B 3 IICSn 0010XX00B 4 IICSn 00000X10B 5 IICSn 00000001B Remark Always ge...

Page 371: ...sion of slave address data 1 When WTIMn 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn is read during interrupt servicing 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn i...

Page 372: ...is read during interrupt servicing 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing 2 IICSn 0010X110B 3 IICSn 0010X100B 4 IICSn 0010XX00B 5 IICSn 00000001B Remark Always generated G...

Page 373: ...P 1 2 1 IICSn 01000110B Example when ALDn is read during interrupt servicing 2 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 b When arbitration loss occurs during transmission of extension code ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 1 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 2 IICSn 00000001B ...

Page 374: ...ICSn 10001110B 2 IICSn 01000000B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 1 IICSn 10001110B 2 IICSn 01000100B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 ...

Page 375: ...n 01000110B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 2 Extension code ST AD6 to AD0 RW AK D7 to Dn ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 1 IICSn 1000X110B 2 IICSn 0110X010B Example when ALDn is read during interrupt servicing IICCn s LRELn is set to 1 by software 3 IICSn 00000001B Re...

Page 376: ...ed only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 f When arbitration loss occurs due to low level data when attempting to generate a restart condition When WTIMn 1 STTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000100B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B Remark Always generated Generated o...

Page 377: ... 3 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 h When arbitration loss occurs due to low level data when attempting to generate a stop condition When WTIMn 1 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 1000X110B 2 IICSn 1000XX00B 3 IICSn 01000000B Example when ALDn is read during interrupt servicing 4 IICSn 00000001B ...

Page 378: ...slave address register n SVAn neither INTIICn nor a wait occurs Remarks 1 The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both synchronized with the falling edge of these clock signals 2 n 0 1 1 During address transmission reception Slave device operation Interrupt and wait timing are determined regardless of the WTIMn bit Ma...

Page 379: ...ssion error is judged as having occurred when the compared data values do not match n 0 1 10 4 9 Extension code 1 When the higher 4 bits of the receive address are either 0000 or 1111 the extension code flag EXCn is set for extension code reception and an interrupt request INTIICn is issued at the falling edge of the eighth clock n 0 1 The local address stored in slave address register n SVAn is n...

Page 380: ...f clocks is adjusted until the data differs This kind of operation is called arbitration n 0 1 When one of the master devices loses in arbitration an arbitration loss flag ALDn in IIC status register n IICSn is set via the timing by which the arbitration loss occurred and the SCLn and SDAn lines are both set for high impedance which releases the bus n 0 1 The arbitration loss is detected based on ...

Page 381: ... extension code transmission During data transmission During ACK signal transfer period after data reception When restart condition is detected during data transfer When stop condition is detected during data transfer When stop condition is output when SPIEn 1 Note 2 When data is at low level while attempting to output a restart condition At falling edge of eighth or ninth clock following byte tra...

Page 382: ...slave function is a function that generates an interrupt request INTIICn when a local address and extension code have been received This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match When a start condition is detected wakeup standby mode is set This wakeup standby mode is in effect while addresses are transmitted du...

Page 383: ...etected When the bus release is detected when a stop condition is detected writing to IIC shift register n IICn causes the master s address transfer to start At this point IICCn s bit 4 SPIEn should be set n 0 1 When STTn has been set the operation mode as start condition or as communication reservation is determined according to the bus status n 0 1 If the bus has been released a start condition ...

Page 384: ...s access IICn IIC shift register n STTn Bit 1 of IIC control register n IICCn STDn Bit 1 of IIC status register n IICSn SPDn Bit 0 of IIC status register n IICSn Remark n 0 1 Communication reservations are accepted via the following timing After bit 1 STDn of IIC status register n IICSn is set to 1 a communication reservation can be made by setting bit 1 STTn of IIC control register n IICCn to 1 b...

Page 385: ...MSTSn 0 Communication reservation Note Generate start condition Sets STT bit communication reservation Secures wait period set by software see Table 10 13 Confirmation of communication reservation Clear user flag IICn write operation Defines that communication reservation is in effect defines and sets user flag to any part of RAM Note The communication reservation operation executes a write to IIC...

Page 386: ...ect whether a start condition was generated or the request was rejected check the STCFn flag of the IICFn register Wait for the period shown in Table 10 14 using software since it takes the period to set the STCFn flag from when STTn 1 is set Table 10 14 Wait Time IICCEn1 IICCEn0 CLn1 CLn0 Wait Time X X 0 0 3 clocks X X 0 1 3 clocks X X 1 0 6 clocks 0 0 1 1 3 N 0 1 1 1 6 clocks 1 0 1 1 9 clocks Re...

Page 387: ...igure 10 38 Master Communication Start or Stop Flowchart DI EI Wait DI No Yes No Yes IICBSYn 0 Sets STTn bit IICn write operation Secures wait period by software see Table 10 14 SET1 STTn IICn XXH EI Master communication stop Bus communication status STCFn 0 Remark n 0 1 ...

Page 388: ...condition to release the bus and then perform master communication Use the following sequence for generating a stop condition 1 Set IIC clock selection register n IICCLn 2 Set the IICEn bit of IIC control register n IICCn 3 Set the SPTn bit of the IICCn register b When STCENn of IICFn register 1 Immediately after the I 2 C operation is enabled the bus released status IICBSYn 0 is recognized regard...

Page 389: ... 1 Start IICn write transfer WRELn 1 Start reception Generate stop condition SPTn 1 START Data processing Data processing ACKEn 0 No No Yes stop condition detection Yes start condition generation No No No No No restart No No Yes Yes Yes Yes Yes Yes INTIICn 1 WTIMn 0 ACKEn 1 INTIICn 1 Transfer complete Transfer complete INTIICn 1 TRCn 1 ACKDn 1 MSTSn 1 Yes No INTIICn 1 INTIICn 1 ACKDn 1 Communicati...

Page 390: ...ICFn register setting IICCn register initial setting IICCn XXH IICEn SPIEn WTIMn 1 STTn 1 Insert wait START No Yes IICBSYn 0 No Yes Start IICn write transfer Start IICn write transfer WTIMn 0 ACKEn 1 WRELn 1 Start reception Data processing Data processing ACKEn 0 SPTn 1 Generate stop condition No Yes address transfer complete Yes INTIICn 1 No Yes Yes INTIICn 1 No Yes INTIICn 1 No Yes ACKDn 1 No Re...

Page 391: ...En 1 WRELn 1 Start reception START ACKEn 0 Data processing Data processing LRELn 1 No Yes No No No receive STOP stop condition detection No No No No Yes No Yes Yes Yes transmit Yes START restart detection Yes Yes WTIMn 0 ACKEn 1 INTIICn 1 Yes Bus participates in communication Transfer completed INTIICn 1 WTIMn 1 Start IICn write transfer INTIICn 1 EXCn 1 COIn 1 TRCn 1 ACKDn 1 START or STOP End Rem...

Page 392: ... device transmits the TRCn bit bit 3 of IIC status register n IICSn that specifies the data transfer direction and then starts serial communication with the slave device IIC bus shift register n IICn s shift operation is synchronized with the falling edge of the serial clock SCLn The transmit data is transferred to the SO latch and is output MSB first via the SDAn pin Data input via the SDAn pin i...

Page 393: ...H H L L L L H H H L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4 D5 D6 D7 IICn address IICn data IICn FFH Transmit Start condition Receive When EXC 1 Note Note Note To cancel slave wait write...

Page 394: ...L L L L L H H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 IICn data IICn FFH Note IICn FFH Note IICn data Transmit Receive Note Note Note To cancel slave wait write FFH to IICn ...

Page 395: ... ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn data IICn address IICn FFH Note IICn FFH Note Stop condition Start condition Transmit Note Note When SPIEn 1 Receive When SPIEn 1 Note To cancel slave ...

Page 396: ... SPDn WTIMn H H L L H H L ACKEn MSTSn STTn L L SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2 D5 D6 D7 IICn address IICn FFH Note Note IICn data Start condition Note To cancel master wait write FFH to IICn ...

Page 397: ... L L L H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Note Note Receive Transmit IICn data IICn data IICn FFH Note IICn FFH Note Note To cancel master wait write FFH to I...

Page 398: ...H L L L H H ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IICn address IICn FFH Note Note IICn data Stop condition Start condition When SPIEn 1 N ACK When SPIEn 1 Note To cancel master wait write FFH to ...

Page 399: ...electable baud rates In addition a baud rate based on divided clock input to the ASCKn pin can also be defined The UARTn baud rate generator can also be used to generate a MIDI standard baud rate 31 25 Kbps 10 5 1 Configuration The UARTn includes the following hardware Table 10 15 Configuration of UARTn Item Configuration Registers Transmit shift registers 0 1 TXS0 TXS1 Receive buffer registers 0 ...

Page 400: ...ata Writing data to TXSn starts the transmit operation TXSn can be written to by an 8 bit memory manipulation instruction It cannot be read from RESET input sets these registers to FFH Caution Do not write to TXSn during a transmit operation 2 Receive shift registers 0 1 RX0 RX1 The RXn register converts serial data input via the RXD0 and RXD1 pins into parallel data When one byte of data is recei...

Page 401: ...operations based on the values set to asynchronous serial interface mode register n ASIMn During a receive operation it performs error checking such as for parity errors and sets various values to asynchronous serial interface status register n ASISn according to the type of error that is detected 10 5 2 UARTn control registers UARTn uses the following registers for control function n 0 1 Asynchro...

Page 402: ...ction Port function 1 0 UARTn mode transmit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS0n Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity UCLn Character length specification 0 7 bits 1 8 bits SLn St...

Page 403: ...arity error Transmit data parity does not match FEn Framing error flag 0 No framing error 1 Framing errorNote 1 Stop bit not detected OVEn Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if the stop bit length has been set to two bits by setting bit 2 SLn of asynchronous serial interface...

Page 404: ... 8 8 0 0 0 0 1 0 0 1 fSCK 9 9 0 0 0 0 1 0 1 0 fSCK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 The value of BRGCn becomes 00H after reset Before starting operation select a setting other than Setting prohibited Selecting the Setting pro...

Page 405: ...ternal clock ASCKn 0 0 0 1 fXX 0 0 0 1 0 fXX 2 1 0 0 1 1 fXX 4 2 0 1 0 0 fXX 8 3 0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 TM3 output at n 1 TM2 output 1 0 0 0 fXX 64 6 1 0 0 1 fXX 128 7 1 0 1 0 fXX 256 8 1 0 1 1 fXX 512 9 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Setting prohibited Cautions 1 If write is performed to BRGMCn0 n1 during communication processing the output of the baud rate generator wi...

Page 406: ...rts a Register settings Operation stop mode settings are made via bits TxEn and RXEn of asynchronous serial interface mode register n ASIMn Figure 10 45 ASIMn Setting Operation Stop Mode After reset 00H R W Address FFFFF300H FFFFF310H 7 6 5 4 3 2 1 0 ASIMn TXEn RXEn PS1n PS0n CLn SLn ISRMn 0 n 0 1 TXEn RXEn Operation mode RXDn Pxx pin function TXDn Pxx pin function 0 0 Operation stop Port function...

Page 407: ...ction 0 1 UARTn mode receive only Serial function Port function 1 0 UARTn mode transmit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS0n Parity bit specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity CLn Character le...

Page 408: ...op bit not detected OVEn Overrun error flag 0 No overrun error 1 Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if the stop bit length has been set to two bits by setting bit 2 SLn of asynchronous serial interface mode register n ASIMn stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 ...

Page 409: ... 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255 Cautions 1 Reset input clears the BRGCn register to 00H Before starting operation select a setting other than Setting prohibited Selecting Setting prohibited setting in stop mode does not cause any problems 2 If write is p...

Page 410: ...0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 TM3 output at n 1 TM2 output 1 0 0 0 fXX 64 6 1 0 0 1 fXX 128 7 1 0 1 0 fXX 256 8 1 0 1 1 fXX 512 9 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Setting prohibited Cautions 1 If write is performed to BRGMCn0 n1 during communication processing the output of the baud rate generator is disturbed and communication will not be performed normally Therefore do not writ...

Page 411: ...e Table 10 16 Relationship Between Main Clock and Baud Rate fXX 8 MHz fXX 12 58 MHz fXX 16 MHz Note 1 fXX 20 MHz Note 2 Baud Rate bps k m Error k m Error k m Error k m Error 32 244 9 0 06 64 244 8 0 06 192 9 0 02 244 9 0 06 128 244 7 0 06 192 8 0 02 244 8 0 06 152 9 0 39 300 208 6 0 16 164 7 0 12 208 7 0 16 130 8 0 16 600 208 5 0 16 164 6 0 12 208 6 0 16 130 7 0 16 1200 208 4 0 16 164 5 0 12 208 5...

Page 412: ... speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed clock clock cycle T enabling normal reception START D0 D7 P STOP 32T 64T 256T 288T 320T 352T Ideal sampling point 304T 336T 30 45T 60 9T 304 5T 15 5T 15 5T 0 5T Sampling error 33 55T 67 1T 301 95T 335 5T Remark T 8 bit counter s source clock cycle Baud rate error tolerance when k 16 100 4 8438 15 5 320 ...

Page 413: ... D6 D7 Start bit Parity bit Stop bit 1 data frame Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits When 7 bits is selected as the number of character bits only the lower 7 bits from bit 0 to bit 6 are valid so that during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 mu...

Page 414: ...he receive data including a parity bit and a parity error occurs when the result is an odd number ii Odd parity During transmission The number of bits in transmit data including a parity bit is controlled so that an odd number of 1 bits is set The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits The parity bit value is 0 If the transmit data contains an e...

Page 415: ...ure 10 52 Timing of Asynchronous Serial Interface Transmit Completion Interrupt TxDn output D0 D1 D2 D6 D7 Parity STOP START INTSTn a Stop bit length 1 TxDn output D0 D1 D2 D6 D7 Parity START INTSTn b Stop bit length 2 STOP Caution Do not write to asynchronous serial interface mode register n ASIMn during a transmit operation Writing to ASIMn during a transmit operation may disable further transmi...

Page 416: ...pleted the receive data in the shift register is transferred to receive buffer register n RXBn and a receive completion interrupt INTSRn occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXBn When an error occurs INSTRn is generated if bit 1 ISRMn of ASIMn is cleared 0 On the other hand INTSRn is not generated if the ISRMn bit is set 1 If the...

Page 417: ...0 17 Receive Error Causes Receive Error Cause ASISn Value Parity error Parity specification at transmission and receive data parity do not match 04H Framing error Stop bit is not detected 02H Overrun error Reception of subsequent data was completed before data was read from the receive buffer register 01H Figure 10 54 Receive Error Timing RxDn Input INTSRn Note D7 D6 D2 D1 D0 Parity STOP START INT...

Page 418: ...ransmit shift register n TXSn and receive buffer register n RXBn are stopped and their values immediately before the clock stopped are held The TXDn pin output holds the data immediately before the clock was stopped in STOP mode during transmission When the clock is stopped during reception the receive data until the clock stopped is stored and subsequent receive operations are stopped Reception r...

Page 419: ...h serial I O mode the processing time of data transfer is shortened MSB and LSB can be switched for the first bit of data to be transferred in serial The 3 wire variable length serial I O mode is useful when connecting to a peripheral I O device that includes a clocked serial interface a display controller etc 10 6 1 Configuration CSI4 includes the following hardware Table 10 18 Configuration of C...

Page 420: ...chronized with the serial clock SIO4 is set by a 16 bit memory manipulation instruction The serial operation starts when data is written to or read from SIO4 while the bit 7 CSIE4 of variable length serial control register 4 CSIM4 is 1 When transmitting data written to SIO4 is output via the serial output SO4 When receiving data is read from the serial input SI4 and written to SIO4 RESET input cle...

Page 421: ...ster regardless of whether MSB or LSB is set for the first transfer bit Any data can be set to the unused higher bits however in this case the received data after a serial transfer operation becomes 0 Figure 10 56 When Transfer Bit Length Other Than 16 Bits Is Set a When transfer bit length is 10 bits and MSB first b When transfer bit length is 12 bits and LSB first SI4 SO4 15 10 9 0 Fixed to 0 SI...

Page 422: ...fter reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SIO4 operation enable disable specification CSIE4 Shift register operation Serial counter Port 0 Operation disabled Clear Port functionNote 1 1 Operation enabled Count operation enabled Serial function port functionNote 2 Transfer operation mode flag MODE4 Operation mode Transfer start trigger SO4 output 0 Transm...

Page 423: ...clears CSIB4 to 00H After reset 00H R W Address FFFFF2E4H 7 6 5 4 3 2 1 0 CSIB4 0 CMODE DMODE DIR BSEL3 BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing SO4 output timing 0 0 Low level Rising edge of SCK4 Falling edge of SCK4 0 1 Low level Falling edge of SCK4 Rising edge of SCK4 1 0 High level Falling edge of SCK4 Rising edge of SCK4 1 1 High level Rising edge of SCK4 Falling ...

Page 424: ...RGCN4 can be set by an 8 bit memory manipulation instruction RESET input clears BRGCN4 to 00H After reset 00H R W Address FFFFF2E6H 7 6 5 4 3 2 1 0 BRGCN4 0 0 0 0 0 BRGN2 BRGN1 BRGN0 BRGN2 BRGN1 BRGN0 Source clock fSCK n 0 0 0 fXX 0 0 0 1 fXX 2 1 0 1 0 fXX 4 2 0 1 1 fXX 8 3 1 0 0 fXX 16 4 1 0 1 fXX 32 5 1 1 0 fXX 64 6 1 1 1 fXX 128 7 ...

Page 425: ...CK 252 126 1 1 1 1 1 1 1 fSCK 254 127 The baud rate transmit receive clock that is generated is obtained by dividing the main clock Generation of baud rate transmit receive clock using main clock The transmit receive clock is obtained by dividing the main clock The following equation is used to obtain the baud rate from the main clock When 1 k 127 Baud rate Hz fXX Main clock oscillation frequency ...

Page 426: ...de SI4 SO4 and SCK4 can be used as normal I O ports a Register settings Operation stop mode is set via CSIE4 bit of variable length serial control register 4 CSIM4 While CSIE4 0 SIO4 operation stop state the pins connected to SI4 SO4 or SCK4 function as port pins Figure 10 57 CSIM4 Setting Operation Stop Mode After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SI...

Page 427: ... I O mode is set via variable length serial control register 4 CSIM4 Figure 10 58 CSIM4 Setting 3 Wire Variable Length Serial I O Mode After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SIO4 operation enable disable specification CSIE4 Shift register operation Serial counter Port 1 Operation enabled Count operation enabled Serial function port function Transfer ...

Page 428: ...DIR BSEL3 BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing SO4 output timing 0 0 Low level Rising edge of SCK4 Falling edge of SCK4 0 1 Low level Falling edge of SCK4 Rising edge of SCK4 1 0 High level Falling edge of SCK4 Rising edge of SCK4 1 1 High level Rising edge of SCK4 Falling edge of SCK4 DIR Serial transfer direction 0 LSB first 1 MSB first BSEL3 BSEL2 BSEL1 BSEL0 Bit...

Page 429: ...can change the attribute of the serial clock SCK4 and the phases of serial data SI4 and SO4 Figure 10 60 Timing of 3 Wire Variable Length Serial I O Mode SCK4 CMODE 0 SIO4 write SO4 DMODE 1 INTCSI4 SCK4 CMODE 1 SO4 DMODE 0 Remark An arrow shows the SI4 data fetch timing When CMODE 0 the serial clock SCK4 stops at the high level during the operation stop and outputs the low level during a data tran...

Page 430: ...Transmit transmit and receive mode MODE4 0 Transfer starts when writing to SIO4 Receive only mode Transfer starts when reading from SIO4 Caution After data has been written to SIO4 transfer will not start even if the CSIE4 bit value is set to 1 Completion of the final bit transfer automatically stops the serial transfer operation and sets the interrupt request flag INTCSI4 Figure 10 61 Timing of 3...

Page 431: ...rigger input ADTRG rising edge falling edge or both rising and falling edges can be specified 2 Software start Conversion is started by setting A D converter mode register 1 ADM1 One analog input channel is selected from ANI0 to ANI11 and A D conversion is performed If A D conversion has been started by means of a hardware start conversion stops once it has been completed and an interrupt request ...

Page 432: ...REF AVSS INTAD 4 ADS3 ADS2 ADS1 ADS0 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS Selector Sample hold circuit AVSS Voltage comparator Tap selector ADTRG Edge detector Controller A D conversion result register ADCR Trigger enable Analog input channel specification register ADS A D converter mode register 1 ADM1 Internal bus IEAD A D converter mode register 2 ADM2 Successive approximation register SAR AVDD ...

Page 433: ...he conversion is loaded to this register from the successive approximation register The higher 10 bits of this register hold the result of the A D conversion the lower 6 bits are fixed to 0 This register is read using a 16 bit memory manipulation instruction RESET input sets ADCR to 0000H When using only the higher 8 bits of the result of the A D conversion ADCRH is read using an 8 bit memory mani...

Page 434: ...hin the range of the absolute maximum ratings is input to a channel the conversion value of the channel is undefined and the conversion values of the other channels may also be affected 7 AVREF pin This pin inputs a reference voltage to the A D converter The signals input to the ANI0 to ANI11 pins are converted into digital signals based on the voltage applied across AVREF and AVSS 8 AVSS pin This...

Page 435: ...ister specifies the conversion time of the input analog signal to be converted into a digital signal starting or stopping the conversion and an external trigger ADM is set by a 1 bit or 8 bit memory manipulation instruction RESET input clears ADM1 to 00H 1 2 After reset 00H R W Address FFFFF3C0H 7 6 5 4 3 2 1 0 ADM1 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS ADCS A D conversion control 0 Conversion stopp...

Page 436: ...rohibited 1 1 0 0 48 fXX 24 fXX Setting prohibited Setting prohibited 1 1 0 1 36 fXX 18 fXX Setting prohibited Setting prohibited 1 1 1 0 Setting prohibited Setting prohibited Setting prohibited 1 1 1 1 12 fXX 6 fXX Setting prohibited Setting prohibited EGA1 EGA0 Valid edge specification for external trigger signal 0 0 No edge detection 0 1 Detection at falling edge 1 0 Detection at rising edge 1 ...

Page 437: ...Channel Specification 0 0 0 0 ANI0 0 0 0 1 ANI1 0 0 1 0 ANI2 0 0 1 1 ANI3 0 1 0 0 ANI4 0 1 0 1 ANI5 0 1 1 0 ANI6 0 1 1 1 ANI7 1 0 0 0 ANI8 1 0 0 1 ANI9 1 0 1 0 ANI10 1 0 1 1 ANI11 Other than above Setting prohibited Caution Be sure to set bits 7 to 4 to 0 3 A D converter mode register 2 ADM2 ADM2 specifies connection disconnection of AVDD and AVREF ADM2 is set by a 1 bit or 8 bit memory manipulati...

Page 438: ...s set If the analog input voltage is less than 1 2 AVREF the MSB is reset 6 Next bit 8 of the SAR is automatically set and the analog input voltage is compared again Depending on the value of bit 9 to which the result of the preceding comparison has been set the voltage tap of the series resistor string is selected as follows Bit 9 1 3 4 AVREF Bit 9 0 1 4 AVREF The analog input voltage is compared...

Page 439: ...ion result Conversion result A D conversion is successively executed until bit 7 ADCS of A D converter mode register 1 ADM1 is reset to 0 by software If ADM1 and the analog input channel specification register ADS are written during A D conversion the conversion is initialized If ADCS is set to 1 at this time conversion is started from the beginning RESET input sets the A D conversion result regis...

Page 440: ... 0 5 INT Function that returns integer of value in VIN Analog input voltage AVREF AVREF pin voltage ADCR Value of the A D conversion result register ADCR The relationship between the analog input voltage and A D conversion result is shown below Figure 11 3 Relationship Between Analog Input Voltage and A D Conversion Result 1 1 3 2 5 3 2043 1022 20451023 2047 1 2048 102420481024 2048 1024 2048 1024...

Page 441: ...nalog input pin specified by the analog input channel specification register ADS into a digital signal When the A D conversion has been completed the result of the conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated Once A D conversion has been started and completed conversion is not started again unless a new external trigger signal i...

Page 442: ...gnal INTAD is generated Once A D conversion has been started and completed the next conversion is started immediately A D conversion is repeated until new data is written to ADS If ADS is rewritten during A D conversion the conversion under execution is stopped and conversion of the newly selected analog input channel is started If data with ADCS set to 0 is written to ADM1 during A D conversion t...

Page 443: ...is time the current consumption of the A D converter can be reduced by stopping the conversion by resetting the bit 7 ADCS of A D converter mode register 1 ADM1 to 0 To reduce the current consumption in the IDLE STOP mode set the AVREF potential in the user circuit to the same value 0 V as the AVSS potential 2 Input range of ANI0 to ANI11 Keep the input voltage of the ANI0 to ANI11 pins to within ...

Page 444: ...11 The analog input ANI0 to ANI11 pins function alternately as port pins To execute A D conversion with any of ANI0 to ANI11 selected do not execute an instruction that inputs data to the port during conversion otherwise the resolution may drop If a digital pulse is applied to pins adjacent to the pin whose input signal is converted into a digital signal the expected A D conversion result may not ...

Page 445: ...est flag may be set immediately before ADS is rewritten If ADIF is read immediately after ADS has been rewritten it may be set despite the fact that conversion of the newly selected analog input signal has not been completed yet When stopping A D conversion and then resuming clear ADIF before resuming conversion Figure 11 7 A D Conversion End Interrupt Generation Timing Rewriting ADS ANIn conversi...

Page 446: ...the VDD pin to the AVDD pin as shown in Figure 11 8 Figure 11 8 Handling of AVDD Pin AVREF VDD VSS AVDD AVSS Main power supply Backup capacitor 9 Reading out A D converter result register ADCR A write operation to A D converter mode register 1 ADM1 and the analog input channel specification register ADS may cause the ADCR contents to be undefined Therefore read the A D conversion result during A D...

Page 447: ...the following formula regardless of the resolution 1 FSR Max value of analog input voltage that can be converted Min value of analog input voltage that can be converted 100 AVREF 0 100 AVREF 100 1LSB is as follows when the resolution is 10 bits 1LSB 1 2 10 1 1024 0 098 FSR Accuracy has no relation to resolution but is determined by overall error 2 Overall error This shows the maximum error value b...

Page 448: ...rror zero scale error full scale error integral linearity error and differential linearity error in the characteristics table Figure 11 10 Quantization Error 0 0 1 1 Digital output Quantization error 1 2LSB 1 2LSB Analog input 0 AVREF 4 Zero scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value 1 2 LSB when the digital outp...

Page 449: ...o 1 111 Figure 11 12 Full Scale Error 100 011 010 000 0 AVREF AVREF 1 AVREF 2 AVREF 3 Digital output Lower 3 bits Analog input LSB Full scale error 111 6 Differential linearity error While the ideal width of code output is 1LSB this indicates the difference between the actual measurement value and the ideal value Figure 11 13 Differential Linearity Error 0 AVREF Digital output Analog input Differe...

Page 450: ...scale error are 0 Figure 11 14 Integral Linearity Error 0 AVREF Digital output Analog input Integral linearity error Ideal line 1 1 0 0 8 Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained The sampling time is included in the conversion time in the characteristics table 9 Sampling time This is the time the analog ...

Page 451: ...t units After a DMA transfer has occurred a specified number of times DMA transfer completion interrupt INTDMA0 to INTDMA5 requests are output individually from the various channels The priority levels of the DMA channels are fixed as follows for simultaneous generation of multiple DMA transfer requests DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 12 2 Transfer Completion Interrupt Request After a DMA transfer h...

Page 452: ... INT signal is input When the DMA transfer request signal is acknowledged the CPU generates a DMA transfer acknowledge signal for the channel control block and interface control block after the current CPU processing has finished For the INT signal refer to the TTYPn1 and TTYPn0 bits in 12 4 5 DMA channel control registers 0 to 5 DCHC0 to DCHC5 2 Channel control block The channel control block dis...

Page 453: ...e can be read written in 16 bit units After reset Undefined R W Address DIOA0 FFFFF180H DIOA3 FFFFF1B0H DIOA1 FFFFF190H DIOA4 FFFFF1C0H DIOA2 FFFFF1A0H DIOA5 FFFFF100H 15 14 13 12 11 10 9 1 0 DIOAn 0 0 0 0 0 0 IOAn9 to IOAn1 0 n 0 to 5 Caution The following peripheral I O registers must not be set P4 P5 P6 P9 P11 PM4 PM5 PM6 PM9 PM11 MM DWC BCC SYC PSC PCC SYS PRCMD DIOAn DRAn DBCn DCHCn CORCN COR...

Page 454: ...50 SB1 µPD703033A 703033AY 703033B 703033BY 70F3033A 70F3033AY 70F3033B 70F3033BY V850 SB2 µPD703035A 703035AY 703035B 703035BY 70F3035A 70F3035AY 70F3035B 70F3035BY 16 KB 16 KB xxFFB000H to xxFFEFFFH V850 SB1 µPD703030B 703030BY 703032A 703032AY 703032B 703032BY 70F3030B 70F3030BY 70F3032A 70F3032AY 70F3032B 70F3032BY V850 SB2 µPD703036H 703036HY 703037A 703037AY 703037H 703037HY 70F3036H 70F3036...

Page 455: ...n DRAn Setting Value and Internal RAM 8 KB xxFFFFFFH xxFFD000H xxFFCFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM are On chip peripheral I O area Internal RAM area DRAn setting value 1FFFH 0000H 8 KB usable for DMA Cautions 1 Do not set odd addresses for 16 bit transfer DCHCn register DSn 1 2 While the increment function is being used DCHCn register DDADn 0 if t...

Page 456: ... xxFFFFFFH xxFFC000H xxFFBFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area On chip peripheral I O area Internal RAM area DRAn setting value 2FFFH 0000H 12 KB usable for DMA Cautions 1 Do not set odd addresses for 16 bit transfer DCHCn register DSn 1 2 While the increment function is being used DCHCn register DDADn 0 if the DRAn register value is set to 2FFFH i...

Page 457: ...00H to 2FFFH or 3000H to 3FFFH n 0 to 5 Figure 12 4 Correspondence Between DRAn Setting Value and Internal RAM 16 KB xxFFFFFFH xxFFB000H xxFFAFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area On chip peripheral I O area Internal RAM area DRAn setting value 2FFFH 3000H 3FFFH xxFFC000H xxFFBFFFH 0000H 16 KB usable for DMA Caution Do not set odd addresses for 16 b...

Page 458: ... the range of 0000H to 0FFFH or 1000H to 3FFFH n 0 to 5 Figure 12 5 Correspondence Between DRAn Setting Value and Internal RAM 24 KB xxFFFFFFH xxFF9000H xxFF8FFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area On chip peripheral I O area Internal RAM area DRAn setting value 0FFFH 1000H 0000H 3FFFH xxFFC000H xxFFBFFFH 12 KB usable for DMA 4 KB usable for DMA xxFFE...

Page 459: ...ld be set for 16 bit transfers These registers are can be read written in 8 bit units After reset Undefined R W Address DBC0 FFFFF184H DBC3 FFFFF1B4H DBC1 FFFFF194H DBC4 FFFFF1C4H DBC2 FFFFF1A4H DBC5 FFFFF1D4H 7 6 5 4 3 2 1 0 DBCn BCn7 BCn6 BCn5 BCn4 BCn3 BCn2 BCn1 BCn0 n 0 to 5 Caution Values set to bit 0 are ignored during 16 bit transfers 4 DMA start factor expansion register DMAS This is an 8 ...

Page 460: ...ion control 0 Increment 1 Address is fixed Channel n DMAS2 DMAS1 DMAS0 TTYPn1 TTYPn0 DMA transfer start factor setting 0 0 INTCSI0 INTIIC0Note 2 0 1 INTCSI1 INTSR0 1 0 INTAD 0 x x x 1 1 INTTM00 0 0 0 INTCSI0 INTIIC0Note 2 1 0 0 INTCSI1 INTSR0 0 1 INTST0 1 0 INTP0 1 x x x 1 1 INTTM10 0 0 0 INTIIC1Note 2 1 0 0 INTCSI3 INTSR1 0 1 INTP6 1 0 INTIE1 V850 SB2 only 2 x x x 1 1 INTAD 0 0 0 INTIIC1Note 2 1 ...

Page 461: ...sferNote 3 0 8 bit transfer 1 16 bit transfer ENn Control of DMA transfer enable disable statusNote 4 0 Disabled 1 Enabled reset to 0 after DMA transfer is completed Notes 1 TCn n 0 to 5 is set to 1 when a specified number of transfers are completed and is cleared to 0 when a write instruction is executed 2 INTIIC0 and INTIIC1 are available only in the Y versions products with on chip I 2 C 3 Make...

Page 462: ... borrow occurs DMA transfer processing signal DMA transfer acknowledge signal Processing format Access destination for transfer from internal RAM to peripheral I O Access destination for transfer from peripheral I O to internal RAM CPU processing DMA transfer processing CPU processing Remark n 0 to 5 If two or more DMA transfer requests are generated simultaneously the DMA transfer requests are ex...

Page 463: ... the same register as the register used in i Remark xx Identifying name of peripheral unit see Table 5 2 n Peripheral unit number see Table 5 2 For example when using the DMA function if an unmasked INTCSI0 interrupt occurs during bit manipulation of the interrupt request flag CSIF0 of the CSIC0 register by the CLR1 instruction INTCSI0 interrupt servicing occurs twice Under such conditions because...

Page 464: ...ared 0 b Interrupt servicing when interrupt servicing occurs twice EI RETI RETI Interrupt request flag xxIFn is cleared 0 Main routine Interrupt servicing routine Interrupt request flag xxIFn is not cleared and remains 1 Bit manipulation instruction to xxIFn Interrupt request Since the interrupt request flag xxIFn remains 1 the interrupt is serviced again Remark xx Identification name of each peri...

Page 465: ...xecution Main routine Interrupt servicing routine Interrupt request flag xxIFn is cleared 0 Bit manipulation instruction to xxIFn Interrupt request d Countermeasure use condition ii EI EI RETI Interrupt request Main routine Interrupt servicing routine Interrupt request flag xxIFn is not cleared 0 and remains 1 Bit manipulation instruction to xxIFn xxIFn is cleared 0 at the start of the interrupt s...

Page 466: ...on the occurrence of an external interrupt or external trigger Because RTO can output signals without jitter it is suitable for controlling a stepper motor The real time output port can be set in port mode or real time output port mode in 1 bit units 13 2 Features 8 bit real time output unit Port mode and real time output mode can be selected in 1 bit units 8 bits 1 channel or 4 bits 2 channels ca...

Page 467: ...trigger controller INTTM4 INTTM5 Real time output port control register RTPC 4 Real time output buffer register higher 4 bits RTBH Real time output buffer register lower 4 bits RTBL Real time output port mode register RTPM RTO includes the following hardware Table 13 1 Configuration of RTO Item Configuration Registers Real time output buffer registers RTBL RTBH Control registers Real time output p...

Page 468: ...of Real Time Output Buffer Registers Higher 4 bits Lower 4 bits RTBL RTBH Table 13 2 Operation When Real Time Output Buffer Registers Are Manipulated Read Note 1 Write Note 2 Operation Mode Register to Be Manipulated Higher 4 bits Lower 4 bits Higher 4 bits Lower 4 bits RTBL RTBH RTBL Invalid RTBL 4 bits 2 channels RTBH RTBH RTBL RTBH Invalid RTBL RTBH RTBL RTBH RTBL 8 bits 1 channel RTBH RTBH RTB...

Page 469: ...ry manipulation instruction RESET input clears RTPM to 00H After reset 00H R W Address FFFFF3A4H 7 6 5 4 3 2 1 0 RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPM0 RTPMn Selection of real time output port n 0 to 7 0 Port mode 1 Real time output port mode Cautions 1 Set a port pin to the output mode when it is used as a real time output port pin 2 A port specified as a real time output port canno...

Page 470: ... BYTE EXTR 0 0 0 0 RTPOE Control of operation of real time output port 0 Disable operationNote 1 Enable operation RTPEG Valid edge of RTPTRG 0 Falling edge 1 Rising edge BYTE Operation mode of real time output port 0 4 bits 2 channels 1 8 bits 1 channel EXTR Control of real time output by RTPTRG signal 0 Do not use RTPTRG as real time output trigger 1 Use RTPTRG as real time output trigger Note RT...

Page 471: ... time output port mode or port mode in 1 bit units Set the real time output port mode register RTPM iv Select a trigger and valid edge Set bits 4 5 and 6 EXTR BYTE and RTPEG of RTPC v Set the same value as i to the real time output buffer registers RTBH and RTBL 3 Enable the real time output operation Set RTPOE to 1 4 Set the output latches P100 to P107 of port 10 to 0 and the next output to RTBH ...

Page 472: ...gister RTPM is output from the bits of RTP0 to RTP7 The bits specified in the port mode by RTPM output 0 If the real time output operation is disabled by clearing RTPOE to 0 RTP0 to RTP7 output 0 regardless of the setting of RTPM Note EXTR Bit 4 of the real time output port control register RTPC BYTE Bit 5 of the real time output port control register RTPC Figure 13 3 Example of Operation Timing o...

Page 473: ...t latch to the real time output buffer registers RTBH and RTBL before enabling the real time output operation RTPOE 0 1 3 Operation cannot be guaranteed if a conflict between the following signals occurs Use software to avoid a conflict Conflict between the switch operation from the RTP mode to the port mode RTPOE 1 and the valid edge of the selected real time output port trigger Conflict between ...

Page 474: ... 2 Port Pin Function 14 2 1 Port 0 Port 0 is an 8 bit I O port for which I O settings can be controlled in 1 bit units A pull up resistor can be connected in 1 bit units software pull up function When using P00 to P04 as the NMI or INTP0 to INTP3 pins noise is eliminated by an analog noise eliminator When using P05 to P07 as the INTP4 ADTRG INTP5 RTPTRG and INTP6 pins noise is eliminated by a digi...

Page 475: ... NMI and INTP0 to INTP6 are specified via rising edge specification register 0 EGP0 and falling edge specification register 0 EGN0 A pull up resistor can be connected in 1 bit units when specified via pull up resistor option register 0 PU0 When a reset is input the settings are initialized to input mode Also the valid edge of each interrupt request becomes invalid NMI and INTP0 to INTP6 do not fun...

Page 476: ... to eliminate the noise 4 Noise elimination is not performed when these pins are used as an normal input port pins 3 Control registers a Port 0 mode register PM0 PM0 can be read written in 8 bit or 1 bit units After reset FFH R W Address FFFFF020H 7 6 5 4 3 2 1 0 PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n Control of I O mode n 0 to 7 0 Output mode 1 Input mode b Pull up resistor option regis...

Page 477: ...g edge 1 Interrupt request signal occurred at rising edge Remark n 0 Control of NMI pin n 1 to 7 Control of INTP0 to INTP6 pins d Falling edge specification register 0 EGN0 EGN0 can be read written in 8 bit or 1 bit units After reset 00H R W Address FFFFF0C2H 7 6 5 4 3 2 1 0 EGN0 EGN07 EGN06 EGN05 EGN04 EGN03 EGN02 EGN01 EGN00 EGN0n Control of falling edge detection n 0 to 7 0 Interrupt request si...

Page 478: ... to P07 P ch WRPM WRPORT RD WRPU VDD P00 NMI P01 INTP0 P02 INTP1 P03 INTP2 P04 INTP3 P05 INTP4 ADTRG P06 INTP5 RTPTRG P07 INTP6 Selector PU0n PU0 Output latch P0n PM0n PM0 Internal bus Remarks 1 PU0 Pull up resistor option register 0 PM0 Port 0 mode register RD Port 0 read signal WR Port 0 write signal 2 n 0 to 7 ...

Page 479: ... read the pin levels at that time are read Writing to P1 writes the values to that register This does not affect the input pins In output mode When the P1 register is read the P1 register s values are read Writing to P1 writes the values to that register and those values are immediately output Port 1 includes the following alternate functions SDA0 and SCL0 pins are available only in the Y versions...

Page 480: ...r can be connected in 1 bit units when specified via pull up resistor option register 1 PU1 Clear the P1 and PM1 registers to 0 when using alternate function pins as outputs The ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode 2 Control registers a Port 1 mode register PM1 PM1 can be read written ...

Page 481: ...d as a normal output 3 Block diagram Port 1 Figure 14 2 Block Diagram of P10 to P12 P14 and P15 P ch WRPM WRPF WRPORT RD WRPU VDD VDD Selector PF1n PF1 PM1n PM1 PU1n PU1 P ch N ch Internal bus Output latch P1n Alternate function P10 SI0 SDA0Note P11 SO0 P12 SCK0 SCL0Note P14 SO1 TxD0 P15 SCK1 ASCK0 Note The SDA0 and SCL0 pins are available only in the Y versions products with on chip I 2 C Remarks...

Page 482: ...re 14 3 Block Diagram of P13 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P13 PM13 PM1 PU13 PU1 Internal bus Alternate function P13 SI1 RxD0 Remark PU1 Pull up resistor option register 1 PM1 Port 1 mode register RD Port 1 read signal WR Port 1 write signal ...

Page 483: ...ark In input mode When the P2 register is read the pin levels at that time are read Writing to P2 writes the values to that register This does not affect the input pins In output mode When the P2 register is read the P2 register s values are read Writing to P2 writes the values to that register and those values are immediately output Port 2 includes the following alternate functions SDA1 and SCL1 ...

Page 484: ...the P2 register while in output mode A pull up resistor can be connected in 1 bit units when specified via pull up resistor option register 2 PU2 When using the alternate function as TI2 and TI3 pins noise elimination is provided by a digital noise eliminator same as digital noise eliminator for port 0 Clear the P2 and PM2 registers to 0 when using alternate function pins as outputs The ORed resul...

Page 485: ...2 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of on chip pull up resistor connection n 0 to 7 0 Do not connect 1 Connect c Port 2 function register PF2 PF2 can be read written in 8 bit or 1 bit units After reset 00H R W Address FFFFF0A4H 7 6 5 4 3 2 1 0 PF2 0 0 PF25 PF24 0 PF22 PF21 PF20 PF2n Control of normal output N ch open drain output n 0 to 2 4 5 0 Normal output 1 N ch open drain ou...

Page 486: ...2 PU2n PU2 P ch N ch Internal bus Output latch P2n Alternate function P20 SI2 SDA1Note P21 SO2 P22 SCK2 SCL1Note P24 SO3 TxD1 P25 SCK3 ASCK1 Note The SDA1 and SCL1 pins are available only in the Y versions products with on chip I 2 C Remarks 1 PU2 Pull up resistor option register 2 PF2 Port 2 function register PM2 Port 2 mode register RD Port 2 read signal WR Port 2 write signal 2 n 0 to 2 4 5 ...

Page 487: ...Diagram of P23 P26 and P27 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P13 PM13 PM1 PU13 PU1 Internal bus Alternate function P13 SI1 RxD0 Remarks 1 PU2 Pull up resistor option register 2 PM2 Port 2 mode register RD Port 2 read signal WR Port 2 write signal 2 n 3 6 or 7 ...

Page 488: ...utput mode n 0 to 7 0 Output 0 1 Output 1 Remark In input mode When the P3 register is read the pin levels at that time are read Writing to P3 writes the values to that register This does not affect the input pins In output mode When the P3 register is read the P3 register s values are read Writing to P3 writes the values to that register and those values are immediately output Port 3 includes the...

Page 489: ...ator same as digital noise eliminator for port 0 When using the alternate function A13 to A15 pins set the pin functions via the memory address output mode register MAM At this time be sure to set the PM3 registers PM34 PM35 PM36 and the P3 registers P34 P35 P36 to 0 Clear the P3 and PM3 registers to 0 when using alternate function pins as outputs The ORed result of the port output and the alterna...

Page 490: ...pen drain output n 3 4 0 Normal output 1 N ch open drain output 3 Block diagram Port 3 Figure 14 6 Block Diagram of P30 to P32 and P35 to P37 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P3n PM3n PM3 PU3n PU3 Internal bus Alternate function P30 TI00 P31 TI01 P32 TI10 SI4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 Remarks 1 PU3 Pull up resistor option register 3 PM3 Port 3 mode register RD Port ...

Page 491: ... WRPF WRPORT RD WRPU VDD VDD Selector PF3n PF3 PM3n PM3 PU3n PU3 P ch N ch Internal bus Output latch P3n Alternate function P33 TI11 SO4 P34 TO0 A13 SCK4 Remarks 1 PU3 Pull up resistor option register 3 RF3 Port 3 function register PM3 Port 3 mode register RD Port 3 read signal WR Port 3 write signal 2 n 3 4 ...

Page 492: ...time are read Writing to P4 and P5 writes the values to those registers This does not affect the input pins In output mode When the P4 and P5 registers are read their values are read Writing to P4 and P5 writes the values to those registers and those values are immediately output Ports 4 and 5 include the following alternate functions Table 14 6 Alternate Function Pins of Ports 4 and 5 Pin Name Al...

Page 493: ...P5 register output latch values can be read by reading the P4 and P5 registers while in output mode A software pull up function is not implemented When using the alternate function as AD0 to AD15 set the pin functions via the memory expansion register MM This does not affect the PM4 and PM5 registers When a reset is input the settings are initialized to input mode 2 Control register a Port 4 mode ...

Page 494: ... Block diagram Ports 4 and 5 Figure 14 8 Block Diagram of P40 to P47 and P50 to P57 WRPM WRPORT RD Selector Output latch mn PMmn PMm Internal bus Pmn ADx Remarks 1 PMm Port m mode register RD Port m read signal WR Port m write signal 2 m 4 5 n 0 to 7 x 0 to 15 ...

Page 495: ...e P6 register is read the pin levels at that time are read Writing to P6 writes the values to that register This does not affect the input pins In output mode When the P6 register is read the P6 register s values are read Writing to P6 writes the values to that register and those values are immediately output Port 6 includes the following alternate functions Table 14 7 Port 6 Alternate Function Pi...

Page 496: ...he P6 register output latch values can be read by reading the P6 register while in output mode A software pull up function is not implemented When using the alternate function A16 to A21 pins set the pin functions via the memory expansion register MM This does not affect the PM6 register When a reset is input the settings are initialized to input mode 2 Control register a Port 6 mode register PM6 ...

Page 497: ...50EJ6V0UD 497 3 Block diagram Port 6 Figure 14 9 Block Diagram P60 to P65 WRPM WRPORT RD Selector Output latch P6n PM6n PM6 Internal bus P6n Ax Remarks 1 PM6 Port 6 mode register RD Port 6 read signal WR Port 6 write signal 2 n 0 to 5 x 16 to 21 ...

Page 498: ...n level n 0 to 7 0 1 Read pin level of bit n After reset Undefined R Address FFFFF010H 7 6 5 4 3 2 1 0 P8 0 0 0 0 P83 P82 P81 P80 P8n Pin level n 0 to 3 0 1 Read pin level of bit n Ports 7 and 8 include the following alternate functions Table 14 8 Alternate Function Pins of Ports 7 and 8 Pin Name Alternate Function I O PULLNote Remark Port 7 P70 ANI0 Input No P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P7...

Page 499: ...s P7 and P8 Data cannot be written to P7 or P8 A software pull up function is not implemented Values read from pins specified as analog inputs are undefined values Do not read values from P7 or P8 during A D conversion 2 Block diagram Ports 7 and 8 Figure 14 10 Block Diagram of P70 to P77 and P80 to P83 Pmn ANIx RD Internal bus Remarks 1 RD Port 7 port 8 read signals 2 m 7 8 n 0 to 7 m 7 0 to 3 m ...

Page 500: ... is read the pin levels at that time are read Writing to P9 writes the values to that register This does not affect the input pins In output mode When the P9 register is read the P9 register s values are read Writing to P9 writes the values to that register and those values are immediately output Port 9 includes the following alternate functions Table 14 9 Port 9 Alternate Function Pins Pin Name A...

Page 501: ...the P9 register while in output mode A software pull up function is not implemented When using the P9 for control signals in expansion mode set the pin functions via the memory expansion mode register MM When a reset is input the settings are initialized to input mode Caution When using port 9 as an I O port set the BIC bit of the system control register SYC to 0 After the system is reset the BIC ...

Page 502: ...ort 9 Figure 14 11 Block Diagram of P90 to P96 WRPM WRPORT RD Selector Output latch P9n PM9n PM9 Internal bus P90 LBEN WRL P91 UBEN P92 R W WRH P93 DSTB RD P94 ASTB P95 HLDAK P96 HLDRQ Remarks 1 PM9 Port 9 mode register RD Port 9 read signal WR Port 9 write signal 2 n 0 to 6 ...

Page 503: ... In input mode When the P10 register is read the pin levels at that time are read Writing to P10 writes the values to that register This does not affect the input pins In output mode When the P10 register is read the P10 register s values are read Writing to P10 writes the values to that register and those values are immediately output Port 10 includes the following alternate functions IERX and IE...

Page 504: ...e memory address output mode register MAM At this time be sure to set P10 and PM10 to 0 When used as the KR0 to KR7 pins noise is eliminated by the analog noise eliminator When using alternate function pins as outputs the ORed result of the port output and the alternate function pin is output from the pins When a reset is input the settings are initialized to input mode Caution When using port 10 ...

Page 505: ...n register PF10 PF10 can be read written in 8 bit or 1 bit units After reset 00H R W Address FFFFF0B4H 7 6 5 4 3 2 1 0 PF10 PF107 PF106 PF105 PF104 PF103 PF102 PF101 PF100 PF10n Control of normal output N ch open drain output n 0 to 7 0 Normal output 1 N ch open drain output ...

Page 506: ...rnal bus Output latch P10n Alternate function P100 RTP0 A5 KR0 P101 RTP1 A6 KR1 P102 RTP2 A7 KR2 P103 RTP3 A8 KR3 P104 RTP4 A9 KR4 IERXNote P105 RTP5 A10 KR5 IETXNote P106 RTP6 A11 KR6 P107 RTP7 A12 KR7 Note The IERX IETX pins apply only to the V850 SB2 Remarks 1 PU10 Pull up resistor option register 10 RF10 Port 10 function register PM10 Port 10 mode register RD Port 10 read signal WR Port 10 wri...

Page 507: ...Undefined P113 P112 P111 P110 P11n Control of output data in output mode n 0 to 3 0 Output 0 1 Output 1 Remark In input mode When the P11 register is read the pin levels at that time are read Writing to P11 writes the values to that register This does not affect the input pins In output mode When the P11 register is read the P11 register s values are read Writing to P11 writes the values to that r...

Page 508: ...ia pull up resistor option register 11 PU11 The on off of wait function can be switched with a port alternate function control register PAC When using the alternate function A1 to A4 pins set the pin functions via the memory address output mode register MAM At this time be sure to clear P11 and PM11 to 0 When a reset is input the settings are initialized to input mode Caution A wait function gener...

Page 509: ... 5 4 3 2 1 0 PU11 0 0 0 0 PU113 PU112 PU111 PU110 PU11n Control of on chip pull up resistor connection n 0 to 3 0 Do not connect 1 Connect c Port alternate function control register PAC PAC can be read written in 8 bit or 1 bit units After reset 00H R W Address FFFFF040H 7 6 5 4 3 2 1 0 PAC 0 0 0 0 0 0 0 WAC P120 Control of output data in output mode 0 Wait function off 1 Wait function on ...

Page 510: ... Block Diagram of P110 to P113 P ch WRPM WRPORT RD WRPU VDD Selector PU11n PU11 Output latch P11n PM11n PM11 Internal bus P110 A1 WAIT P111 A2 P112 A3 P113 A4 Remarks 1 PU11 Pull up resistor option register 11 PM11 Port 11 mode register RD Port 11 read signal WR Port 11 write signal 2 n 0 to 3 ...

Page 511: ...ing not needed for P02 P03 INTP2 Input PM03 1 Setting not needed for P03 P04 INTP3 Input PM04 1 Setting not needed for P04 INTP4 Input P05 ADTRG Input PM05 1 Setting not needed for P05 INTP5 Input P06 RTPTRG Input PM06 1 Setting not needed for P06 P07 INTP6 Input PM07 1 Setting not needed for P07 SI0 Input PM10 1 Setting not needed for P10 P10 SDA0Note I O PM10 0 P10 0 PF10 1 P11 SO0 Output PM11 0...

Page 512: ...P24 TXD1 Output PM24 0 P24 0 Input PM25 1 Setting not needed for P25 SCK3 Output PM25 0 P25 0 P25 ASCK1 Input PM25 1 Setting not needed for P25 TI2 Input PM26 1 Setting not needed for P26 P26 TO2 Output PM26 0 P26 0 TI3 Input PM27 1 Setting not needed for P27 P27 TO3 Output PM27 0 P27 0 P30 TI00 Input PM30 1 Setting not needed for P30 P31 TI01 Input PM31 1 Setting not needed for P31 TI10 Input P32...

Page 513: ...3 4 6 1 MM P60 to P65 A16 to A21 Output Setting not needed for PM60 to PM65 Setting not needed for P60 to P65 Refer to 3 4 6 1 MM P70 to P77 ANI0 to ANI7 Input None Setting not needed for P70 to P77 P80 to P83 ANI8 to ANI11 Input None Setting not needed for P80 to P83 LBEN Output P90 WRL Output Setting not needed for PM90 Setting not needed for P90 Refer to 3 4 6 1 MM P91 UBEN Output Setting not n...

Page 514: ...ut A11 A12 Output PM106 PM107 0 P106 P107 0 Refer to 3 4 6 2 MAM P106 P107 KR6 KR7 Input PM106 PM107 1 Setting not needed for P106 and P107 A1 Output PM110 0 P110 0 Refer to 3 4 6 2 MAM P110 WAIT Input PM110 1 Setting not needed for P110 WAC 1 PAC P111 to P113 A2 to A4 Output PM111 to PM113 0 P111 to P113 0 Refer to 3 4 6 2 MAM Note Only in the V850 SB2 Caution When changing the output level of po...

Page 515: ... pin status does not change Once data has been written to the output latch it is held until the next data is written to the output latch Caution A bit manipulation instruction CLR1 SET1 NOT1 manipulates 1 bit but accesses a port in 8 bit units If this instruction is executed to manipulate a port with a mixture of input and output bits the contents of the output latch of a pin set in the input mode...

Page 516: ...lated malfunction at the RESET pin 15 2 Pin Operations During the system reset period almost all pins are set to high impedance all pins except for RESET X2 XT2 REGC AVREF VDD VSS AVDD AVSS BVDD BVSS EVDD EVSS and VPP IC Accordingly if connected to an external memory device be sure to attach a pull up or pull down resistor for each pin If such a resistor is not attached these pins will be set to h...

Page 517: ...B versions of V850 SB2 Refer to 2 4 I O Circuit Types I O Buffer Power Supplies and Connection of Unused Pins for the power supply corresponding to each pin Figure 16 1 Regulator A D converter 4 5 V to 5 5 V AVDD Main Sub oscillators On chip digital circuit 3 3 V V850 SB1 H versions of V850 SB2 3 0 V A B versions of V850 SB2 Regulator V DD BVDD EVDD Flash memory 3 0 V to 5 5 V 3 0 V to 5 5 V Bidir...

Page 518: ...truction bugs found in the mask ROM can be avoided and program flow can be changed by using the ROM correction function Up to four correction addresses can be specified Cautions 1 The ROM correction function cannot be used for the data in the internal ROM it can only be used for instruction codes If ROM correction is carried out on data that data will replace the instruction code of the JMP r0 ins...

Page 519: ...he correction address matches the fetch address n 0 to 3 Whether match detection by a comparator is enabled or disabled can be set for each channel CORCN can be set by a 1 bit or 8 bit memory manipulation instruction After reset 00H R W Address FFFFF36CH 7 6 5 4 3 2 1 0 CORCN 0 0 0 0 COREN3 COREN2 COREN1 COREN0 CORENn CORADn register and fetch address match detection control 0 Match detection disa...

Page 520: ...ess matches the fetch address At this time the program can judge the following cases by reading CORRQ Reset input CORRQ 00H ROM correction generation CORRQn bit 1 n 0 to 3 Branch to 00000000H by user program CORRQ 00H After reset 00H R W Address FFFFF36EH 7 6 5 4 3 2 1 0 CORRQ 0 0 0 0 CORRQ3 CORRQ2 CORRQ1 CORRQ0 CORRQn Channel n ROM correction request flag 0 No ROM correction request occurred 1 RO...

Page 521: ... the correction address within following ranges µPD703031A 703031AY 703031B 703031BY 703034A 703034AY 703034B 703034BY 128 KB 00000000H to 0001FFFEH µPD703033A 703033AY 703033B 703033BY 703035A 703035AY 703035B 703035BY 256 KB 00000000H to 0003FFFEH µPD703030B 703030BY 703036H 703036HY 384 KB 00000000H to 0005FFFEH µPD703032A 703032AY 703032B 703032BY 703037A 703037AY 703037H 703037HY 512 KB 00000...

Page 522: ...address of the internal RAM that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal ROM Executed by a program stored in the internal ROM Executed by a program stored in the internal RAM Executed by the ROM correction function Caution Check the ROM correction generation from the vector table with a hi...

Page 523: ...3037A 70F3037AY 70F3037H 70F3037HY 512 KB flash memory versions In the instruction fetch to this flash memory 4 bytes can be accessed by a single clock the same as in the mask ROM version Writing to flash memory can be performed with the memory mounted on the target system on board A dedicated flash programmer is connected to the target system to perform writing The following can be considered as ...

Page 524: ...FFFFH can be erased in one shot b Area erase Erasure can be performed in area units there are three 128 KB unit areas Area 0 The area of xx000000H to xx01FFFFH 128 KB is erased Area 1 The area of xx020000H to xx03FFFFH 128 KB is erased Area 2 The area of xx040000H to xx05FFFFH 128 KB is erased 3 V850 SB1 µ µ µ µPD70F3032A 70F3032AY 70F3032B 70F3032BY V850 SB2 µ µ µ µPD70F3037A 70F3037AY 70F3037H 7...

Page 525: ...of the flash memory are rewritten after the V850 SB1 or V850 SB2 is mounted on the target system Mount connectors etc on the target system to connect the dedicated flash programmer 2 Off board programming Writing to a flash memory are performed by the dedicated program adapter FA Series etc before mounting the V850 SB1 or V850 SB2 on the target system Remark FA Series is a product of Naito Densei ...

Page 526: ...te The V850 SB1 and V850 SB2 cannot be supplied with the clock from the CLK pin of the flash programmer PG FP3 Supply the clock by creating an oscillator on the flash writing adapter broken line portion An example of the oscillator is shown below REGC X1 X2 1 F µ Remarks 1 Handle the pins not described above in accordance with the recommended connection of unused pins refer to 2 4 Pin I O Circuit ...

Page 527: ...sary Unnecessary Unnecessary Unnecessary Unnecessary RESET Output Reset signal RESET 31 RESET 31 RESET 31 VPP Output Writing voltage IC VPP 18 IC VPP 18 IC VPP 18 HS Input Handshake signal of CSI0 HS communication P15 SCK4 ASCK0 99 Unnecessary Unnecessary Unnecessary Unnecessary VDD 38 VDD 38 VDD 38 EVDD 6 EVDD 6 EVDD 6 BVDD 5 BVDD 5 BVDD 5 VDD VDD voltage generation power supply monitoring AVDD 7...

Page 528: ...F3037H PD70F3037HY µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Note The V850 SB1 and V850 SB2 cannot be supplied with the clock from the CLK pin of the flash programmer PG FP3 Supply a clock by creating an oscillator on the flash writing adapter broken line portion An example of the oscillator is shown below REGC X1 X2 1 F µ Remarks 1 Handle the pins not described above in accordance with the recommen...

Page 529: ...ary Unnecessary Unnecessary Unnecessary Unnecessary RESET Output Reset signal RESET 34 RESET 34 RESET 34 VPP Output Writing voltage IC VPP 21 IC VPP 21 IC VPP 21 HS Input Handshake signal of CSI0 HS communication P15 SCK4 ASCK0 2 Unnecessary Unnecessary Unnecessary Unnecessary VDD 41 VDD 41 VDD 41 EVDD 9 EVDD 9 EVDD 9 BVDD 8 BVDD 8 BVDD 8 VDD VDD voltage generation power supply monitoring AVDD 74 ...

Page 530: ... flash programmer UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850 SB1 or V850 SB2 to perform writing erasing etc A dedicated program adapter FA Series required for off board writing 18 4 Communication Mode The communication between the dedicated flash programmer and the V850 SB1 or V850 SB2 is performed by serial communication using UART0 or CSI0 of the ...

Page 531: ...al clock Up to 1 MHz MSB first Figure 18 6 Communication with Dedicated Flash Programmer CSI0 HS V850 SB1 V850 SB2 RESET VSS VDD VPP Dedicated flash programmer SO0 SI0 VPP VDD GND RESET SI SO SCK0 SCK P15 HS The dedicated flash programmer outputs the transfer clock and the V850 SB1 and V850 SB2 operate as slaves When the PG FP3 is used as the dedicated flash programmer it generates the following s...

Page 532: ...VDD I O VDD voltage generation voltage monitoring VDD GND Ground VSS CLKNote Output Clock output to V850 SB1 V850 SB2 X1 RESET Output Reset signal RESET SI RxD Input Receive signal SO0 TxD0 SO TxD Output Transmit signal SI0 RxD0 SCK Output Transfer clock SCK0 HS Input Handshake signal of CSI0 HS P15 Note Supply clocks on the target board Remark Always connected Does not need to be connected if gen...

Page 533: ...ledge the output high impedance status 18 5 1 VPP pin In the normal operation mode 0 V is input to the VPP pin In the flash memory programming mode a 7 8 V write voltage is supplied to the VPP pin The following shows an example of the connection of the VPP pin Figure 18 7 VPP Pin Connection Example VPP Dedicated flash programmer connection pin Pull down resistor RVPP V850 SB1 V850 SB2 18 5 2 Seria...

Page 534: ...olate the connection to the other device or set the other device to the output high impedance status Figure 18 8 Conflict of Signals Serial Interface Input Pin V850 SB1 V850 SB2 Other device Output pin Conflict of signals Input pin In the flash memory programming mode the signal that the dedicated flash programmer sends out conflicts with signals another device outputs Therefore isolate the signal...

Page 535: ... so that the input signal to the other device is ignored Figure 18 9 Malfunction of Other Device V850 SB1 V850 SB2 Pin In the flash memory programming mode if the signal the V850 SB1 or V850 SB2 outputs affects the other device isolate the signal on the other device side Other device Input pin Dedicated flash programmer connection pin V850 SB1 V850 SB2 Pin In the flash memory programming mode if t...

Page 536: ...f signals In the flash memory programming mode the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs Therefore isolate the signals on the reset signal generator side Dedicated flash programmer connection pin 18 5 4 Port pins including NMI When the flash memory programming mode is set all the port pins except the pins that communicate with th...

Page 537: ...18 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Figure 18 11 Procedure for Manipulating Flash Memory Supplies RESET pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End No Yes End Start ...

Page 538: ... set the V850 SB1 or V850 SB2 in the flash memory programming mode When switching modes set the VPP pin before releasing reset When performing on board writing change modes using a jumper etc Figure 18 12 Flash Memory Programming Mode VPP RESET Flash memory programming mode 7 8 V 3 V 0 V 1 2 n VPP Operation Mode 0 V Normal operation mode 7 8 V Flash memory programming mode ...

Page 539: ...CSI0 HS V850 SB1 and V850 SB2 perform slave operation MSB first 8 UART0 Communication rate 9600 bps at reset LSB first Others RFU Setting prohibited Caution When UART0 is selected the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the VPP pulse 18 6 4 Communication command The V850 SB1 and V850 SB2 communicate with the dedicated flas...

Page 540: ...ommand executed immediately before and executes a verify check Status read out command Acquires the status of operations Oscillating frequency setting command Sets the oscillation frequency Erasing time setting command Sets the erasing time of one shot erase Writing time setting command Sets the writing time of data write Writeback time setting command Sets the writeback time Baud rate setting com...

Page 541: ...ll unit broadcasting communication Broadcasting communication to all units 3 Effective transfer rate The effective transfer rate is in mode 1 the V850 SB2 does not support modes 0 and 2 for the effective transfer rate Mode 1 Approx 17 Kbps Caution Different modes must not be mixed on one IEBus 4 Communication mode Data transfer is executed in half duplex asynchronous communication mode 5 Access co...

Page 542: ...cation type is the same communication with the lower master address takes precedence A master address consists of 12 bits with unit 000H having the highest priority and unit FFFH having the lowest priority 19 1 3 Communication mode Although the IEBus has three communication modes each having a different transfer rate the V850 SB2 supports only communication mode 1 The transfer rate and the maximum...

Page 543: ...e plural slave units exist the slave units do not return an acknowledge signal during communication Whether broadcasting communication or normal communication is to be executed is selected by broadcasting bit for this bit refer to 19 1 6 2 Broadcasting bit Broadcasting communication is classified into two types group unit broadcasting communication and all unit broadcasting communication Group uni...

Page 544: ... complete the unit starts outputting the broadcasting bit in synchronization with the completion of the start bit output by the other unit The units other than the one that has started communication detect this start bit and enter the reception status 2 Broadcasting bit This bit indicates whether the master selects one slave individual communication or plural slaves broadcasting communication as t...

Page 545: ... the data on the bus as a result of comparison it is assumed that the master has lost in arbitration As a result the master stops transmission and enters the reception status Because the IEBus is configured of wired AND the unit having the minimum master address of the units participating in arbitration arbitration masters wins in arbitration After a 12 bit master address has been output only one ...

Page 546: ...e address is FFFH All unit broadcasting communication If slave address is other than FFFH Group unit broadcasting communication Remark The group No during group unit broadcasting communication is the value of the higher 4 bits of the slave address If one unit occupies the bus as the master the address set by the slave address register SAR is output Figure 19 3 Slave Address Field Slave address fie...

Page 547: ...and locksNote 2 1 0 1 1 Writes data and locksNote 2 1 1 0 0 Undefined 1 1 0 1 Undefined 1 1 1 0 Writes command 1 1 1 1 Writes data Notes 1 The telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 MSB If bit 3 is 1 Transfer from master unit to slave unit If bit 3 is 0 Transfer from slave unit to master uni...

Page 548: ...ds lock address lower 8 bits 0 0 0 1 Reads lock address higher 4 bits Moreover units for which lock is not set by the master unit reject acknowledgment and do not output an acknowledge bit when the control data shown in Table 19 4 is acknowledged Table 19 4 Control Field for Unlocked Slave Unit Bit 3 Bit 2 Bit 1 Bit 0 Function 0 1 0 0 Lock address read lower 8 bits 0 1 0 1 Lock address read higher...

Page 549: ...ation 0 Broadcasting communication 1 Communication Target SLVRQ Slave Specification 1 No Specification 0 Lock Status LOCK Lock 1 Unlock 0 Master Unit Identification Match with PAR Lock Request Unit 1 Other 0 Slave Transmission Enable ENSLVTX Slave Reception Enable ENSLVRX 0H 3H 4H 5H 6H 7H 0 0 1 don t care don t care 0 1 1 1 1 don t care Other than above Caution If the received control data is oth...

Page 550: ...ster unit and the synchronization signals of bits are output by the master unit When the slave unit detects that the parity is even it outputs the acknowledge signal and starts outputting the data field During broadcasting communication however the slave unit does not output the acknowledge signal If the parity is odd the slave unit judges that the telegraph length bit has not been correctly recei...

Page 551: ...e configuration of the data field is as shown below Figure 19 6 Data Field Data field number specified by telegraph length field MSB LSB One data ACK Parity Control bit 8 bits ACK Parity Following the data bit the parity bit and acknowledge bit are respectively output by the master unit and slave unit Use broadcasting communication only for when the master unit transmits data At this time the ackn...

Page 552: ...ng broadcasting communication the slave unit judges that reception has not been performed correctly and stops reception b When master receives data When the master unit reads data from a slave unit the master unit outputs a sync signal corresponding to all the read bits The slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit Th...

Page 553: ...f the following cases and transmission is stopped If the parity of the control bit is incorrect If control bit 3 is 1 write operation when the slave reception enable flag ENSLVRX is not set 1 Note If the control bit indicates reading of data 3H or 7H when the slave transmission enable flag ENSLVTX is not set 1 Note If a unit other than that has set locking requests 3H 6H 7H AH BH EH or FH of the c...

Page 554: ... the IEBus data register DR and no more data can be received Note Note In this case when the communication executed is individual communication if the maximum number of transmit bytes is within the value that can be transmitted in one frame the transmission side executes transmission of that data field again For broadcasting communication the transmission side does not execute transmission again a...

Page 555: ...ter DR Bit 2 Meaning 0 Unit is not locked 1 Unit is locked Bit 3 Meaning 0 Fixed to 0 Bit 4Note 3 Meaning 0 Slave transmission is stopped 1 Slave transmission is ready Bit 5 Meaning 0 Fixed to 0 Bit 7 Bit 6 Meaning 0 0 Mode 0 0 1 Mode 1 1 0 Mode 2 1 1 Not used Indicates the highest mode supported by unitNote 4 Notes 1 After reset Bit 0 is set to 1 2 The receive buffer size is 1 byte 3 When the V85...

Page 556: ...r than the one that has locked the unit does not receive broadcasting communication A unit is locked or unlocked as follows a Locking If the communication frame is completed without succeeding to transmit or receive data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received ACK 0 by the control bit that specifies locking 3H A...

Page 557: ... to the maximum number of transfer bytes without being output 19 1 8 Bit format The format of the bits constituting the communication frame of the IEBus is shown below Figure 19 9 Bit Format of IEBus Logic 1 Logic 0 Preparation period Synchronization period Data period Stop period Preparation period First low level logic 1 period Synchronization period Next high level logic 0 period Data period Pe...

Page 558: ...rator Contention detection ACK generation Parity generation error detection TX RX Interrupt controller Interrupt control block INT request CPU interface block Internal registers handler DMA transfer IEBus interface block CLK Bit processing block Field processing block Internal bus R W PSR 8 bits 8 5 8 12 12 12 Internal bus 8 12 1 Hardware configuration and function The IEBus mainly consists of the...

Page 559: ...l registers refer to 19 3 Internal Registers of IEBus Controller d Bit processing block This block generates and disassembles bit timing and mainly consists of a bit sequence ROM 8 bit preset timer and comparator e Field processing block This block generates each field in the communication frame and mainly consists of a field sequence ROM 4 bit down counter and comparator f IEBus interface block T...

Page 560: ...r SAR R W FFFFF3E6H IEBus partner address register PAR R 0000H FFFFF3E8H IEBus control data register CDR FFFFF3EAH IEBus telegraph length register DLR 01H FFFFF3ECH IEBus data register DR R W FFFFF3EEH IEBus unit status register USR R FFFFF3F0H IEBus interrupt status register ISR R W 00H FFFFF3F2H IEBus slave status register SSR 41H FFFFF3F4H IEBus communication success counter SCR 01H FFFFF3F6H I...

Page 561: ... as the master writing to the BCR register including bit manipulation instructions is disabled until either the end of that communication or frame or until communication is stopped by the occurrence of an arbitration loss communication error Master requests cannot therefore be multiplexed However if the IEBus is specified as a slave while a master request is being held pending the BCR can be writt...

Page 562: ... should be resent by software following a loss in arbitration When resending the master request in this case set 1 the MSTRQ flag after securing the required wait period This flag is unable to be set 1 before the end of this wait period INTIE2 interrupt signal Start interrupt generation Forcible reset period Wait period 61 7 s MAX µ MSTRQ flag reset signal 2 When a master request has been sent and...

Page 563: ...d and communication continued when the control data of a slave status request is returned even if the ENSLVTX flag is in the reset status e Slave reception enable flag ENSLVRX Bit 3 Set reset conditions Set By software Reset By software Caution If the ENSLVRX flag is reset when the IEBus is busy with other CPU processing NACK will be returned via the acknowledge bit of the control field making it ...

Page 564: ... to 0 15 0 14 0 13 0 12 0 UAR 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E2H After reset 0000H R W R W 3 IEBus slave address register SAR During master request the value of this register is reflected in the value of the transmit data in the slave address field This register must be always set before starting communication Sets the slave address 12 bits to bits 11 to 0 15 0 14 0 13 0 12 0 SAR 11 10 9 ...

Page 565: ...is register and write the data of the higher 4 bits to DR Sets the partner address 12 bits to bits 11 to 0 15 0 14 0 13 0 12 0 PAR 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E6H After reset 0000H R W R 5 IEBus control data register CDR a When master unit The data of the lower 4 bits is reflected in the data transmitted in the control field During master request this register must be set in advance be...

Page 566: ...tes command 1 1 1 1 Writes data Cautions 1 Because the slave unit must judge whether the received data is a command or data it must read the value of this register after completing communication 2 If the master unit sets an undefined value NACK is returned from the slave unit and communication is aborted During broadcasting communication however the master unit continues communication without reco...

Page 567: ...than the unit that sent the lock request ACK returned 5 If 6H control data was received in the locked state from other than the unit that sent the lock request ACK not returned In all of the above cases the acknowledgment of a slave status or lock request will cause the STATUSF flag bit 4 of the ISR register to be set and the status interrupt INTIE2 to be generated The generation timing is at the ...

Page 568: ...IEBus unit is the communication target The STATUSF flag bit 4 of the ISR register is set and the status interrupt INTIE2 generated however if a slave status or lock address request is acknowledged Note that even if the same control data is received while the IEBus is in the locked state the interrupt generation timing for INTIE2 differs depending on whether the master unit 3 or another unit 4 is r...

Page 569: ...ster transmission slave transmission The data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data This register must be set in advance before transmission b When reception unit Master reception slave reception The receive data in the telegraph length field transmitted from the transmission unit is written to thi...

Page 570: ...1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 256 bytes Cautions 1 If the master issues a request 0H 4H 5H or 6H to transmit a slave status and lock address higher 4 bits lower 8 bits the contents of this register are set to 01H by hardware therefore the CPU does not have to set this register 2 In the case of defeat in a bus conflict and a slave status request is received from the unit that won DLR is fixed...

Page 571: ...es the IEBus data register value However when the last byte and 32nd byte the last byte of 1 communication frame is stored in the shift register INTIE1 is not issued b When reception unit One byte of the data received by the shift register of the IEBus interface block is stored to this register Each time 1 byte has been correctly received an interrupt INTIE1 is issued When transmit receive data is...

Page 572: ... flag indicating whether there has been a slave request from the master Set reset conditions Set When the unit is requested as a slave if the received slave address and unit UAR match during individual communication reception or if the higher 4 bits of the received slave address match or if the received slave address is FFFH during broadcasting communication reception this flag is set by hardware ...

Page 573: ...rforming broadcasting communication The contents of the flag are updated in the broadcast field of each frame Except for initialization reset by system reset the set reset conditions vary depending on the receive data of the broadcast field bit Set reset conditions Set When broadcasting is received by the broadcast field Reset When individual is received by the broadcast field or upon the input of...

Page 574: ...control field Reset When the communication enable flag is cleared When the communication end flag is set after receipt of a lock release 3H 6H AH BH in the control field Caution Lock specification release is not possible in broadcasting communication In the lock status individual communication from a unit other than the one that requests locking is not acknowledged However even communication from ...

Page 575: ... each flag satisfying the reset conditions in Table 19 8 Table 19 8 Reset Conditions of Flags in ISR Register Flag Name Reset Condition Processing Example IEERR STARTF STATUSF Byte write operation of ISR register Any value can be written ISR 00H etc ENDTRNS ENDFRAM Set MSTRQ ENSLVTX or ENSLVRX flag BCR register 88H or ENSLVTX 1 etc Caution Even if 0 is written to the ENDTRNS or ENDFRAM flag by acc...

Page 576: ...munication does not end after the number of bytes set in the telegraph length field have been transferred 1 Communication ends after the number of bytes set in the telegraph length field have been transferred ENDFRAM Frame end flag 0 The frame transfer of the maximum number of bytes 32 bytes prescribed by mode 1 does not end 1 The frame transfer of the maximum number of bytes 32 bytes prescribed b...

Page 577: ...rom the unit requesting a lock Reset By software c Status transmission flag STATUSF Bit 4 A flag indicating that the transmission status is either the master to slave status or the lock address higher 4 bits lower 8 bits when IEBus is a slave unit Set reset conditions Set When 0H 4H 5H or 6H is received in the control field from the master when the IEBus is a slave unit Reset By software d Communi...

Page 578: ...r a slave unit A NACK reception error only occurs in individual communication ACK and NACK are not discriminated in broadcasting communication Remark An interrupt is generated if NACK is received in a field other than the data field Underrun Occurrence conditions Occurs during data transmission if there was insufficient time to write the next transmit data to the IEBus data register DR before ACK ...

Page 579: ...t starts in the overrun state the cause of the overrun NACK is not returned in the ACK period of the slave address control or telegraph length field the DR register is not updated If the next communication is not to the IEBus unit the DR register is not updated until it is read Because the IEBus unit is not a communication target the data interrupt INTIE1 and communication error interrupt INTIE2 a...

Page 580: ...e fixed to 01H mode 1 After reset 41H R Address FFFFF3F2H 7 6 5 4 3 2 1 0 SSR 0 1 0 STATSLV 0 STATLOCK STATRX STATTX STATSLV Slave transmission status flag 0 Slave transmission stops 1 Slave transmission enabled STATLOCK Lock status flag 0 Unlock status 1 Lock status STATRX DR receive status 0 Receiving data not stored in DR 1 Receiving data stored in DR STATTX DR transmit status 0 Transmission da...

Page 581: ... Address FFFFF3F4H 7 6 5 4 3 2 1 0 SCR Bit 7 6 5 4 3 2 1 0 Setting value Remaining number of communication data bytes 0 0 0 0 0 0 0 1 01H 1 byte 0 0 0 0 0 0 1 0 02H 2 bytes 0 0 1 0 0 0 0 0 20H 32 bytes 1 1 1 1 1 1 1 1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 0 byte end of communication or 256 bytesNote Note The actual hard counter consists of 9 bits When 00H is read it cannot be judged whether the remain...

Page 582: ... whether ACK or NACK When the count value has reached 00H the frame end flag ENDFRAM is set The maximum number of transfer bytes of the preset value of mode 1 per frame is 20H 32 bytes After reset 20H R Address FFFFF3F6H 7 6 5 4 3 2 1 0 CCR 13 IEBus clock selection register IECLK This register selects the clock of IEBus The main clock frequencies that can be used are shown below Main clock frequen...

Page 583: ...z 6 291 MHz 12 0 MHz 12 582 MHz 18 0 MHz 18 873 MHz Caution The IEHCLK register is available only in the H versions of the V850 SB2 µ µ µ µPD703036H 703036HY 70F3036H 70F3036HY 703037H 703037HY 70F3037H and 70F3037HY After reset 00H R W Address FFFFF3DEH 7 6 5 4 3 2 1 0 IEHCLK 0 0 0 0 0 0 0 IECS1 IECS1 IECSNote IEBus clock selection 0 0 fXX 6 0 MHz or fXX 6 291 MHz 0 1 fXX 12 0 MHz or fXX 12 582 M...

Page 584: ... 5 of the above interrupt requests are assigned to the interrupt status register ISR For details refer to Table 19 9 Interrupt Source List The configuration of the interrupt control block is illustrated below Figure 19 16 Configuration of Interrupt Control Block IEERR STARTF STATUSF ENDTRNS ENDFRAM STATTX STATRX IEBus macro Interrupt control block V850 SB2 CPU INTIE1 INTIE2 Cautions 1 OR output of...

Page 585: ...nt Contention judgment If loses remaster processing Communication preparation processing Interrupt always occurs if loses in contention during master request Start interrupt Slave Slave address Slave request judgment Communication preparation processing Generated only during slave request Status transmission Slave Control Refer to transmission processing example such as slave status Interrupt occu...

Page 586: ...g Reception stops INTIE2 occurs NACK is returned To start bit waiting status Transmission stops INTIE2 occurs To start bit waiting status Individual communication Software processing Error processing such as retransmission request Error processing such as retransmission request NACK Reception Error Unit status Reception Transmission Occurrence condition Unit NACK transmission Unit NACK transmissio...

Page 587: ...g INTIE2 does not occur NACK is returned Data is retransmitted from other unit Remark Data cannot be received until overrun status is cleared Transmission stops INTIE2 occurs To start bit waiting status Individual communication Software processing DR is read and overrun status is cleared Error processing such as retransmission request Error processing such as retransmission request Parity Error Un...

Page 588: ...ode 1 µ µ 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave reception processing See 19 5 1 1 Slave reception processing Judgment of contention result Remaster request processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end ...

Page 589: ... is received from the slave in the data field an interrupt INTIE1 is not issued to the CPU and the same data is retransmitted by hardware If the transmit data is not written in time during the period of writing the next data a communication error interrupt occurs due to occurrence of underrun and communication ends midway 3 Recommunication processing The vector interrupt processing in 2 judges whe...

Page 590: ...rt Broad casting M address P S address P A Control A P Telegraph length A P Data 1 Approx 390 s mode 1 µ Data 1 P A Data 2 P A Data n 1 P A Data n P A 2 1 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave processing Judgment of collision result Remaster request processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Erro...

Page 591: ...ave If the receive data is not read in time until the next data is received the hardware automatically transmits NACK 2 Frame end processing The vector interrupt processing in 2 judges whether the data has been correctly received within one frame If the data has not been correctly received if the number of data to be received in one frame could not be received a request to retransmit the data must...

Page 592: ... Judgment of slave request 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end of frame Frame end processing See 19 5 3 2 Frame end processing Remarks 1 Interrupt INTIE1 occurrence See 19 5 3 1 Interrupt INTIE1 occurrence The transmit data of the second byte and those that follow are written...

Page 593: ...he period of writing the next data a communication error interrupt occurs due to occurrence of underrun and communication is abnormally ended 2 Frame end processing The vector interrupt processing in 2 judges whether the data has been correctly transmitted within one frame If the data has not been correctly transmitted if the number of data to be transmitted in one frame could not be transmitted t...

Page 594: ... s mode 1 µ µ Broad casting Telegraph length 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave processing 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end of frame Frame end processing See 19 5 4 2 Frame end processing Remarks 1...

Page 595: ...field an interrupt INTIE1 is not issued to the CPU and the same data is retransmitted from the master If the receive data is not read in time until the next data is received NACK is automatically transmitted 2 Frame end processing The vector interrupt processing in 2 judges whether the data has been correctly received within one frame ...

Page 596: ...e following interrupt does not occur in that communication frame 1 Master transmission Figure 19 21 Master Transmission Interval of Interrupt Occurrence Start bit T t1 T Broad casting Master address T t2 P Slave address T P A A T T t3 Control P A A t4 T A T Telegraph length P A Data P A Communication starts Communication start interrupt P A Data Data A P Data T T t4 End of communication End of fra...

Page 597: ... of frame Communication start interrupt T T T T T A T t4 t4 t5 t2 A P T A t3 Remarks 1 T Timing error P Parity error A ACK error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 93 µs Communication starts communication start interrupt t2 Approx 1282 µs Communication start interrupt timing e...

Page 598: ... Control Data Telegraph length Remarks 1 T Timing error P Parity error A ACK error U Underrun error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 96 µs Communication starts communication start interrupt t2 Approx 1192 µs Communication start interrupt timing error t3 Approx 15 µs Communic...

Page 599: ...ts Broad casting Master address Slave address Control Data Telegraph length Remarks 1 T Timing error P Parity error A ACK error O Overrun error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item Symbol MIN Unit Communication starts timing error t1 Approx 96 µs Communication starts communication start interrupt t2 Approx 1192 µs Communication start int...

Page 600: ...VDD 0 5Note 5 V Per pin 4 0 mA Total for P00 to P07 P10 to P15 P20 to P25 25 mA Total for P26 P27 P30 to P37 P100 to P107 P110 to P113 25 mA Total for P40 to P47 P90 to P96 CLKOUT 25 mA Output current low IOL Total for P50 to P57 P60 to P65 25 mA Per pin 4 0 mA Total for P00 to P07 P10 to P15 P20 to P25 25 mA Total for P26 P27 P30 to P37 P100 to P107 P110 to P113 25 mA Total for P40 to P47 P90 to ...

Page 601: ...and 70F3033AY P rank products of the µPD70F3035A and 70F3035AY and the µPD70F3032A 70F3032AY 70F3037A 70F3037AY 70F3030B 70F3030BY 70F3032B 70F3032BY 70F3033B 70F3033BY 70F3035B 70F3035BY 70F3036H 70F3036HY 70F3037H and 70F3037HY The rank is indicated by the letter appearing as the 5th digit from the left in the lot number Cautions 1 Do not directly connect the output or I O pins of IC products to...

Page 602: ... 5 to 5 5 V 4 0 to 5 5 V 3 0 to 5 5 V 3 0 to 5 5 V 2 to 13 MHz A and B versions of V850 SB2 4 0 to 5 5 V 4 5 to 5 5 V 4 0 to 5 5 V 3 0 to 5 5 V 3 0 to 5 5 V Note 3 Other than IDLE mode 4 0 to 5 5 V 4 5 to 5 5 V 4 0 to 5 5 V 3 0 to 5 5 V 3 0 to 5 5 V 32 768 kHz IDLE mode 3 5 to 5 5 V 4 0 to 5 5 V 3 0 to 5 5 V 3 0 to 5 5 V Note 4 Notes 1 When A D converter is used 2 When A D converter is not used 3 ...

Page 603: ... on the output voltage of the on chip regulator 3 0 V 3 3 V for details refer to CHAPER 16 REGULATOR External clock input is prohibited 2 When using the main clock oscillator wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines D...

Page 604: ... On chip On chip 0 4 0 5 5 CSTCV12M5T54J R0 12 5 On chip On chip 0 4 0 5 5 CSALS16M0X55 B0 10 10 0 4 0 5 5 CSTCV16M0X51J R0 16 00 On chip On chip 0 4 0 5 5 CSTLS20M0X51 B0 On chip On chip 0 4 0 5 5 Murata Mfg Co Ltd V850 SB1 CSTCW20M0X51 R0 20 00 On chip On chip 22 k 0 4 0 5 5 Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator ma...

Page 605: ... When using the subclock oscillator wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator cap...

Page 606: ...5 V VOH1 Note 1 CLKOUT 4 0 V BVDD 5 5 V IOH 3 mA BVDD 1 0 V 3 0 V EVDD 5 5 V IOH 100 µA EVDD 0 5 V Output voltage high VOH2 Notes 2 3 4 0 V EVDD 5 5 V IOH 3 mA EVDD 1 0 V IOL 3 mA 3 0 V BVDD EVDD 5 5 V 0 5 V Output voltage low VOL IOL 3 mA 4 0 V BVDD EVDD 5 5 V 0 4 V Normal operation A and B versions of V850 SB2 0 0 54 V VPP power supply voltage VPP1 Normal operation V850 SB1 and H versions of V85...

Page 607: ...Note 9 70 µA IDD5 In normal operation mode subclock operation Note 5 50 150 µA Supply current µPD703034A 703034AY 703034B 703034BY 703035A 703035AY 703035B 703035BY 703037A 703037AY IDD6 In IDLE mode subclock operation Note 5 13 70 µA Notes 1 fCPU fXX 20 MHz all peripheral functions operating fXX 19 MHz in the µPD703036H 703036HY 703037H and 703037HY 2 fXX 20 MHz fXX 19 MHz in the µPD703036H 70303...

Page 608: ...032B 70F3032BY 70F3033A 70F3033AY 70F3033B 70F3033BY 70F3036H 70F3036HY 70F3037H 70F3037HY IDD6 In IDLE mode subclock operation Note 8 Note 4 170 340 µA Notes 1 fCPU fXX 20 MHz all peripheral functions operating fXX 19 MHz in the µPD70F3036H 70F3036HY 70F3037H and 70F3037HY 2 µPD70F3033A 70F3033AY 70F3033B 70F3033BY 3 µPD70F3030B 70F3030BY 70F3036H 70F3036HY 4 µPD70F3032A 70F3032AY 70F3032B 70F303...

Page 609: ...topped XT1 VSS Note 6 100 µA Note 2 200 600 µA IDD5 In normal operation mode subclock operation Note 7 Note 3 300 900 µA Note 2 90 180 µA Supply current µPD70F3035A 70F3035AY 70F3035B 70F3035BY 70F3037A 70F3037AY IDD6 In IDLE mode subclock operation Note 7 Note 3 170 340 µA Notes 1 fCPU fXX 13 MHz all peripheral functions operating 2 µPD70F3035A 70F3035AY 70F3035B 70F3035BY 3 µPD70F3037A 70F3037AY...

Page 610: ...Power supply voltage hold time from STOP mode setting tHVD 0 ms STOP mode release signal input time tDREL 0 ms Data retention high level input voltage VIHDR All input ports 0 9VDDDR VDDDR V Data retention low level input voltage VILDR All input ports 0 0 1VDDDR V Notes 1 In STOP mode when only watch timer is operating VDD 3 5 to 5 5 V Shifting to STOP mode or restoring from STOP mode must be perfo...

Page 611: ... for when TA 25 C tHVD VDDDR tDREL VIHDR VIHDR tFVD tRVD VDD Stop mode release interrupt NMI etc Release by falling edge Stop mode release interrupt NMI etc Release by rising edge Setting STOP mode RESET input VILDR 4 0 VNote Note VDD 4 0 V indicates the minimum operating voltage of the V850 SB1 and V850 SB2 ...

Page 612: ... EVSS 0 V AC Test Input Measurement Point VDD EVDD BVDD AVDD VDD 0 V VIH VIL VIH VIL Measurement points Input signal AC Test Output Measurement Points VDD EVDD BVDD VOH VOL VOH VOL Measurement points Output signal VDD 0 V Load Conditions DUT Device under test CL 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration bring the load capacitance of the device to 50 pF or...

Page 613: ... 2 tWKH 0 4tCYK 12 ns CLKOUT low level width 3 tWKL 0 4tCYK 12 ns CLKOUT rise time 4 tKR 12 ns CLKOUT fall time 5 tKF 12 ns b TA 40 to 85 C VDD 4 0 to 5 5 V BVDD 3 0 to 4 0 V EVDD 3 0 to 5 5 V VSS AVSS BVSS EVSS 0 V Parameter Symbol Conditions MIN MAX Unit V850 SB1 58 8 ns 31 2 µs H versions of V850 SB2 58 8 ns 31 2 µs CLKOUT output cycle 1 tCYK A and B versions of V850 SB2 76 9 ns 31 2 µs CLKOUT ...

Page 614: ...3 0 to 5 5 V VSS BVSS EVSS 0 V Parameter Symbol Conditions MIN MAX Unit Output rise time 6 tOR 20 ns Output fall time 7 tOF 20 ns 7 6 Output signal 3 Reset timing TA 40 to 85 C VDD 4 0 to 5 5 V BVDD EVDD 3 0 to 5 5 V VSS AVSS BVSS EVSS 0 V Parameter Symbol Conditions MIN MAX Unit RESET pin high level width 8 tWRSH 500 ns RESET pin low level width 9 tWRSL 500 ns 8 9 RESET input ...

Page 615: ...time from DSTB 22 tDDOD 10 ns Data output setup time to DSTB 23 tSODD 1 n T 25 ns Data output hold time from DSTB 24 tHDOD T 20 ns 25 tSAWT1 n 1 1 5T 40 ns WAIT setup time to address 26 tSAWT2 n 1 1 5 n T 40 ns 27 tHAWT1 n 1 0 5 n T ns WAIT hold time from address 28 tHAWT2 n 1 1 5 n T ns 29 tSSTWT1 n 1 T 32 ns WAIT setup time to ASTB 30 tSSTWT2 n 1 1 n T 32 ns 31 tHSTWT1 n 1 nT ns WAIT hold time f...

Page 616: ...s 27 tHAWT1 n 1 0 5 n T ns WAIT hold time from address 28 tHAWT2 n 1 1 5 n T ns 29 tSSTWT1 n 1 T 45 ns WAIT setup time to ASTB 30 tSSTWT2 n 1 1 n T 45 ns 31 tHSTWT1 n 1 nT ns WAIT hold time from ASTB 32 tHSTWT2 n 1 1 n T ns HLDRQ high level width 33 tWHQH T 10 ns HLDAK low level width 34 tWHAL T 25 ns Bus output delay time from HLDAK 35 tDHAC 6 ns Delay time from HLDRQ to HLDAK 36 tDHQHA1 2n 7 5 T...

Page 617: ... 50 tDKHA 19 ns Remark The values in the above specifications are values for when clocks with a 5 5 duty ratio are input from X1 d Clock synchronous TA 40 to 85 C VDD 4 0 to 5 5 V BVDD 3 0 to 4 0 V EVDD 3 0 to 5 5 V VSS AVSS BVSS EVSS 0 V Parameter Symbol Conditions MIN MAX Unit Delay time from CLKOUT to address 38 tDKA 0 22 ns Delay time from CLKOUT to address float 39 tFKA 16 10 ns Delay time fr...

Page 618: ... output ASTB output T1 T2 TW 38 15 20 45 DSTB RD output WAIT input AD0 to AD15 I O 39 10 43 40 T3 42 13 21 16 14 19 17 18 41 12 29 31 25 27 26 28 30 46 45 46 Data Address 40 11 41 32 A1 to A15 output A16 to A21 output Note output Note R W UBEN LBEN Remarks 1 The broken lines indicate high impedance 2 WRL and WRH are high level ...

Page 619: ...wait CLKOUT output ASTB output T1 T2 TW 38 15 20 45 A1 to A15 output A16 to A21 output Note output DSTB WRL WRH output WAIT input AD0 to AD15 I O 44 10 40 T3 21 23 24 18 41 22 29 31 25 27 26 28 30 46 45 46 Data Address 40 11 41 32 Note R W UBEN LBEN Remarks 1 The broken lines indicate high impedance 2 RD is high level ...

Page 620: ... hold timing CLKOUT output TH A1 to A15 output 47 48 TH TH TH TI 47 36 50 50 34 37 33 49 35 A16 to A21 output Note output HLDRQ input HLDAK output ASTB output DSTB RD output WRL WRH output AD0 to AD15 I O Data Note R W UBEN LBEN Remark The broken lines indicate high impedance ...

Page 621: ...level width 52 tWNIL 500 ns n 0 to 3 analog noise elimination 500 ns n 4 5 digital noise elimination 3T 20 ns INTPn high level width 53 tWITH n 6 digital noise elimination 3Tsmp 20 ns n 0 to 3 analog noise elimination 500 ns n 4 5 digital noise elimination 3T 20 ns INTPn low level width 54 tWITL n 6 digital noise elimination 3Tsmp 20 ns Remarks 1 T 1 fXX 2 Tsmp Noise elimination sampling clock cyc...

Page 622: ...ks by setting the PRMn2 to PRMn0 bits of prescaler mode registers n0 n1 PRMn0 PRMn1 When n 0 TM0 Tsam 2T 4T 16T 64T 256T or 1 INTWTNI cycle When n 1 TM1 Tsam 2T 4T 16T 32T 128T or 256T However when the TIn0 valid edge is selected as the count clock Tsam 4T Remark T 1 fXX 55 56 TIn0 TIn1 input 57 58 TIm input Remark n 0 1 m 2 to 5 7 Asynchronous serial interface UART0 UART1 timing TA 40 to 85 C VDD...

Page 623: ...meter Symbol Conditions MIN MAX Unit SCKn cycle 62 tKCY2 400 ns SCKn high level width 63 tKH2 140 ns SCKn low level width 64 tKL2 140 ns SIn setup time to SCKn 65 tSIK2 50 ns SIn hold time from SCKn 66 tKSI2 50 ns Note 1 60 ns Delay time from SCKn to SOn output 67 tKSO2 4 0 V EVDD 5 5 V Note 2 70 ns 3 0 V EVDD 4 0 V 100 ns Notes 1 µPD703031A 703031AY 703031B 703031BY 703033A 703033AY 703033B 70303...

Page 624: ...CHAPTER 20 ELECTRICAL SPECIFICATIONS User s Manual U13850EJ6V0UD 624 66 67 65 62 63 64 Remarks 1 The broken lines indicate high impedance 2 n 0 to 3 SCKn I O SIn input SOn output Input data Output data ...

Page 625: ...I4 setup time to SCK4 71 tSIK1 3 0 V EVDD 4 0 V 50 ns SI4 hold time from SCK4 72 tKSI1 20 ns Delay time from SCK4 to SO4 output 73 tKSO1 55 ns b Slave mode TA 40 to 85 C VDD 4 0 to 5 5 V BVDD EVDD 3 0 to 5 5 V VSS AVSS BVSS EVSS 0 V Parameter Symbol Conditions MIN MAX Unit 4 0 V EVDD 5 5 V 200 ns SCK4 cycle 68 tKCY2 3 0 V EVDD 4 0 V 400 ns 4 0 V EVDD 5 5 V 60 ns SCK4 high level width 69 tKH2 3 0 V...

Page 626: ...CHAPTER 20 ELECTRICAL SPECIFICATIONS User s Manual U13850EJ6V0UD 626 68 70 69 71 72 73 SI4 input SO4 output SCK4 I O Output data Input data Remark The broken lines indicate high impedance ...

Page 627: ... 83 tSU STO 4 0 0 6 µs Pulse width of spike suppressed by input filter 84 tSP 0 50 ns Capacitance load of each bus line Cb 400 400 pF Notes 1 At the start condition the first clock pulse is generated after the hold time 2 The system requires a minimum of 300 ns hold time internally for the SDAn signal at VIHmin of SCLn signal in order to occupy the undefined area at the falling edge of SCLn 3 If t...

Page 628: ...0 FSR Conversion time tCONV 5 10 µs Zero scale errorNote 1 0 4 FSR ADM2 00H 0 4 FSR Full scale errorNote 1 ADM2 01H 0 6 FSR ADM2 00H 4 0 LSB Integral linearity errorNote 2 ADM2 01H 6 0 LSB ADM2 00H 4 0 LSB Differential linearity errorNote 2 ADM2 01H 6 0 LSB Analog reference voltage AVREF AVREF AVDD 4 5 5 5 V Analog power supply voltage AVDD 4 5 5 5 V Analog input voltage VIAN AVSS AVREF V AVREF in...

Page 629: ...z operation is guaranteed at 6 29 MHz system clock in the V850 SB2 Regulator TA 40 to 85 C VDD 4 0 to 5 5 V VSS 0 V Parameter Symbol Conditions MIN TYP MAX Unit Output stabilization time tREG Stabilization capacitance C 1 µF Connected to REGC pin 1 ms Cautions 1 Be sure to start inputting supply voltage VDD when RESET VSS EVSS BVSS 0 V the above state and make RESET high level after the tREG perio...

Page 630: ...F3033BY IDD 68 µPD70F3030B 70F3030BY IDD 73 µPD70F3032A 70F3032AY 70F3032B 70F3032BY 2 The recommended setting value of the step erase time is 0 2 s 3 The prewrite time prior to erasure and the erase verify time writeback time are not included 4 The recommended setting value of the writeback time is 1 ms 5 Writeback is executed once by the issuance of the writeback command Therefore the retry coun...

Page 631: ...se 1 write after erase 1 rewrite Note 7 Note 8 Count area Notes 1 The recommended setting value of the step erase time is 0 2 s 2 The prewrite time prior to erasure and the erase verify time writeback time are not included 3 The recommended setting value of the writeback time is 1 ms 4 Writeback is executed once by the issuance of the writeback command Therefore the retry count must be the maximum...

Page 632: ...se 1 write after erase 1 rewrite Note 7 Note 8 Count area Notes 1 The recommended setting value of the step erase time is 0 2 s 2 The prewrite time prior to erasure and the erase verify time writeback time are not included 3 The recommended setting value of the writeback time is 1 ms 4 Writeback is executed once by the issuance of the writeback command Therefore the retry count must be the maximum...

Page 633: ...51 µPD70F3035B 70F3035BY IDD 61 µPD70F3037A 70F3037AY 2 The recommended setting value of the step erase time is 0 2 s 3 The prewrite time prior to erasure and the erase verify time writeback time are not included 4 The recommended setting value of the writeback time is 1 ms 5 Writeback is executed once by the issuance of the writeback command Therefore the retry count must be the maximum value min...

Page 634: ...68 µPD70F3036H 70F3036HY IDD 73 µPD70F3037H 70F3037HY 2 The recommended setting value of the step erase time is 0 2 s 3 The prewrite time prior to erasure and the erase verify time writeback time are not included 4 The recommended setting value of the writeback time is 1 ms 5 Writeback is executed once by the issuance of the writeback command Therefore the retry count must be the maximum value min...

Page 635: ...true position T P at maximum material condition ITEM MILLIMETERS A B D G 16 00 0 20 14 00 0 20 0 50 T P 1 00 J 16 00 0 20 K C 14 00 0 20 I 0 08 1 00 0 20 L 0 50 0 20 F 1 00 N P Q 0 08 1 40 0 05 0 10 0 05 S100GC 50 8EU 8EA 2 S 1 60 MAX H 0 22 0 05 0 04 M 0 17 0 03 0 07 R 3 7 3 1 25 26 50 100 76 75 51 S S N J detail of lead end C D A B R K M L P I S Q G F M H ...

Page 636: ...Q R K M L P S S N G F NOTE Each lead centerline is located within 0 15 mm of its true position T P at maximum material condition ITEM MILLIMETERS A B D G 23 6 0 4 20 0 0 2 0 30 0 10 0 6 H 17 6 0 4 I C 14 0 0 2 0 15 J 0 65 T P K 1 8 0 2 L 0 8 0 2 F 0 8 P100GF 65 3BA1 4 N P Q 0 10 2 7 0 1 0 1 0 1 R 5 5 S 3 0 MAX M 0 15 0 10 0 05 C D A B S ...

Page 637: ...D703034AGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD703034BGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD703034AYGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD703034BYGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD703035AGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD703035BGC xxx 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD703035A...

Page 638: ...h 14 14 µ µ µ µPD70F3035BGC 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD70F3035AYGC 8EU 100 pin plastic LQFP fine pitch 14 14 µ µ µ µPD70F3035BYGC 8EU 100 pin plastic LQFP fine pitch 14 14 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count Two times or less Exposure limit 3 daysNote a...

Page 639: ... xxx 3BA 100 pin plastic QFP 14 20 µ µ µ µPD703037AGF xxx 3BA 100 pin plastic QFP 14 20 µ µ µ µPD703037HGF xxx 3BA 100 pin plastic QFP 14 20 µ µ µ µPD703037AYGF xxx 3BA 100 pin plastic QFP 14 20 µ µ µ µPD703037HYGF xxx 3BA 100 pin plastic QFP 14 20 µ µ µ µPD70F3033AGF 3BA 100 pin plastic QFP 14 20 µ µ µ µPD70F3033BGF 3BA 100 pin plastic QFP 14 20 µ µ µ µPD70F3033AYGF 3BA 100 pin plastic QFP 14 20 ...

Page 640: ...4 20 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count Two times or less Exposure limit 3 daysNote after that prebake at 125 C for 20 to 72 hours IR35 203 2 VPS Package peak temperature 215 C Time 25 to 40 seconds at 200 C or higher Count Two times or less Exposure limit 3 daysNote after th...

Page 641: ... Infrared reflow Package peak temperature 230 C Time 30 seconds max at 210 C or higher Count Two times or less Exposure limit 3 daysNote after that prebake at 125 C for 10 hours IR30 103 2 VPS Package peak temperature 215 C Time 25 to 40 seconds at 200 C or higher Count Two times or less Exposure limit 3 daysNote after that prebake at 125 C for 10 hours VP15 103 2 Partial heating Pin temperature 3...

Page 642: ...itch 14 14 Side view Target system NQPACK100SD YQPACK100SD 178 mm Note In circuit emulator option board Conversion connector IE 703037 MC EM1 In circuit emulator IE 703002 MC YQGUIDE Note YQSOCKET100SDN included with IE 703002 MC can be inserted here to adjust the height height 3 2 mm Top view Target system YQPACK100SD NQPACK100SD YQGUIDE IE 703037 MC EM1 IE 703002 MC Pin 1 position Connection con...

Page 643: ...C EM1 In circuit emulator IE 703002 MC YQGUIDE Note YQSOCKET100SDN included with IE 703002 MC to this portion for adjusting the height height 3 2 mm Top view Target system YQPACK100RB NQPACK100RB YQGUIDE IE 703037 MC EM1 IE 703002 MC NEXB 100 SD RB 8 mm 20 mm Pin 1 position Connection condition diagram 33 2 mm 28 mm 18 5 mm 20 mm 38 mm Target system NQPACK100RB YQPACK100RB IE 703037 MC EM1 Connect...

Page 644: ...ister 4 CSI 425 BRGCN4 Baud rate generator source clock selection register 4 CSI 424 BRGMC00 Baud rate generator mode control register 00 UART 405 BRGMC01 Baud rate generator mode control register 01 UART 405 BRGMC10 Baud rate generator mode control register 10 UART 405 BRGMC11 Baud rate generator mode control register 11 UART 405 CCR IEBus communication count register IEBus 582 CDR IEBus control ...

Page 645: ...erial operation mode register 1 CSI 270 CSIM2 Serial operation mode register 2 CSI 270 CSIM3 Serial operation mode register 3 CSI 270 CSIM4 Variable length serial control register 4 CSI 422 CSIS0 Serial clock selection register 0 CSI 270 CSIS1 Serial clock selection register 1 CSI 270 CSIS2 Serial clock selection register 2 CSI 270 CSIS3 Serial clock selection register 3 CSI 270 DBC0 DMA byte coun...

Page 646: ...C 454 DRA4 DMA internal RAM address register 4 DMAC 454 DRA5 DMA internal RAM address register 5 DMAC 454 DWC Data wait control register BCU 132 ECR Interrupt source register CPU 99 EGN0 Falling edge specification register 0 INTC 154 477 EGP0 Rising edge specification register 0 INTC 154 477 EIPC Status saving register during interrupt CPU 99 EIPSW Status saving register during interrupt CPU 99 FE...

Page 647: ...Port 115 NCC Noise elimination control register INTC 167 OSTS Oscillation stabilization time selection register WDT 187 262 267 P0 Port 0 Port 474 P1 Port 1 Port 479 P2 Port 2 Port 483 P3 Port 3 Port 488 P4 Port 4 Port 492 P5 Port 5 Port 492 P6 Port 6 Port 495 P7 Port 7 Port 498 P8 Port 8 Port 498 P9 Port 9 Port 500 P10 Port 10 Port 503 P11 Port 11 Port 507 PAC Port alternate function control regi...

Page 648: ...caler mode register 11 RPU 210 PSC Power save control register CG 186 PSW Program status word CPU 100 PU0 Pull up resistor option register 0 Port 476 PU1 Pull up resistor option register 1 Port 480 PU2 Pull up resistor option register 2 Port 485 PU3 Pull up resistor option register 3 Port 489 PU10 Pull up resistor option register 10 Port 505 PU11 Pull up resistor option register 11 Port 509 RTBH R...

Page 649: ...lock selection register 40 Timer 237 TCL41 Timer clock selection register 41 Timer 237 TCL50 Timer clock selection register 50 Timer 237 TCL51 Timer clock selection register 51 Timer 237 TCL60 Timer clock selection register 60 Timer 237 TCL61 Timer clock selection register 61 Timer 237 TCL70 Timer clock selection register 70 Timer 237 TCL71 Timer clock selection register 71 Timer 237 TM0 16 bit ti...

Page 650: ...t control register INTC 162 to 164 TMIC5 Interrupt control register INTC 162 to 164 TMIC6 Interrupt control register INTC 162 to 164 TMIC7 Interrupt control register INTC 162 to 164 TOC0 16 bit timer output control register 0 RPU 208 TOC1 16 bit timer output control register 1 RPU 208 TXS0 Transmit shift register 0 UART 400 TXS1 Transmit shift register 1 UART 400 UAR IEBus unit address register IE...

Page 651: ... lines refer to Table C 2 This column shows instruction operations refer to Table C 3 This column shows flag statuses refer to Table C 4 Operand Opcode Operation Flag OV S Z SAT Table C 1 Symbols in Operand Description Symbol Description reg1 General purpose register r0 to r31 Used as source register reg2 General purpose register r0 to r31 Mainly used as destination register ep Element pointer r30...

Page 652: ...d memory a b Reads data of size b from address a store memory a b c Writes data b of size c to address a load memory bit a b Reads bit b from address a store memory bit a b c Writes c to bit b of address a saturated n Performs saturated processing of n n is 2 s complements Result of calculation of n If n is n 7FFFFFFFH as result of calculation 7FFFFFFFH If n is n 80000000H as result of calculation...

Page 653: ...V 1 Overflow NV 1000 OV 0 No overflow C L 0001 CY 1 Carry Lower Less than NC NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY OR Z 1 Not higher Less than or equal H 1011 CY OR Z 0 Higher Greater than N 0100 S 1 Negative P 1100 S 0 Positive T 0101 Always unconditional SA 1101 SAT 1 Saturated LT 0110 S XOR OV 1 Less than signed...

Page 654: ... rrrrr0111ddddddd adr ep zero extend disp7 Store memory adr GR reg2 Byte SST H reg2 disp8 ep rrrrr1001ddddddd Note 1 adr ep zero extend disp8 Store memory adr GR reg2 Halfword SST W reg2 disp8 ep rrrrr1010dddddd1 Note 2 adr ep zero extend disp8 Store memory adr GR reg2 Word ST B reg2 disp16 reg1 rrrrr111010RRRRR dddddddddddddddd adr GR reg1 sign extend disp16 Store memory adr GR reg2 Byte ST H reg...

Page 655: ...RRRRR result GR reg2 GR reg1 CMP imm5 reg2 rrrrr010011iiiii result GR reg2 sign extend imm5 Arithmetic operation SETF cccc reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H SATADD reg1 reg2 rrrrr000110RRRRR GR reg2 saturated GR reg2 GR reg1 SATADD imm5 reg2 rrrrr010001iiiii GR reg2 saturated GR reg2 sign extend imm5 SATSUB reg1 reg2 rr...

Page 656: ...0101iiiii GR reg2 GR reg2 arithmetically shift right by zero extend imm5 0 JMP reg1 00000000011RRRRR PC GR reg1 JR disp22 0000011110dddddd ddddddddddddddd0 Note 1 PC PC sign extend disp22 JARL disp22 reg2 rrrrr11110dddddd ddddddddddddddd0 Note 1 GR reg2 PC 4 PC PC sign extend disp22 Jump Bcond disp9 ddddd1011dddcccc Note 2 if conditions are satisfied then PC PC sign extend disp9 SET1 bit 3 disp16 ...

Page 657: ... 1FH RETI 0000011111100000 0000000101000000 if PSW EP 1 then PC EIPC PSW EIPSW else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW R R R R R HALT 0000011111100000 0000000100100000 Stops DI 0000011111100000 0000000101100000 PSW ID 1 Maskable interrupt disabled EI 1000011111100000 0000000101100000 PSW ID 0 Maskable interrupt enabled Special NOP 0000000000000000 Uses 1 clock cycle without ...

Page 658: ...ngs 600 AC characteristics 612 Access clock 129 AD0 to AD7 85 AD8 to AD15 85 ADCR 433 ADCRH 433 Address match detection method 318 Address space 103 ADIC 162 to 164 ADM1 435 ADM2 437 ADS 437 ADTRG 81 Analog input channel specification register 437 ANI0 to ANI11 86 Arbitration 319 ASCK0 82 ASCK1 83 ASIM0 ASIM1 402 ASIS0 ASIS1 403 ASTB 88 Asynchronous serial interface 399 Asynchronous serial interfa...

Page 659: ...fferential linearity error 449 DIOA0 to DIOA5 453 DLR 569 DMA function 451 DMA byte count registers 0 to 5 459 DMA channel control registers 0 to 5 460 DMA internal RAM address registers 0 to 5 454 DMA peripheral I O address registers 0 to 5 453 DMA transfer request control block 452 DMAIC0 to DMAIC5 162 to 164 DMA start factor expansion register 459 DMAS 459 DR 571 DRA0 to DRA5 454 DSTB 87 DWC 13...

Page 660: ... 278 291 351 IICC0 IICC1 280 339 IICCE0 IICCE1 289 350 IICCL0 IICCL1 288 349 IICF0 IICF1 347 IICIC1 162 to 164 IICS0 IICS1 285 344 IICX0 IICX1 289 350 Illegal opcode 171 Image 104 In service priority register 165 INTC 40 50 Integral linearity error 450 Internal RAM area 110 Internal ROM area 107 Interrupt control register 162 to 164 Interrupt controller 40 50 Interrupt request signal generator 279...

Page 661: ... 42 52 Port 0 474 Port 0 mode register 476 Port 1 479 Port 1 function register 481 Port 1 mode register 480 Port 10 503 Port 10 function register 505 Port 10 mode register 504 Port 11 507 Port 11 mode register 508 Port 2 483 Port 2 function register 485 Port 2 mode register 484 Port 3 488 Port 3 function register 490 Port 3 mode register 489 Port 4 492 Port 4 mode register 493 Port 5 492 Port 5 mo...

Page 662: ... edge specification register 0 154 477 ROM 40 50 ROM correction function 518 RTBH 468 RTBL 468 RTO 466 RTP 41 52 RTP0 to RTP7 89 RTPC 470 RTPM 469 RTPTRG 81 RX0 RX1 400 RXB0 RXB1 400 RXD0 82 RXD1 83 S Sampling time 450 SAR 433 564 SCK0 SCK1 82 SCK2 SCK3 83 SCK4 84 SCL0 82 SCL1 83 SCR 581 SDA0 82 SDA1 83 Serial clock counter 278 Serial clock selection registers 0 to 3 270 Serial I O shift registers...

Page 663: ...9 UBEN 87 USR 572 V V850 SB1 33 43 V850 SB2 53 63 Variable length serial control register 4 422 Variable length serial I O shift register 4 420 Variable length serial setting register 4 423 VDD 91 VPP 91 VSS 91 W WAIT 90 Wait function 132 Wakeup controller 278 Wakeup function 320 Watch timer clock selection register 257 Watch timer function 253 Watch timer high speed clock selection register 256 W...

Page 664: ...ion CHAPTER 7 TIMER COUNTER FUNCTION Modification of Figure 11 2 A D Converter Mode Register 1 ADM1 Addition of description in 11 5 Low Power Consumption Mode CHAPTER 11 A D CONVERTER Addition of Caution in CHAPTER 18 FLASH MEMORY CHAPTER 18 FLASH MEMORY Addition of Table 19 5 Acknowledge Signal Output Condition of Control Field Addition of description 19 1 8 Bit format Modification of Caution in ...

Page 665: ...3034BY Modification of Note and addition of registers in 3 4 8 Peripheral I O registers Addition of description in 3 4 9 Specific registers Modification of Description example in 3 4 9 Specific registers Modification of Caution 2 in 3 4 9 Specific registers Addition of Remarks in 3 4 9 2 b Reset conditions PRERR 1 CHAPTER 3 CPU FUNCTIONS Addition of Note and Caution in 4 2 2 1 System control regis...

Page 666: ...in Figure 7 18 a 16 bit timer mode control registers 0 1 TMC0 TMC1 Modification of description in Caution in 7 2 6 2 One shot pulse output with external trigger Modification of description in 7 2 7 6 a One shot pulse output by software Modification of description in 7 2 7 6 b One shot pulse output with external trigger Addition of 7 3 1 Outline Change of Figure 7 32 Timing of Interval Timer Operat...

Page 667: ...ers 0 to 5 DCHC0 to DCHC5 Addition of 12 5 Operation Addition of 12 6 Cautions CHAPTER 12 DMA FUNCTIONS Addition of 13 2 Features Addition of 13 3 2 Output latch Addition of description in 13 5 Usage Addition of 13 7 3 CHAPTER 13 REAL TIME OUTPUT FUNCTION RTO Addition of description in Table 14 1 Pin I O Buffer Power Supplies Addition of Caution in 14 2 8 1 Function of P9 pins Addition of Caution ...

Page 668: ... of 19 3 2 14 IEBus high speed clock selection register IEHCLK CHAPTER 19 IEBus CONTROLLER V850 SB2 Addition of CHAPTER 20 ELECTRICAL SPECIFICATIONS CHAPTER 20 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 21 PACKAGE DRAWINGS CHAPTER 21 PACKAGE DRAWINGS Addition of CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS CHAPTER 22 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX A NOTES ON TARGET SYSTEM ...

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