NEC Renesas mPD71312 User Manual Download

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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas

Electronics Corporation

took over all the business of both

companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by:

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Send any inquiries to http://www.renesas.com/inquiry.

Summary of Contents for Renesas mPD71312

Page 1: ...ook over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1st 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ...

Page 2: ...ct for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and meas...

Page 3: ...Document No U18438EJ2V0UD00 2nd edition Date Published May 2008 NS Printed in Japan 2008 µPD71312 µPD71312 LCD Controller Driver Dedicated to 78K0 Kx2 and 78K0R Kx3 User s Manual ...

Page 4: ...User s Manual U18438EJ2V0UD 2 MEMO ...

Page 5: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 6: ...eof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specifi...

Page 7: ...User s Manual U18438EJ2V0UD 5 MEMO ...

Page 8: ...ns How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To gain a general understanding of functions Read this manual in the order of the CONTENTS To know details of the 78K 0 microcontrollers instructions Refer to the separate document 78K 0 Series Instructions User s Manual U12326E Conventions D...

Page 9: ...LLER DRIVER 16 3 1 Functions of LCD Controller Driver 16 3 2 Configuration of LCD Controller Driver 18 3 3 Controlling LCD Controller Driver 20 3 4 Registers Controlling LCD Controller Driver 22 3 5 Setting LCD Controller Driver 26 3 6 LCD Display Data Memory 28 3 7 Common and Segment Signals 29 3 8 Display Modes 33 3 8 1 Static display example 33 3 8 2 Two time slice display example 36 3 8 3 Thre...

Page 10: ...tion of Operation 51 4 2 1 I 2 C bus function 51 4 2 2 Status transition diagram 53 4 3 Write Operation 54 4 4 Read Operation 57 CHAPTER 5 ELECTRICAL SPECIFICATIONS 61 CHAPTER 6 PACKAGE DRAWINGS 66 CHAPTER 7 RECOMMENDED SOLDERING CONDITIONS 68 ...

Page 11: ...ote Power supply voltage LVDD 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 C Note Only communication with IIC0 of the 78K0 Kx2 and 78K0R Kx3 is possible It does not support the simplified IIC of the 78K0R Kx3 1 2 Applications APS cameras digital cameras AV equipments and household electrical appliances etc 1 3 Ordering Information Flash memory version Lead free products Part Number Packa...

Page 12: ...OM2 COM3 S0 S1 S2 S3 S4 S5 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 CAPL CAPH IC SCL SDA LCLK RESET LV DD LV SS S35 S34 S33 S32 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 ...

Page 13: ...1 S21Note VLC0 Note VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 S6Note 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note Leave open or connect to an identical pin that is adjacent to this pin Pin Identification CAPH CAPL LCD power supply capacitance control COM0 to COM3 Common output IC Internally connected LCLK Clock input LVDD Power ...

Page 14: ...S36 to S39 Note Output LCD controller driver segment signal outputs Output COM0 to COM3 Output LCD controller driver common signal outputs Output LVDD Positive power supply for LCD controller driver LVSS Ground potential for LCD controller driver VLC0 to VLC2 LCD drive voltage CAPH CAPL LCD drive voltage booster capacitor connection RESET Input System reset input LCLK Input System clock input Inpu...

Page 15: ... common signal output pins for the LCD controller driver 2 2 5 LVDD This is the positive power supply pin for the LCD controller driver 2 2 6 LVSS This is the ground potential pin for the LCD controller driver 2 2 7 VLC0 to VLC2 These pins are the power supply voltage pins for driving the LCD 2 2 8 CAPH CAPL These pins are the capacitor connection pins for driving the LCD 2 2 9 RESET This is the a...

Page 16: ... for the configuration of the I O circuit of each type Table 2 2 Pin I O Circuit Types Pin Name I O Circuit Type I O Recommended Connection of Unused Pins LCLK 2 U Independently connect to LVDD or LVSS via a resistor SCL 2 G Input SDA 13 R I O Be sure to pull up externally S0 to S35 S36 to S39 Note 17 COM0 to COM3 18 Output VLC0 to VLC2 CAPH CAPL Leave open RESET 2 Input IC Connect directly to LVS...

Page 17: ...triggered input with hysteresis characteristics IN Type 2 U Type 13 R IN Note Schmitt triggered input with hysteresis characteristics data output disable IN OUT N ch VSS Type 17 Type 18 P ch N ch P ch N ch N ch N ch data OUT VLC0 VLC1 SEG VLC2 P ch P ch P ch N ch P ch N ch P ch N ch P ch N ch data P ch N ch VLC1 VLC0 VLC2 OUT COM Note It is pulled down only during reset ...

Page 18: ...ting external resistance division and internal resistance division 2 Automatic output of segment and common signals based on automatic display data memory read 3 Five different display modes Static 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 4 Four different frame frequencies selectable in each display mode 5 Segment signal outputs 36 S0 to S35 52 pin product 40 S0 to S...

Page 19: ...to COM2 108 36 segment signals 3 common signals Internal voltage boosting External resistance division Internal resistance division 1 3 4 COM0 to COM3 36 144 36 segment signals 4 common signals b 64 pin product LCD Driver Reference Voltage Generator Bias Mode Number of Time Slices Common Signals Used Number of Segments Maximum Number of Pixels Static COM0 COM1 to COM3 40 40 segment signals 1 commo...

Page 20: ...ntroller Driver Item Configuration Display outputs Segment signals 36 52 pin product 40 64 pin product Common signals 4 COM0 to COM3 Display block LCDSEG 36 byte RAM 52 pin product 40 byte RAM 64 pin product LCD controller driver Control block LCDCTL LCD mode setting register LCDMD LCD display mode register LCDM LCD clock control register LCDC LCD voltage boost control register 0 VLCG0 Figure 3 1 ...

Page 21: ...gister 0 VLCG0 CAPH CAPL Timing controller VLCON LCDM0 CTSEL1 CTSEL0 LCDON SCOC SEGSET0 MDSET1 LCD mode setting register LCDMD MDSET0 SEGSET2 SEGSET1 LCD drive voltage controller 2 3 Selector Clock generator for boosting Booster circuit Common voltage controller Segment voltage controller Display data memory Display data memory Figure 3 2 Block Diagram of LCD Controller Driver Note 64 pin product ...

Page 22: ...s Table 3 3 Slave ID and Address of LCDCTL and LCDSEG Block Control registers Display RAM Slave ID 7 bits Address 8 bits LCD mode setting register LCDMD 00000000 LCD display mode register LCDM 00000001 LCD clock control register LCDC 00000010 LCDCTL Control block 0 1 1 1 0 0 0 LCD voltage boost control register 0 VLCG0 00000011 S0 to S35 00000000 to 00100011 LCDSEG Display block 0 1 1 1 0 0 1 S36 ...

Page 23: ...27H Note 0 0 0 0 S39 Note 26H Note 0 0 0 0 S38 Note 25H Note 0 0 0 0 S37 Note 24H Note 0 0 0 0 S36 Note 23H 0 0 0 0 S35 22H 0 0 0 0 S34 21H 0 0 0 0 S33 20H 0 0 0 0 S32 1FH 0 0 0 0 S31 1EH 0 0 0 0 S30 1DH 0 0 0 0 S29 1CH 0 0 0 0 S28 1BH 0 0 0 0 S27 1AH 0 0 0 0 S26 19H 0 0 0 0 S25 18H 0 0 0 0 S24 17H 0 0 0 0 S23 16H 0 0 0 0 S22 15H 0 0 0 0 S21 14H 0 0 0 0 S20 13H 0 0 0 0 S19 12H 0 0 0 0 S18 11H 0 0 ...

Page 24: ...et using an 8 bit memory manipulation instruction Reset signal generation sets LCDMD to 00H Figure 3 5 Format of LCD Mode Setting Register Address LCDCTL s 00H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 LCDMD SEGSET2 SEGSET1 SEGSET0 0 0 0 MDSET1 MDSET0 SEGSET2 SEGSET1 SEGSET0 Segment number setting 0 1 1 36 52 pin product 0 0 40 64 pin product Other than above Setting prohibited MDSET1 MDSET0 LCD ...

Page 25: ...Display off all segment outputs are deselected 1 Display on SCOC Segment pin common pin output control Note 0 Output ground level to segment common pin 1 Output deselect level to segment pin and LCD waveform to common pin VLCON Booster circuit operation enable disable Note 0 No internal voltage boosting 1 Internal voltage boosting enabled LCD controller driver display mode selection Resistance div...

Page 26: ...s and common buffers to non display output status by setting SCOC 1 3 Set display on by setting LCDON 1 3 LCD clock control register LCDC LCDC specifies the LCD source clock and LCD clock The frame frequency is determined according to the LCD clock and the number of time slices LCDC is set using an 8 bit memory manipulation instruction Reset signal generation sets LCDC to 00H Figure 3 7 Format of ...

Page 27: ...of the LCD panel used is 4 5 V 1 1 0 V specification of the LCD panel used is 3 V Contrast adjustment TYP VLC0 VLC1 VLC2 CTSEL1 CTSEL0 GAIN 0 GAIN 1 GAIN 0 GAIN 1 GAIN 0 GAIN 1 1 0 4 89 V Note2 3 39 V 3 27 V Note2 2 27 V 1 63 V Note2 1 13 V 1 1 4 71 V 3 21 V 3 13 V 2 13 V 1 57 V 1 07 V 0 0 4 50 V 3 00 V 3 00 V 2 00 V 1 50 V 1 00 V 0 1 4 29 V 2 79 V 2 87 V 1 87 V 1 43 V 0 93 V Notes 1 Select the se...

Page 28: ... the LCD clock using LCD clock control register LCDC 7 Set the voltage boost level and contrasts using LCD voltage boost control register 0 VLCG0 GAIN 0 VLC0 4 5 V VLC1 3 V VLC2 1 5 V GAIN 1 VLC0 3 V VLC1 2 V VLC2 1 V 8 Set VLCON bit 5 of LCDM to 1 to enable voltage boosting 9 Wait for voltage boost wait time tVAWAIT from setting of VLCON see CHAPTER 5 ELECTRICAL SPECIFICATIONS 10 Set SCOC bit 6 o...

Page 29: ...1 and 2 of LCD display mode register LCDM 6 Set the LCD clock using LCD clock control register LCDC 7 Set SCOC bit 6 of LCDM to 1 to output the deselect voltage 8 Set LCDON bit 7 of LCDM to 1 and set data to the data memory in accordance with the display contents after the output corresponding to each data memory is started Subsequent to this procedure set the data to be displayed in the data memo...

Page 30: ...ta memory and the segment common outputs Figure 3 9 Relationship Between LCD Display Data Memory Contents and Segment Common Outputs a 52 pin product S35 S34 S33 S32 S2 S1 S0 COM3 COM2 COM1 COM0 b7 b6 b5 b4 b3 b2 b1 b0 LCDSEG s 23H LCDSEG s 22H LCDSEG s 21H LCDSEG s 20H LCDSEG s 02H LCDSEG s 01H LCDSEG s 00H Address b 64 pin product S39 S38 S37 S36 S2 S1 S0 COM3 COM2 COM1 COM0 b7 b6 b5 b4 b3 b2 b1...

Page 31: ...lay data memory 00H to 23H of LCDSEG Bits 0 1 2 and 3 of each byte are read in synchronization with COM0 COM1 COM2 and COM3 respectively If a bit is 1 it is converted to the select voltage and if it is 0 it is converted to the deselect voltage The conversion results are output to the segment pins S0 to S35 b 64 pin product The segment signals correspond to 40 bytes of LCD display data memory 00H t...

Page 32: ...Static display mode Segment Signal Select Signal Level Deselect Signal Level Common Signal LVSS VLC0 VLC0 LVSS VLC0 LVSS VLCD VLCD 0 V 0 V b 1 2 bias method Segment Signal Select Signal Level Deselect Signal Level Common Signal LVSS VLC0 VLC0 LVSS Select signal level VLC0 LVSS VLCD VLCD 0 V 0 V Deselect signal level VLC1 VLC2 VLCD VLCD VLCD VLCD c 1 3 bias method Segment Signal Select Signal Level...

Page 33: ... display mode COMn Static display TF T VLC0 LVSS VLCD T One LCD clock period TF Frame frequency b 1 2 bias method COMn Two time slot mode TF 2 T VLC0 LVSS VLCD VLC2 COMn Three time slot mode TF 3 T VLC0 LVSS VLCD VLC2 T One LCD clock period TF Frame frequency c 1 3 bias method COMn Three time slot mode TF 3 T VLC0 LVSS VLCD VLC1 VLC2 TF 4 T COMn Four time slot mode VLC0 VLCD VLC1 VLC2 LVSS T One L...

Page 34: ...lect Common signal Segment signal VLC0 LVSS VLCD VLC0 LVSS VLCD T T T One LCD clock period b 1 2 bias method Select Deselect Common signal Segment signal VLC0 LVSS VLCD VLC0 LVSS VLCD T T VLC2 VLC2 T One LCD clock period c 1 3 bias method Select Deselect Common signal Segment signal VLC0 LVSS VLCD VLC0 LVSS VLCD T T VLC2 VLC2 VLC1 VLC1 T One LCD clock period ...

Page 35: ...OM0 see Figure 3 12 for the relationship between the segment signals and LCD segments Table 3 6 Select and Deselect Voltages COM0 Segment S8 S9 S10 S11 S12 S13 S14 S15 Common COM0 Select Deselect Select Select Deselect Select Select Select According to Table 3 6 it is determined that the bit 0 pattern of the display data memory locations 08H to 0FH of LCDSEG must be 10110111 Figure 3 14 shows the ...

Page 36: ... 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 Bit 0 Bit 2 Bit 1 Bit 3 Timing Strobe Data memory address LCD panel LCDSEG s 00H 1 2 3 4 5 6 7 8 9 A B C D E F LCDSEG s 10H 1 2 3 4 5 6 7 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 COM 3 COM 2 COM 1 COM 0 Can be connected together ...

Page 37: ...HAPTER 3 LCD CONTROLLER DRIVER User s Manual U18438EJ2V0UD 35 Figure 3 14 Static LCD Drive Waveform Examples LVSS COM0 LVSS S11 LVSS S12 VLCD 0 COM0 to S12 VLCD 0 COM0 to S11 TF VLC0 VLC0 VLC0 VLCD VLCD ...

Page 38: ...rding to Table 3 7 at the timing of the common signals COM0 and COM1 see Figure 3 15 for the relationship between the segment signals and LCD segments Table 3 7 Select and Deselect Voltages COM0 and COM1 Segment S12 S13 S14 S15 Common COM0 Select Select Deselect Deselect COM1 Deselect Select Select Select According to Table 3 7 it is determined that the display data memory location 0FH of LCDSEG t...

Page 39: ...1 0 0 0 1 0 1 1 1 1 1 1 1 0 Bit 3 Bit 2 Bit 1 Bit 0 Timing strobe Data memory address LCD panel LCDSEG s 00H 1 2 3 4 5 6 7 8 9 A B C D E F LCDSEG s 10H 1 2 3 4 5 6 7 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 COM 3 COM 2 COM 1 COM 0 Open Open Can always be used to store any data because the two time slice mode is being used ...

Page 40: ...anual U18438EJ2V0UD 38 Figure 3 17 Two Time Slice LCD Drive Waveform Examples 1 2 Bias Method LVSS COM0 LVSS LVSS S15 VLCD 0 COM1 to S15 VLCD 0 COM0 to S15 COM1 1 2VLCD 1 2VLCD TF VLC0 VLC0 VLC0 VLCD VLCD VLC1 2 VLC1 2 VLC1 2 1 2VLCD 1 2VLCD ...

Page 41: ...timing of the common signals COM0 to COM2 see Figure 3 18 for the relationship between the segment signals and LCD segments Table 3 8 Select and Deselect Voltages COM0 to COM2 Segment S6 S7 S8 Common COM0 Deselect Select Select COM1 Select Select Select COM2 Select Select According to Table 3 8 it is determined that the display data memory location 06H of LCDSEG that corresponds to S6 must contain...

Page 42: ...Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD panel LCDSEG s 00H 1 2 3 4 5 6 7 8 9 A B C D E F LCDSEG s 10H 1 2 3 4 5 6 7 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 COM 3 COM 2 COM 1 COM 0 Open x x x x x x x x Can be used to store any data because there is no corresponding segment in the LCD panel Can always be used to st...

Page 43: ...3 20 Three Time Slice LCD Drive Waveform Examples 1 2 Bias Method LVSS COM0 LVSS LVSS COM2 VLCD 0 COM1 to S6 VLCD 0 COM0 to S6 COM1 1 2VLCD 1 2VLCD LVSS S6 VLCD 0 COM2 to S6 1 2VLCD TF VLC0 VLC0 VLC0 VLCD VLCD VLC1 2 VLC1 2 VLC1 2 1 2VLCD 1 2VLCD VLC0 VLC1 2 VLCD 1 2VLCD ...

Page 44: ...hree Time Slice LCD Drive Waveform Examples 1 3 Bias Method COM0 VLCD 0 COM0 to S6 1 3VLCD LVSS COM1 LVSS COM2 LVSS S6 LVSS VLCD 0 COM1 to S6 1 3VLCD VLCD 0 COM2 to S6 1 3VLCD VLC0 VLC2 VLCD VLC1 1 3VLCD VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 TF VLCD 1 3VLCD VLCD 1 3VLCD ...

Page 45: ...s according to Table 3 9 at the timing of the common signals COM0 to COM3 see Figure 3 22 for the relationship between the segment signals and LCD segments Table 3 9 Select and Deselect Voltages COM0 to COM3 Segment S12 S13 Common COM0 Select Select COM1 Deselect Select COM2 Select Select COM3 Select Select According to Table 3 9 it is determined that the display data memory location 0CH of LCDSEG...

Page 46: ... 0 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 Bit 3 Bit 2 Bit 1 Bit 0 Timing strobe Data memory address LCD panel LCDSEG s 00H 1 2 3 4 5 6 7 8 9 A B C D E F LCDSEG s 10H 1 2 3 4 5 6 7 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 COM 3 COM 2 COM 1 COM 0 ...

Page 47: ...aveform Examples 1 3 Bias Method COM0 VLCD 0 COM0 to S12 1 3VLCD LVSS COM1 LVSS COM2 LVSS COM3 LVSS VLCD 0 COM1 to S12 1 3VLCD S12 LVSS VLC0 VLC2 VLCD VLC1 1 3VLCD VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLC0 VLC2 VLC1 VLCD 1 3VLCD VLC0 VLC2 VLC1 TF Remark The waveforms for COM2 to S12 and COM3 to S12 are omitted ...

Page 48: ... are incorporated Using internal voltage divider resistors a LCD drive power supply that meet each bias method listed in Table 3 10 can be generated without using external voltage divider resistors Table 3 10 LCD Drive Voltages with On Chip Voltage Divider Resistors Bias Method No Bias Static 1 2 Bias Method 1 3 Bias Method LCD Drive Voltage Pin VLC0 VLCD VLCD VLCD VLC1 VLCD VLCD Note VLCD VLC2 VL...

Page 49: ...l Resistance Division Method a 1 3 bias method and static display mode R R R LVSS VLC0 VLCD VLC1 VLC2 b 1 2 bias method R R R LVSS VLC0 VLCD VLC1 VLC2 Remark It is recommended to use the external resistance division method when using the static display mode in order to reduce power consumed by the voltage divider resistor ...

Page 50: ...xamples of LCD drive voltage connection corresponding to each bias method Figure 3 26 Examples of LCD Drive Power Connections External Resistance Division Method a Static display mode VLCD VLC0 VLC1 VLC2 b Static display mode VLC1 VLC2 LVSS GND LVSS VLC0 VLCD VLC1 VLC2 LVSS VLC0 VLCD VLC1 VLC2 c 1 2 bias method d 1 3 bias method R LVSS R VLC0 VLCD VLC1 VLC2 R LVSS R R VLC0 VLCD VLC1 VLC2 Remark Bo...

Page 51: ...µF recommended is required when the internal voltage boosting method is selected Table 3 11 Output Voltages of VLC0 to VLC2 Pins VLCG0 GAIN 0 GAIN 1 LCD drive power supply pin VLC0 4 5 V 3 0 V VLC1 3 0 V 2 0 V VLC2 LCD reference voltage 1 5 V 1 0 V Cautions 1 When using the LCD function do not leave the VLC0 VLC1 and VLC2 pins open Refer to Figure 3 27 for connection 2 Since the LCD drive voltage ...

Page 52: ...n pins SCL SDA Communication function Slave transmission reception 4 1 System Configuration The system configuration of the LCD controller driver is illustrated in Figure 4 1 Figure 4 1 System Configuration µPD71312 Serial clock Serial data bus VDD VDD SDA SCL 78K0 Kx2 78K0R Kx3 SDA0 SCL0 Caution Only communication with IIC0 of the 78K0 Kx2 and 78K0R Kx3 is possible It does not support the simplif...

Page 53: ...that follow the start condition This slave ID is used to select a specific slave out of several slaves connected to a bus line Normally one slave ID is assigned to one slave Since the µPD71312 has two internal slave IDs however LCDCTL control register and LCDSEG display memory can be selected as access targets A slave detects via hardware that data on the SDA line is a slave ID and checks whether ...

Page 54: ...t the transmission and reception sides The reception side returns ACK each time it has received 8 bit data To generate ACK the reception side makes the SDA line low at high level of the ninth clock on the SCL line The transmission side detects whether ACK has been received from the reception side after transmitting 8 bit data When ACK is returned it is assumed that reception has been correctly per...

Page 55: ...ransfer has been completed Figure 4 6 Stop Condition SCL SDA H 4 2 2 Status transition diagram Figure 4 7 shows the status transition diagram Figure 4 7 Shift Register Operation RESET Status 4 Wait for WD RST Status 6 Wait for ID R Status 7 Wait for RD Status 3 Wait for AD Status 2 Wait for ID W Status 5 Wait for WD SP Status 8 Wait for ACK NACK Status 1 Wait for ST SP Status 9 Wait for SP SP dete...

Page 56: ...sing procedure Figure 4 8 Processing Procedure of Write Operation Remark ST Start condition RST Restart condition SP Stop condition Slave ID reception Yes ST detected ID matched ACK M ACK transmission Address reception WD reception SP detection End LCD controller driver side slave Yes No No Yes No Slave ID transmission Address transmission WD transmission End CPU side master ST generation ACK rece...

Page 57: ... D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK SP Note The address is incremented by one based on the register read write start address by continuously performing read write access from transmissions of the start condition to stop condition With this function the address does not need to be set each time Cautions 1 Generate a stop condition if an access like the one shown below is made An access mad...

Page 58: ...acknowledge signal is received at the rising edge of the 9th clock 9 Write data is transmitted second time from the 1st to 8th clocks following 8 The address is automatically incremented by 1 10 An acknowledge signal is received at the rising edge of the 9th clock 11 The stop condition is transmitted Figure 4 10 shows the timing chart of the write operation Figure 4 10 Timing Chart of Write Operat...

Page 59: ...on Address reception RST detected Slave ID reception ID matched RD transmission ACK reception SP detection End Yes LCD controller driver side slave No No Yes Yes No No Yes No Slave ID transmission Address transmission Slave ID transmission RD reception ACK transmission End Yes CPU side master Yes No ST generation ACK reception Yes RST generation ACK transmission ACK reception Yes SP generation No ...

Page 60: ...3 Read data2 14 ACK 15 SP D7 D6 D5 D4 D3 D2 D1 D0 NACK SP D7 D6 D5 D4 D3 D2 D1 D0 NACK SP Note The address is incremented by one based on the register read write start address by continuously performing read write access from transmissions of the start condition to stop condition With this function the address does not need to be set each time Cautions 1 Generate a stop condition if an access like...

Page 61: ...ing edge of the 9th clock 7 The restart condition is transmitted 8 The slave ID is transmitted second time from the 1st to 7th clocks following 7 9 R W information 1 is transmitted at the 8th clock 10 An acknowledge signal is received at the rising edge of the 9th clock 11 Read data is received first time from the 1st to 8th clocks following 10 12 An acknowledge signal is transmitted from the fall...

Page 62: ...s the timing chart of the read operation Figure 4 13 Timing Chart of Read Operation Continued from above 1 8 9 1 ID6 R ACK RD7 1 8 9 1 ID6 R RD7 ACK xxH xxH xxH xxH xxH xxH xxH Setup 8 9 RD0 8 9 RD0 ACK ACK xxH xxH xxH FFH Write FFH or WREL0 1 xxH 1 8 9 1 8 9 RD7 RD0 RD7 RD0 xxH xxH xxH xxH xxH xxH xxH xxH FFH Write FFH or WREL0 1 Restart condition Stop condition 1 8 9 1 8 9 8 1 Stop condition 9 S...

Page 63: ...mA Operating ambient temperature TA 40 to 85 C Storage temperature Tstg 40 to 125 C Notes 1 Must be 6 5 V or lower 2 64 pin product only Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must...

Page 64: ...ET LCLK 3 µA Output leakage current high ILOH VO LVDD 3 µA Output leakage current low ILOL VO 0 V 3 µA LCLK pull down resistor RLCLK After reset 10 30 100 kΩ LVDD 5 0 V 10 25 50 µA IDD1 When LCD including booster circuit is stopped and IIC is operating LVDD 3 0 V 10 13 30 µA LVDD 5 0 V 10 2 36 µA IDD2 When only LCD booster circuit is operating and IIC is in standby status LVDD 3 0 V 10 1 5 16 µA L...

Page 65: ...ime tHD STA 4 1 0 7 µs Hold time when SCL L tLOW 5 0 1 25 µs Hold time when SCL H tHIGH 5 0 1 25 µs Data setup time reception tSU DAT 0 0 µs Data hold time transmission Note 2 tHD DAT 0 47 4 0 0 23 1 00 µs Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of tHD DAT is during normal transfer and a wait state is inserte...

Page 66: ...utput resistor Note 2 Segment RODS 200 kΩ Pull up resistor Note 3 between LVDD and VLC0 RLU LVDD 5 0 V VLC0 3 0 V 7 3 kΩ c 1 2 bias method 2 7 V LVDD 5 5 V Parameter Symbol Conditions MIN TYP MAX Unit LCD drive voltage VLCD 2 7 LVDD V LCD divider resistor Note 1 RLCD 60 100 150 kΩ TA 10 to 85 C 40 kΩ LCD output resistor Note 2 Common RODC TA 40 to 10 C 60 kΩ LCD output resistor Note 2 Segment RODS...

Page 67: ...F Note 2 3 VLCD2 V 4 5 V LVDD 5 5 V 4 s GAIN 1 1 8 V LVDD 4 5 V 0 5 s Voltage boost wait time Note 4 tVAWAIT GAIN 0 0 5 s LCD output resistor Note 5 Common RODC 40 kΩ LCD output resistor Note 5 Segment RODS 200 kΩ Notes 1 This is a capacitor that is connected between voltage pins used to drive the LCD C1 A capacitor connected between CAPH and CAPL C2 A capacitor connected between VLC0 and GND C3 A...

Page 68: ...A1 A2 A3 10 00 0 20 10 00 0 20 12 00 0 20 12 00 0 20 1 60 MAX 0 10 0 05 1 40 0 05 0 25 c θ e x y ZD ZE 0 65 0 13 0 10 1 10 1 10 L Lp L1 0 50 0 60 0 15 1 00 0 20 P52GB 65 UET 1 3 5 3 NOTE Each lead centerline is located within 0 13 mm of its true position at maximum material condition detail of lead end 52 PIN PLASTIC LQFP 10x10 0 32 0 08 0 07 b 13 26 1 52 14 27 40 39 ...

Page 69: ...A2 A3 10 00 0 20 10 00 0 20 12 00 0 20 12 00 0 20 1 60 MAX 0 10 0 05 1 40 0 05 0 25 c θ e x y ZD ZE 0 50 0 08 0 08 1 25 1 25 L Lp L1 0 50 0 60 0 15 1 00 0 20 P64GB 50 UEU 1 3 5 3 NOTE Each lead centerline is located within 0 08 mm of its true position at maximum material condition detail of lead end 0 22 0 05 b 16 32 1 64 17 33 49 48 64 PIN PLASTIC LQFP FINE PITCH 10x10 ...

Page 70: ...evice Mount Manual http www necel com pkg en mount index html Table 7 1 Surface Mounting Type Soldering Conditions Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max at 220 C or higher Count Three times or less Exposure limit 7 days Note after that prebake at 125 C for 20 to 72 hours IR60 207 3 Partial heating Pin t...

Page 71: ...l 02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 12 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com For further information please contact G0706 Europe NEC Electronics Europe GmbH Arcadiastrasse 10 4...

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