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NEC 78K0S/KB1+, User Manual

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CHAPTER  11   SERIAL  INTERFACE  UART6 

User’s Manual  U17446EJ3V1UD 

192 

(6)  Asynchronous serial interface control register 6 (ASICL6) 

This register controls the serial communication operations of serial interface UART6.  

ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. 

Generation of reset signal sets this register to 16H. 

 

Caution  ASICL6 can be refreshed (the same value is written) by software during a communication 

operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 are 1 or when bit 7 (POWER6) and 

bit 5 (RXE6) of ASIM6 are 1), if 0 data has been written to ASICL6 by SBRT6 and SBTT6. 

 

Figure 11-10.  Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2) 

 

Address:  FF98H  After reset:  16H  R/W

Note

 

Symbol 

<7> 

<6> 

5 4 3 2 1 0 

ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60  DIR6 TXDLV6 

 

 

 

 

 

 

 

 

 

 

SBRF6 

SBF reception status flag 

 

0 

If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly 

 

1 

SBF reception in progress 

 

 

 

 

SBRT6 

SBF reception trigger 

 0 

−

 

 

1 

SBF reception trigger 

 

 

 

 

SBTT6 

SBF transmission trigger 

 0 

−

 

 

1 

SBF transmission trigger 

 

Note

  Bit 7 is read-only. 

 

<R>

Summary of Contents for 78K0S/KB1+

Page 1: ...PD78F9232 μPD78F9234 μPD78F9232 A μPD78F9234 A μPD78F9232 A2 μPD78F9234 A2 78K0S KB1 8 bit Single Chip Microcontrollers 2005 Printed in Japan Document No U17446EJ3V1UD00 3rd edition Date Published January 2007 N CP K ...

Page 2: ...User s Manual U17446EJ3V1UD 2 MEMO ...

Page 3: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 4: ... responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury includin...

Page 5: ...set Instruction description How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To understand the overall functions of 78K0S KB1 Read this manual in the order of the CONTENTS The mark R shows major revised points The revised points can be easily searched by copying an R in the PDF file and specify...

Page 6: ...l This manual 78K 0S Series Instructions User s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No Operation U16656E Language U14877E RA78K0S Assembler Package Structured Assembly Language U11623E Operation U16654E CC78K0S C Compiler Language U14872E ID78K0S NS Ver 2 52 Integrated Debugger Operation U16584E ID78K0S QB Ver 2 81 Integrated Debugge...

Page 7: ...ages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed abov...

Page 8: ... 2 12 VSS 24 2 3 Pin I O Circuits and Connection of Unused Pins 25 CHAPTER 3 CPU ARCHITECTURE 27 3 1 Memory Space 27 3 1 1 Internal program memory space 29 3 1 2 Internal data memory space 29 3 1 3 Special function register SFR area 30 3 1 4 Data memory addressing 30 3 2 Processor Registers 32 3 2 1 Control registers 32 3 2 2 General purpose registers 35 3 2 3 Special function registers SFRs 36 3 ...

Page 9: ...erators 72 5 4 System Clock Oscillators 75 5 4 1 High speed internal oscillator 75 5 4 2 Crystal ceramic oscillator 75 5 4 3 External clock input circuit 77 5 4 4 Prescaler 77 5 5 Operation of CPU Clock Generator 78 5 6 Operation of Clock Generator Supplying Clock to Peripheral Hardware 83 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 85 6 1 Functions of 16 bit Timer Event Counter 00 85 6 2 Configuratio...

Page 10: ...pped by software is selected by option byte 155 9 4 3 Watchdog timer operation in STOP mode when low speed internal oscillator can be stopped by software is selected by option byte 157 9 4 4 Watchdog timer operation in HALT mode when low speed internal oscillator can be stopped by software is selected by option byte 159 CHAPTER 10 A D CONVERTER 160 10 1 Functions of A D Converter 160 10 2 Configur...

Page 11: ... Standby Function Operation 238 14 2 1 HALT mode 238 14 2 2 STOP mode 241 CHAPTER 15 RESET FUNCTION 245 15 1 Register for Confirming Reset Source 252 CHAPTER 16 POWER ON CLEAR CIRCUIT 253 16 1 Functions of Power on Clear Circuit 253 16 2 Configuration of Power on Clear Circuit 254 16 3 Operation of Power on Clear Circuit 254 16 4 Cautions for Power on Clear Circuit 255 CHAPTER 17 LOW VOLTAGE DETEC...

Page 12: ...ample of block blank check operation in self programming mode 300 19 8 8 Example of byte write operation in self programming mode 303 16 8 9 Examples of internal verify operation in self programming mode 306 19 8 10 Examples of operation when command execution time should be minimized in self programming mode 310 19 8 11 Examples of operation when interrupt disabled time should be minimized in sel...

Page 13: ... in circuit emulator IE 78K0S NS or IE 78K0S NS A 373 A 5 4 When using in circuit emulator QB 78K0SKX1MINI 373 A 6 Debugging Tools Software 374 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 375 APPENDIX C REGISTER INDEX 377 C 1 Register Index Register Name 377 C 2 Register Index Symbol 380 APPENDIX D LIST OF CAUTIONS 383 APPENDIX E REVISION HISTORY 402 E 1 Major Revisions in This Edition 402 E 2 Revisi...

Page 14: ...tchdog timer operable on internal low speed internal oscillator clock O I O ports 26 O Timer 4 channels 16 bit timer event counter 1 channel 8 bit timer 2 channels Watchdog timer 1 channel O Serial interface UART LIN Local Interconnect Network bus supported 1 channel O On chip multiplier 8 bits x 8 bits 16 bits O 10 bit resolution A D converter 4 channels O Supply voltage VDD 2 0 to 5 5 V Note O O...

Page 15: ...emory versions Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications Part number list μ PD78F9232MC 5A4 μ PD78F9234MC 5A4 μ PD78F9232MC 5A4 A μ PD78F9234MC 5A4 A μ PD78F9232MC A 5A4 Note μ PD78F9234MC A 5A4 Note μ PD78F9232MC A 5A4 A Note ...

Page 16: ...45 P46 P44 RxD6 P43 TxD6 INTP1 P42 TOH1 P41 INTP3 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 Caution Connect the AVSS pin to VSS ANI0 to ANI3 Analog input P130 Port 13 AVREF Analog reference voltage RESET Reset AVSS Analog ground RxD6 Receive data INTP0 to INTP3 External interrupt input TI000 TI010 Timer input P00 to P03 Port 0 TO00 TOH1 Timer output P20 to P23 Port 2 TxD6 Transmit data P30 to P34 Por...

Page 17: ...Hz TYP Crystal ceramic oscillation 1 to 10 MHz External clock input oscillation 1 to 10 MHz Clock for TMH1 and WDT oscillation frequency Low speed internal oscillation 240 kHz TYP CMOS I O 7 13 15 24 CMOS input 1 1 1 1 Port CMOS output 1 1 16 bit TM0 1 ch 8 bit TMH 1 ch 8 bit TM8 1 ch Timer WDT 1 ch Serial interface LIN Bus supporting UART 1 ch A D converter 10 bits 4 ch 2 7 to 5 5V Multiplier 8 b...

Page 18: ...C LVI control Reset control Port 3 P30 to P33 4 P34 P120 to P123 4 Port 12 System control High speed internal oscillator RESET P34 X1 P121 X2 P122 Low speed internal oscillator INTP0 P30 INTP1 P43 INTP2 P31 INTP3 P41 ANI0 P20 to ANI3 P23 4 A D converter AVREF AVSS 8 bit timer 80 Watchdog timer Multiplier 8 bit timer H1 16 bit timer event counter 00 TO00 TI010 P31 TI000 P30 RxD6 P44 TxD6 P43 Serial...

Page 19: ...otal 26 pins CMOS I O 24 pins CMOS input 1 pin CMOS output 1 pin Timer 16 bit timer event counter 1 channel 8 bit timer timer H1 1 channel 8 bit timer timer 80 1 channel Watchdog timer 1 channel Timer output 2 pins PWM 1 pin A D converter 10 bit resolution 4 channels Serial interface LIN bus supporting UART mode 1 channel External 4 Vectored interrupt sources Internal 9 Reset Reset by RESET pin In...

Page 20: ...ut mode in 1 bit units An on chip pull up resistor can be connected by setting software Input P34 Note Input Port 3 Input only Input RESET Note P40 P41 INTP3 P42 TOH1 P43 TxD6 INTP1 P44 RxD6 P45 P46 P47 I O Port 4 8 bit I O port Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected by setting software Input P120 P121 Note X1 Note P122 Note X2 Note P123 I O ...

Page 21: ...30 INTP0 TI010 Input Capture trigger input to capture register CR000 of 16 bit timer event counter 00 Input P31 TO00 INTP2 TO00 Output 16 bit timer event counter 00 output Input P31 TI010 INTP2 TOH1 Output 8 bit timer H1 output Input P42 ANI0 to ANI3 Input Analog input of A D converter Input P20 to P23 AVREF Reference voltage of A D converter AVSS A D converter ground potential Make the same poten...

Page 22: ...1 also have functions to input output a timer signal and input an external interrupt request signal P34 is a 1 bit input only port This pin is also used as a RESET pin and when the power is turned on this is the reset function For settings of alternate function refer to CHAPTER 18 OPTION BYTE When using P34 as input port pull up the P34 pin by using external resistor P30 to P33 can be set to the f...

Page 23: ...al interface a INTP1 and INTP3 These are external interrupt request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified b TOH1 This is the output pin of 8 bit timer H1 c TxD6 This pin outputs serial data from the asynchronous serial interface d RxD6 This pin inputs serial data to the asynchronous serial interface 2 2 5 P120 to P123 Port 12...

Page 24: ...ply an external clock to X1 Caution The P121 X1 and P122 X2 pins are pulled down during reset 2 2 9 AVREF This pin inputs a reference voltage to the internal A D converter When the A D converter is not used connect this pin to VDD 2 2 10 AVSS This is the A D converter ground potential pin Even when the A D converter is not used always use this pin with the same potential as the VSS pin 2 2 11 VDD ...

Page 25: ... ANI0 to P23 ANI3 11 Input Independently connect to AVREF or VSS via a resistor Output Leave open P30 TI000 INTP0 P31 TI010 TO00 INTP2 P32 and P33 8 A I O Input Independently connect to VDD or VSS via a resistor Output Leave open P34 RESET 2 Input Connect to VDD via a resistor P40 P41 INTP3 P42 TOH1 P43 TxD6 INTP1 P44 RxD6 P45 to P47 P120 8 A Input Independently connect to VDD or VSS via a resisto...

Page 26: ...oltage AVSS P ch N ch Input enable Pull up enable VDD P ch Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch P ch Feedback cut off X1 IN OUT X2 IN OUT OSC enable Data Output disable VDD P ch N ch Data Output Disable P ch N ch Type 2 Type 3 C Type 8 A Type 16 B Type 11 Schmitt triggered input with hysteresis characteristics Comparator VSS VSS VSS VSS VSS ...

Page 27: ...Internal high speed RAM 256 8 bits Flash memory 4 096 8 bits Use prohibited Program memory space Data memory space Program area Option byte area Program area CALLT table area Vector table area F F F F H 0 F F F H 0 0 8 0 H 0 0 7 F H 0 0 8 2 H 0 0 8 1 H 0 0 4 0 H 0 0 3 F H 0 0 2 2 H 0 0 2 1 H 0 0 0 0 H F F 0 0 H F E F F H F E 0 0 H F D F F H 1 0 0 0 H 0 F F F H 0 0 0 0 H Protect byte area Remark Th...

Page 28: ...bits Program memory space Data memory space Program area Option byte area Program area CALLT table area Vector table area Use prohibited F F F F H 1 F F F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 0 8 2 H 0 0 8 1 H 0 0 4 0 H 0 0 3 F H 0 0 2 2 H 0 0 2 1 H F F 0 0 H F E F F H F E 0 0 H F D F F H 2 0 0 0 H 1 F F F H 0 0 0 0 H Protect byte area Remark The option byte and protect byte are 1 byte each ...

Page 29: ... an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H Reset input 0012H INTAD 0006H INTLVI 0016H INTP2 0008H INTP0 0018H INTP3 000AH INP1 001AH INTTM80 000CH INTTMH1 001CH INTSRE6 000EH INTTM000 001EH INTSR6 0010H INTTM010 0020H INTST6 Caution No interrupt sources correspond to ...

Page 30: ...ich contains a data memory and the special function register area SFR can be accessed using a unique addressing mode in accordance with each function Figures 3 3 and 3 4 illustrate the data memory addressing Figure 3 3 Data Memory Addressing μPD78F9232 Special function registers SFR 256 8 bits Internal high speed RAM 256 8 bits Flash memory 4 096 8 bits Use prohibited Direct addressing Register in...

Page 31: ...egisters SFR 256 8 bits Internal high speed RAM 256 8 bits Flash memory 8 192 8 bits Use prohibited Direct addressing Register indirect addressing Based addressing SFR addressing Short direct addressing F F F F H F F 0 0 H F E F F H F F 2 0 H F F 1 F H F E 0 0 H F D F F H F E 2 0 H F E 1 F H 2 0 0 0 H 1 F F F H 0 0 0 0 H ...

Page 32: ...word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETI and POP PSW instructions Reset signal generation sets PSW to 02H Figure 3 6 Program Status Word Configuration 7...

Page 33: ...P0 The SP is decremented before writing saving to the stack memory and is incremented after reading restoring from the stack memory Each stack operation saves restores data as shown in Figures 3 8 and 3 9 Cautions 1 Since generation of reset signal makes the SP contents undefined be sure to initialize the SP before using the stack memory 2 Stack pointers can be set only to the high speed RAM area ...

Page 34: ...ALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _ 2 SP _ 1 SP SP SP _ 3 Upper half register pairs Figure 3 9 Data to Be Restored from Stack Memory RETI instruction PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Lower half register pairs RET instruction POP rp instruction SP PC7 to PC0 Upper half register pairs SP 1 SP SP 2 SP SP 1 SP SP 2 SP SP 1 SP 2 SP SP ...

Page 35: ...t registers in pairs can be used as a 16 bit register AX BC DE and HL Registers can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figure 3 10 General Purpose Register Configuration a Function names X 15 0 7 0 16 bit processing 8 bit processing HL DE BC AX A C B E D L H b Absolute names R0 15 0 7 0 16 bit processing 8 bit processi...

Page 36: ...nipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When specifying an address describe an even address Table 3 3 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the addresses of the im...

Page 37: ...Note 2 0000H FF18H FF19H 10 bit A D conversion result register ADCR Note 2 FF1AH 8 bit A D conversion result register ADCRH R Undefined FF20H Port mode register 0 PM0 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF24H Port mode register 4 PM4 FF2CH Port mode register 12 PM12 FFH FF30H Pull up resistor option register 0 PU0 FF32H Pull up resistor option register 2 PU2 FF33H Pull up...

Page 38: ...s register 6 ASIF6 R FF96H Clock selection register 6 CKSR6 00H FF97H Baud rate generator control register 6 BRGC6 FFH FF98H Asynchronous serial interface control register 6 ASICL6 R W 16H FFA0H Flash protect command register PFCMD W Undefined FFA1H Flash status register PFS 00H FFA2H Flash programming mode control register FLPMC Undefined FFA3H Flash programming command register FLCMD 00H FFA4H F...

Page 39: ...each time another instruction is executed When a branch instruction is executed the branch destination address information is set to the PC to branch by the following addressing for details of each instruction refer to 78K 0S Series Instructions User s Manual U11047E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction cod...

Page 40: ...or BR Low Addr High Addr 3 3 3 Table indirect addressing Function The table contents branch destination address of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC to branch Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can be used to branch to ...

Page 41: ... 4 Register addressing Function The register pair AX contents to be specified with an instruction word are transferred to the program counter PC to branch This function is carried out when the BR AX instruction is executed Illustration 7 0 rp 0 7 A X 15 0 PC 8 7 ...

Page 42: ...ruction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE80H When setting addr16 to FE80H Instruction code 0 0 1 0 1 0 0 1 OP code 1 0 0 0 0 0 0 0 80H 1 1 1 1 1 1 1 0 FEH Illustration 7 0 OP code addr16 low addr16 hig...

Page 43: ...ped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is cleared to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration below Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even address only Description example ...

Page 44: ...ction word This addressing is applied to the 256 byte space FF00H to FFFFH However SFRs mapped at FF00H to FF1FH are accessed with short direct addressing Operand format Identifier Description sfr Special function register name Description example MOV PM0 A When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective address 1 1 1 1 1 1 1 8 7 0 7 OP c...

Page 45: ...at is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instructio...

Page 46: ... accessed is specified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE The contents of addressed memory are transferred Memory address specified by re...

Page 47: ...ition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 Illustration 16 0 H 7 8 L 0 7 7 0 A HL The contents of the memory add...

Page 48: ...hod is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved restored upon interrupt request generation Stack addressing can be used to access the internal high speed RAM area only Description example In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 Illustration E FEE0H SP SP FEE0H FEDFH FEDEH D Memory 0 7 FEDEH ...

Page 49: ...n be used for various control operations Table 4 1 shows the functions of each port In addition to digital I O port functions each of these ports has an alternate function For details refer to CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Functions Port 4 P40 Port 13 P130 P00 Port 0 P03 P20 Port 2 P23 P30 Port 3 P33 P34 P47 P120 P123 Port 12 ...

Page 50: ... Input Port 3 Input only Input RESET Note P40 P41 INTP3 P42 TOH1 P43 TxD6 INTP1 P44 RxD6 P45 P46 P47 I O Port 4 8 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected by setting software Input P120 P121 Note X1 Note P122 Note X2 Note P123 I O Port 12 4 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resistor can be ...

Page 51: ...units Table 4 2 Configuration of Ports Item Configuration Control registers Port mode registers PM0 PM2 PM3 PM4 PM12 Port registers P0 P2 P3 P4 P12 P13 Port mode control register 2 PMC2 Pull up resistor option registers PU0 PU2 PU3 PU4 PU12 Ports Total 26 CMOS I O 24 CMOS input 1 CMOS output 1 Pull up resistor Total 22 ...

Page 52: ... bit units by using pull up resistor option register 0 PU0 This port is also used as the analog input pins of the internal A D converter Generation of reset signal sets port 0 to the input mode Figure 4 2 shows the block diagram of port 0 Figure 4 2 Block Diagram of P00 to P03 P00 to P03 WRPU RD WRPORT WRPM PU00 to PU03 Output latch P00 to P03 PM00 to PM03 VDD P ch PM0 P0 PU0 Selector Internal bus...

Page 53: ...n register 2 PU2 This port is also used as the analog input pins of the internal A D converter Generation of reset signal sets port 2 to the input mode Figure 4 2 shows the block diagram of port 2 Figure 4 3 Block Diagram of P20 to P23 P20 ANI0 to P23 ANI3 WRPU RD PU20 to PU23 WRPM PM20 to PM23 VDD P ch PU2 PMC2 PM2 WRPORT Output latch P20 to P23 PMC20 to PMC23 A D converter Internal bus Selector ...

Page 54: ...st input pin functions Generation of reset signal sets port 3 to the input mode P34 is a 1 bit input only port This pin is also used as a RESET pin and when the power is turned on this is the reset function For settings of alternate function refer to CHAPTER 18 OPTION BYTE When using P34 as input port pull up the P34 pin by using external resistor Figures 4 4 to 4 7 show the block diagrams of port...

Page 55: ...iagram of P31 P31 TI010 TO00 INTP2 WRPU RD WRPORT WRPM PU31 Output latch P31 PM31 Alternate function VDD P ch PU3 PM3 Internal bus Selector Alternate function P3 PU3 Pull up resistor option register 3 P3 Port register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 56: ...P3 Port register 3 PM3 Port mode register 3 RD Read signal WR Write signal Figure 4 7 Block Diagram of P34 RD P34 RESET Option byte Reset Internal bus RD Read signal Caution Because the P34 pin functions alternately as the RESET pin if it is used as an input port pin the function to input an external reset signal to the RESET pin cannot be used The function of the port is selected by the option by...

Page 57: ...pins are used as an input port an on chip pull up resistor can be connected in 1 bit units by using pull up resistor option register 4 PU4 The P41 to P44 pins can also be used for external interrupt request input serial interface data I O and timer output Generation of reset signal sets port 4 to the input mode Figures 4 8 to 4 11 show the block diagrams of port 4 Figure 4 8 Block Diagram of P40 P...

Page 58: ...iagram of P41 and P44 P41 INTP3 P44 RxD6 WRPU RD WRPORT WRPM PU41 PU44 Alternate function Output latch P41 P44 PM41 PM44 VDD P ch PU4 PM4 Internal bus Selector P4 PU4 Pull up resistor option register 4 P4 Port register 4 PM4 Port mode register 4 RD Read signal WR Write signal ...

Page 59: ...ure 4 10 Block Diagram of P42 P42 TOH1 WRPU RD WRPORT WRPM PU42 Output latch P42 PM42 Alternate function VDD P ch PM4 PU4 Internal bus Selector P4 PU4 Pull up resistor option register 4 P4 Port register 4 PM4 Port mode register 4 RD Read signal WR Write signal ...

Page 60: ...tput mode by using port mode register 12 PM12 When the P120 and P123 pins are used as an input port an on chip pull up resistor can be connected by using pull up resistor option register 12 PU12 The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator The functions of the P121 and P122 pins differ therefore depending on the selected system clock oscillator The foll...

Page 61: ...elected by the option byte For details refer to CHAPTER 18 OPTION BYTE Generation of reset signal sets port 12 to the input mode Figures 4 12 and 4 13 show the block diagrams of port 12 Figure 4 12 Block Diagram of P120 and P123 P120 P123 WRPU RD WRPORT WRPM PU120 PU123 Output latch P120 P123 PM120 PM123 VDD P ch PM12 PU12 Internal bus Selector P12 PU12 Pull up resistor option register 12 P12 Port...

Page 62: ...RD Read signal WR Write signal 4 2 6 Port 13 This is a 1 bit output only port Figure 4 14 shows the block diagram of port 13 Figure 4 14 Block Diagram of P130 RD Output latch P130 WRPORT P130 Internal bus P13 P13 Port register 13 RD Read signal WR Write signal Remark When a reset is input P130 outputs a low level If P130 outputs a high level immediately after reset is released the output signal of...

Page 63: ...isters Controlling Port Functions The ports are controlled by the following four types of registers Port mode registers PM0 PM2 PM3 PM4 PM12 Port registers P0 P2 P3 P4 P12 P13 Port mode control register 2 PMC2 Pull up resistor option registers PU0 PU2 PU3 PU4 PU12 ...

Page 64: ...pins is set to the output mode and its output level is changed To use the port pin in the output mode therefore set the corresponding interrupt mask flag to 1 in advance Figure 4 15 Format of Port Mode Register Address FF20H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM0 1 1 1 1 PM03 PM02 PM01 PM00 Address FF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 Address FF2...

Page 65: ... After reset 00H Output latch R W Symbol 7 6 5 4 3 2 1 0 P0 0 0 0 0 P03 P02 P01 P00 Address FF02H After reset 00H Output latch R W Symbol 7 6 5 4 3 2 1 0 P2 0 0 0 0 P23 P22 P21 P20 Address FF03H After reset 00H Note Output latch R W Note Symbol 7 6 5 4 3 2 1 0 P3 0 0 0 P34 P33 P32 P31 P30 Address FF04H After reset 00H Output latch R W Symbol 7 6 5 4 3 2 1 0 P4 P47 P46 P45 P44 P43 P42 P41 P40 Addre...

Page 66: ...3 0 Port mode 1 A D converter mode Caution When PMC20 to PMC23 are set to 1 the P20 ANI0 to P23 ANI3 pins cannot be used as port pins Moreover be sure to set the pull up resistor option registers PU20 to PU23 to 0 for the pins set to A D converter mode Table 4 3 Setting of Port Mode Register Port Register Output Latch and Port Mode Control Register When Alternate Function Is Used Alternate Functio...

Page 67: ... reset signal set these registers to 00H Figure 4 18 Format of Pull up Resistor Option Register Address FF30H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU0 0 0 0 0 PU03 PU02 PU01 PU00 Address FF32H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU2 0 0 0 0 PU23 PU22 PU21 PU20 Address FF33H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU3 0 0 0 0 PU33 P32 PU31 PU30 Address FF34H After reset 00H R W Symb...

Page 68: ... is off however the pin status remains unchanged Once data is written to the output latch it is retained until new data is written to the output latch Reset signal generation clears the data in the output latch 4 4 2 Reading from I O port 1 In output mode The data of the output latch can be read by a transfer instruction The contents of the output latch remain unchanged 2 In input mode The pin sta...

Page 69: ... X1 and X2 pins It can oscillate a clock of 1 to 10 MHz Oscillation of this circuit can be stopped by execution of the STOP instruction External clock input circuit This circuit supplies a clock from an external IC to the X1 pin A clock of 1 to 10 MHz can be supplied Internal clock supply can be stopped by execution of the STOP instruction If the external clock input is selected as the system cloc...

Page 70: ...tion of Clock Generators Item Configuration Control registers Processor clock control register PCC Preprocessor clock control register PPCC Low speed internal oscillation mode register LSRCM Oscillation stabilization time select register OSTS Oscillators Crystal ceramic oscillator High speed internal oscillator External clock input circuit Low speed internal oscillator ...

Page 71: ...lock oscillation stabilization time counter Selector Prescaler Clock to peripheral hardware fXP 8 bit timer H1 watchdog timer Option byte 1 Cannot be stopped 0 Can be stopped Low speed internal oscillation mode register LSRCM Low speed internal oscillator Prescaler System clock oscillatorNote External clock input Crystal ceramic oscillation High speed internal oscillation Watchdog timer fX fX 2 fX...

Page 72: ...8 bit memory manipulation instruction Generation of reset signal sets PCC and PPCC to 02H Figure 5 2 Format of Processor Clock Control Register PCC Address FFFBH After reset 02H R W Symbol 7 6 5 4 3 2 1 0 PCC 0 0 0 0 0 0 PCC1 0 Caution Bits 7 to 2 and 0 must be set to 0 Figure 5 3 Format of Preprocessor Clock Control Register PPCC Address FFF3H After reset 02H R W Symbol 7 6 5 4 3 2 1 0 PPCC 0 0 0...

Page 73: ...ation mode register LSRCM This register is used to select the operation mode of the low speed internal oscillator 240 kHz TYP This register is valid when it is specified by the option byte that the low speed internal oscillator can be stopped by software If it is specified by the option byte that the low speed internal oscillator cannot be stopped by software setting of this register is invalid an...

Page 74: ...TS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 2 10 fX 102 4 μs 0 1 2 12 fX 409 6 μs 1 0 2 15 fX 3 27 ms 1 1 2 17 fX 13 1 ms Cautions 1 To set and then release the STOP mode set the oscillation stabilization time as follows Expected oscillation stabilization time of resonator Oscillation sta...

Page 75: ...een the X1 and X2 pins If the crystal ceramic oscillator is selected by the option byte as the system clock source the X1 and X2 pins are used as crystal or ceramic resonator connection pins For details of the option byte refer to CHAPTER 18 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS Figure 5 6 shows the external circuit of the crystal ceramic oscillator Figure 5 6 Exte...

Page 76: ...7 Examples of Incorrect Resonator Connection 1 2 a Too long wiring of connected circuit b Crossed signal lines VSS X1 X2 VSS X1 X2 PORT c Wiring near high fluctuating current d Current flowing through ground line of oscillator Potential at points A B and C fluctuates VSS X1 X2 High current VSS X1 X2 PORT VDD A B C High current ...

Page 77: ... option byte refer to CHAPTER 18 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS 5 4 4 Prescaler The prescaler divides the clock fX output by the system clock oscillator to generate a clock fXP to be supplied to the peripheral hardware It also divides the clock to peripheral hardware fXP to generate a clock to be supplied to the CPU Remark The clock output by the oscillator ...

Page 78: ...ed internal oscillator is selected as the oscillator the CPU can be started without having to wait for the oscillation stabilization time of the system clock Therefore the start time can be shortened Improvement of expandability If the high speed internal oscillator is selected as the oscillator the X1 and X2 pins can be used as I O port pins For details refer to CHAPTER 4 PORT FUNCTIONS Figures 5...

Page 79: ...C 02H HALT STOP Interrupt Reset signal Interrupt Power application Reset by power on clear High speed internal oscillator selected by option byte Clock division ratio variable during CPU operation VDD 2 1 V 0 1 V Remark PCC Processor clock control register PPCC Preprocessor clock control register 2 Crystal ceramic oscillator If crystal ceramic oscillation is selected by the option byte a clock fre...

Page 80: ... The oscillation stabilization time that elapses after the STOP mode is released is selected by the oscillation stabilization time select register OSTS a The internal reset signal is generated by the power on clear function on power application the option byte is referenced after reset and the system clock is selected b After the high speed internal oscillation clock is generated the option byte i...

Page 81: ...processor clock control register 3 External clock input circuit If external clock input is selected by the option byte the following is possible High speed operation The accuracy of processing is improved as compared with high speed internal oscillation 8 MHz TYP because an oscillation frequency of 1 to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied I...

Page 82: ...er application the option byte is referenced after reset and the system clock is selected b The option byte is referenced and the system clock is selected Then the external clock operates as the system clock Figure 5 13 Status Transition of Default Start by External Clock Input HALT STOP HALT instruction STOP instruction VDD 2 1 V 0 1 V Start with PCC 02H PPCC 02H Interrupt Reset signal Interrupt ...

Page 83: ...cannot be stopped by software If it is specified that the low speed internal oscillator can be stopped by software oscillation can be started or stopped by using the low speed internal oscillation mode register LSRCM If it is specified that it cannot be stopped by software the clock source of WDT is fixed to the low speed internal oscillation clock fRL The low speed internal oscillator is independ...

Page 84: ...xed to fRL Low speed internal oscillator can be stopped Low speed internal oscillator cannot be stopped Low speed internal oscillator stops LSRSTOP 1 Reset signal Power application Reset by power on clear Select by option byte if low speed internal oscillator can be stopped or not VDD 2 1 V 0 1 V Note The clock source of the watchdog timer WDT is selected from fX or fRL or it may be stopped For de...

Page 85: ...th or more of a signal input externally Valid level pulse width 2 fXP or more 3 Pulse width measurement 16 bit timer event counter 00 can measure the pulse width of an externally input signal Valid level pulse width 2 fXP or more 4 Square wave output 16 bit timer event counter 00 can output a square wave with any selected frequency Cycle 2 to 65536 2 count clock cycle 5 PPG output 16 bit timer eve...

Page 86: ...de register 3 PM3 Port register 3 P3 Figures 6 1 shows a block diagram of these counters Figure 6 1 Block Diagram of 16 bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC00 TI010 TO00 INTP2 P31 fXP fXP 22 fXP 28 fX TI000 INTP0 P30 Prescaler mode register 00 PRM00 2 PRM001 PRM000 CRC002 16 bit timer capture compare register 010 CR010 Match Match 16 bit timer counter 00 ...

Page 87: ...ulse output mode Cautions 1 Even if TM00 is read the value is not captured by CR010 2 When TM00 is read count misses do not occur since the input of the count clock is temporarily stopped and then resumed after the read 2 16 bit timer capture compare register 000 CR000 CR000 is a 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a captu...

Page 88: ...lear start mode entered on match between TM00 and CR000 This means a 1 pulse count operation cannot be performed when this register is used as an external event counter However in the free running mode and in the clear start mode using the valid edge of TI000 pin if CR000 is set to 0000H an interrupt request INTTM000 is generated when CR000 changes from 0000H to 0001H following overflow FFFFH 2 If...

Page 89: ... to select the valid edge of the TI000 pin as the capture trigger The TI000 valid edge is set by means of prescaler mode register 00 PRM00 refer to Table 6 3 Table 6 3 CR010 Capture Trigger and Valid Edge of TI000 Pin CRC002 1 CR010 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges ...

Page 90: ...er Event Counter 00 The following six types of registers are used to control 16 bit timer event counter 00 16 bit timer mode control register 00 TMC00 Capture compare control register 00 CRC00 16 bit timer output control register 00 TOC00 Prescaler mode register 00 PRM00 Port mode register 3 PM3 Port register 3 P3 1 16 bit timer mode control register 00 TMC00 This register sets the 16 bit timer op...

Page 91: ...000H the OVF00 flag is set to 1 6 Even if the OVF00 flag is cleared before the next count clock is counted before TM00 becomes 0001H after the occurrence of a TM00 overflow the OVF00 flag is re set newly and clear is disabled 7 The capture operation is performed at the fall of the count clock An interrupt request input INTTM0n0 however occurs at the rise of the next count clock Remark TM00 16 bit ...

Page 92: ...gger selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase Note CRC000 CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register Note When the CRC001 bit value is 1 capture is not performed if both the rising and falling edges have been selected as the valid edges of the TI000 pin Cautions 1 The timer operation must be...

Page 93: ... inversion operation LVS00 LVR00 Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TOC001 Timer output F F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 Timer output control 0 Disables output output fixed to level 0 1 Enables output Note The one shot pulse output mo...

Page 94: ...l 7 6 5 4 3 2 1 0 PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000 ES110 ES100 TI010 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES010 ES000 TI000 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 Count clock selection 0 0 fXP 10 MHz 0 1 fXP 2 2 2 5 M...

Page 95: ... edge of the TI0n0 pin a rising edge is detected immediately after the TM00 operation is enabled 4 The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fXP and in the latter case the count clock is selected by prescaler mode register 00 PRM00 The capture operation is not ...

Page 96: ...he set value Caution Changing the CR000 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 bit Timer Event Counter 00 17 Changing compare register during timer operation Remark For how to enable the INTTM000 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS Interrupt requests are generated repeatedly using the count value set in 16 bit timer ...

Page 97: ...ing 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with the interval timer See the description of the respective control registers for details Figure 6 11 Interval Timer Configuration Diagram 16 bit ...

Page 98: ... from 0 Thus if the value M after the CR000 change is smaller than that N before the change it is necessary to restart the timer after changing CR000 Figure 6 13 Timing After Change of Compare Register During Timer Count Operation N M N M CR000 N M Count clock TM00 count value X 1 X FFFFH 0000H 0001H 0002H Remark N X M 6 4 2 External event counter operation Setting The basic operation setting proc...

Page 99: ...rried out only when the valid edge of the TI000 pin is detected twice after sampling with the internal clock fXP noise with a short pulse width can be removed Figure 6 14 Control Register Settings in External Event Counter Mode with Rising Edge Specified a Capture compare control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register b Prescaler m...

Page 100: ... Figure 6 16 External Event Counter Operation Timing with Rising Edge Specified 1 INTTM000 generation timing immediately after operation starts Counting is started after a valid edge is detected twice CR000 INTTM000 0000H 0001H 0002H 0003H N 2 N 1 N 0000H 0001H 0002H N 1 2 3 Count starts TI000 pin input TM00 count value 2 INTTM000 generation timing after INTTM000 has been generated twice CR000 INT...

Page 101: ...width is sampled in the count clock cycle selected by prescaler mode register 00 PRM00 and the valid level of the TI000 or TI010 pin is detected twice thus eliminating noise with a short pulse width Figure 6 17 CR010 Capture Operation with Rising Edge Specified Count clock TM00 TI000 Rising edge detection CR010 INTTM010 N 3 N 2 N 1 N N 1 N Setting The basic operation setting procedure is as follow...

Page 102: ...on The measurable pulse width in this operation example is up to 1 cycle of the timer counter Figure 6 18 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register When TI000 and CR010 Are Used a Capture compare control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register CR010 used as capture registe...

Page 103: ...6 bit timer capture compare register 010 CR010 Internal bus INTTM010 Selector Figure 6 20 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified t 0000H 0000H FFFFH 0001H D0 D0 D1 D0 t D3 D2 t D2 D1 t D1 D2 D3 D2 D3 D0 1 D1 D1 1 Note Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 Note The carry flag is set t...

Page 104: ... using the count clock cycle selected by prescaler mode register 00 PRM00 and a capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice thus eliminating noise with a short pulse width Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter Figure 6 21 Control Register Settings for Measurement of Two Pulse Widths ...

Page 105: ...le to measure the pulse width of the signal input to the TI000 pin When the rising or falling edge specified by bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRM00 is input to the TI000 pin the value of TM00 is taken into 16 bit timer capture compare register 010 CR010 and an interrupt request signal INTTM010 is set Also when the inverse edge to that of the capture operation is input ...

Page 106: ...g edge for pulse width detection Setting invalid setting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 0 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Free running mode Note If the valid edge of the TI000 pin is specified to be both the rising and falling edges 16 bit timer capture compare register 000 CR000 cannot perform the capture operation When the CRC001 bit value...

Page 107: ...e rising and falling edges as the valid edges of the TI000 pin by using bits 4 and 5 ES000 and ES010 of PRM00 When a valid edge of the TI000 pin is detected the count value of 16 bit timer counter 00 TM00 is taken into 16 bit timer capture compare register 010 CR010 and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count Sampling is perfo...

Page 108: ... count clock setting 11 is prohibited Specifies rising edge for pulse width detection Setting invalid setting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 0 TMC001 0 1 OVF00 0 TMC00 Clears and starts at valid edge of TI000 pin Note If the valid edge of the TI000 pin is specified to be both the rising and falling edges 16 bit timer capture compare r...

Page 109: ...6 3 5 Port mode register 3 PM3 2 For how to enable the INTTM000 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS A square wave with any selected frequency can be output at intervals determined by the count value preset to 16 bit timer capture compare register 000 CR000 The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 1 by setting bit 0 TOE00 and bit 1 T...

Page 110: ... is prohibited Does not invert output on match between TM00 and CR010 Disables one shot pulse output d 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 TMC001 0 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with square wave output See the description of the respective control ...

Page 111: ... count clock by using the PRM00 register 6 Set the TMC00 register to start the operation see Figure 6 29 for the set value Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 bit Timer Event Counter 00 17 Changing compare register during timer operation Remarks 1 For the setting of the TO00 pin see 6 3 5 Port m...

Page 112: ...F F setting 11 is prohibited Inverts output on match between TM00 and CR010 Disables one shot pulse output c Prescaler mode register 00 PRM00 ES110 0 1 ES100 0 1 ES010 0 1 ES000 0 1 3 0 2 0 PRM001 0 1 PRM000 0 1 PRM00 Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited d 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 ...

Page 113: ...TM00 Clear circuit Noise eliminator fXP fXP fXP 22 fXP 28 TI000 INTP0 P30 16 bit timer capture compare register 010 CR010 TO00 TI010 INTP2 P31 Selector Output controller Figure 6 31 PPG Output Operation Timing t 0000H 0000H 0001H 0001H M 1 Count clock TM00 count value TO00 Pulse width M 1 t 1 cycle N 1 t N CR000 capture value CR010 capture value M M N 1 N N Clear Clear Remark 0000H M N FFFFH ...

Page 114: ... by setting bit 6 OSPT00 of the TOC00 register to 1 by software By setting the OSPT00 bit to 1 16 bit timer event counter 00 is cleared and started and its output becomes active at the count value N set in advance to 16 bit timer capture compare register 010 CR010 After that the output becomes inactive at the count value M set in advance to 16 bit timer capture compare register 000 CR000 Note Even...

Page 115: ...5 4 3 CRC00 CRC002 CRC001 CRC000 CR000 as compare register CR010 as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts output upon match between TM00 and CR010 Sets on...

Page 116: ...igure 6 34 and by using the valid edge of the TI000 pin as an external trigger The valid edge of the TI000 pin is specified by bits 4 and 5 ES000 ES010 of prescaler mode register 00 PRM00 The rising falling or both the rising and falling edges can be specified When the valid edge of the TI000 pin is detected the 16 bit timer event counter is cleared and started and the output becomes active at the...

Page 117: ... CRC00 0 0 0 0 0 7 6 5 4 3 CRC00 CRC002 CRC001 CRC000 CR000 used as compare register CR010 used as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 TOC001 TOE00 OSPE00 OSPT00 TOC004 LVS00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts output upon match...

Page 118: ...ied 0000H N N N N N M M M M M N 1 N 2 M 1 M 2 M 2 M 1 0001H 0000H Count clock TM00 count value CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output When TMC00 is set to 08H TM00 count starts t Caution 16 bit timer counter 00 starts operating as soon as a value other than 0 0 operation stop mode is set to the TMC003 and TMC002 bits Remark N M ...

Page 119: ...topped and then resumed after the read 4 If the timer is stopped timer counts and timer interrupts do not occur even if a signal is input to the TI000 TI010 pins 3 Setting of 16 bit timer capture compare registers 000 010 CR000 CR010 1 Set 16 bit timer capture compare register 000 CR000 to other than 0000H in the clear start mode entered on match between TM00 and CR000 This means a 1 pulse count o...

Page 120: ...lways set data to PRM00 after stopping the timer operation 9 Valid edge setting Set the valid edge of the TI000 pin with bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRM00 after stopping the timer operation 10 One shot pulse output One shot pulse output normally operates only in the free running mode or in the clear start mode at the valid edge of the TI000 pin Because an overflow do...

Page 121: ...tion of OVF00 flag 1 The OVF00 flag is also set to 1 in the following case Either of the clear start mode entered on a match between TM00 and CR000 clear start at the valid edge of the TI000 pin or free running mode is selected CR000 is set to FFFFH When TM00 is counted up from FFFFH to 0000H Figure 6 37 Operation Timing of OVF00 Flag Count clock CR000 TM00 OVF00 INTTM000 FFFFH FFFEH FFFFH 0000H 0...

Page 122: ... set as the count clock do not set the clear start mode and the capture trigger at the valid edge of the TI000 pin 2 If both the rising and falling edges are selected as the valid edges of the TI000 pin capture is not performed 3 When the CRC001 bit value is 1 the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected but the input from the TI010 pin ...

Page 123: ... clock 5 Enable the timer output inversion operation at the match between TM00 and CR000 TOC001 1 6 Clear the interrupt request flag of INTTM000 TMIF000 0 7 Enable the INTTM000 interrupt TMMK000 0 Changing duty CR010 1 Disable the timer output inversion operation at the match between TM00 and CR010 TOC004 0 2 Disable the INTTM000 interrupt TMMK000 1 3 Rewrite CR010 4 Wait for 1 cycle of the TM00 c...

Page 124: ...d Remark n 0 1 2 The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fXP and in the latter case the count clock is selected by prescaler mode register 00 PRM00 The capture operation is not performed until the valid edge is sampled and the valid level is detected twice thus ...

Page 125: ...haracteristics refer to CHAPTER 21 and CHAPTER 22 ELECTRICAL SPECIFICATIONS 2 When an external waveform is input to 16 bit timer event counter 00 it is sampled by the noise limiter circuit and thus an error occurs on the timing to become valid inside the device Count clock fsam TI000 Input pulse through noise limiter circuit Sampling time on filter Remark The count clock fsam can be selected using...

Page 126: ...me Resolution 2 6 fXP 8 μs 2 14 fXP 2 05 ms 2 6 fXP 8 μs 2 8 fXP 32 μs 2 16 fXP 8 19 ms 2 8 fXP 32 μs 2 10 fXP 128 μs 2 18 fXP 32 7 ms 2 10 fXP 128 μs fXP 8 0 MHz 2 16 fXP 8 19 ms 2 24 fXP 2 01 s 2 16 fXP 8 19 ms 2 6 fXP 6 4 μs 2 14 fXP 1 64 ms 2 6 fXP 6 4 μs 2 8 fXP 25 6 μs 2 16 fXP 6 55 ms 2 8 fXP 25 6 μs 2 10 fXP 102 μs 2 18 fXP 26 2 ms 2 10 fXP 102 μs fXP 10 0 MHz 2 16 fXP 6 55 ms 2 24 fXP 1 6...

Page 127: ... counter 80 TM80 Register 8 bit compare register 80 CR80 Control register 8 bit timer mode control register 80 TMC80 Figure 7 1 Block Diagram of 8 bit Timer 80 Internal bus Internal bus 8 bit compare register 80 CR80 Match 8 bit timer counter 80 TM80 Clear INTTM80 fXP 26 fXP 216 TCE80 TCL801 TCL800 8 bit timer mode control register 80 TMC80 fXP 28 fXP 210 Selector Remark fXP Oscillation frequency ...

Page 128: ...igure 7 2 Format of 8 bit Compare Register 80 CR80 Symbol CR80 Address FFCDH After reset Undefined W 7 6 5 4 3 2 1 0 Caution When changing the value of CR80 be sure to stop the timer operation If the value of CR80 is changed with the timer operation enabled a match interrupt request signal is generated immediately and the timer may be cleared 2 8 bit timer counter 80 TM80 This 8 bit register count...

Page 129: ... clears TMC80 to 00H Figure 7 4 Format of 8 bit Timer Mode Control Register 80 TMC80 Address FFCCH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TMC80 TCE80 0 0 0 0 TCL801 TCL800 0 TCE80 Control of operation of TM80 0 Stop operation clear TM80 to 00H 1 Enable operation Selection of count clock of 8 bit timer 80 TCL801 TCL800 fXP 8 0 MHz fXP 10 0 MHz 0 0 fXP 2 6 125 kHz 156 3 kHz 0 1 fXP 2 8 31 25 kHz...

Page 130: ...ue of CR80 is changed with the timer operation enabled a match interrupt request signal may be generated immediately 2 If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by using an 8 bit memory manipulation instruction the error of one cycle after the timer is started may be 1 clock or more refer to 7 5 1 Error when timer starts Therefore be sure to follow th...

Page 131: ...Timing of Interval Timer Operation Clear Clear Count start Interval time Interval time Count clock TM80 count value CR80 TCE80 INTTM80 N 01H 00H N 01H 00H N 00H 01H N N N N t Interrupt request generated Interrupt request generated Remark Interval time N 1 t N 00H to FFH ...

Page 132: ...fer to Figure 7 6 Figure 7 6 Case Where Error of 1 5 Clocks Max Occurs 8 bit timer counter 80 TM80 Count pulse Clear signal Selected clock TCE80 Delay A Delay B Selected clock TCE80 Clear signal Count pulse TM80 count value 00H 01H 02H 03H Delay A Delay B If the timer is started when the selected clock is high and if delay A delay B an error of up to 1 5 clocks occurs 2 Setting of 8 bit compare re...

Page 133: ... 8 bit Timer H1 8 bit timer H1 consists of the following hardware Table 8 1 Configuration of 8 bit Timer H1 Item Configuration Timer register 8 bit timer counter H1 Registers 8 bit timer H compare register 01 CMP01 8 bit timer H compare register 11 CMP11 Timer output TOH1 Control registers 8 bit timer H mode register 1 TMHMD1 Port mode register 4 PM4 Port register 4 P4 Figure 8 1 shows a block dia...

Page 134: ...D10 TOLEV1 TOEN1 8 bit timer H mode register 1 TMHMD1 8 bit timer H compare register 11 CMP11 Decoder TOH1 P42 INTTMH1 Selector fXP fXP 22 fXP 24 fXP 26 fXP 212 fRL 27 Interrupt generator Output controller Level inversion 1 0 F F R 8 bit timer counter H1 PWM mode signal Timer H enable signal Clear 3 2 8 bit timer H compare register 01 CMP01 Output latch P42 PM42 ...

Page 135: ...it Timer H Compare Register 11 CMP11 Symbol CMP11 Address FF0FH After reset 00H R W 7 6 5 4 3 2 1 0 CMP11 can be rewritten during timer count operation If the CMP11 value is rewritten during timer operation the compare value after the rewrite takes effect at the timing at which the count value and the compare value before the rewrite match If the timing at which the count value and compare value m...

Page 136: ...s are used to control 8 bit timer H1 8 bit timer H mode register 1 TMHMD1 Port mode register 4 PM4 Port register 4 P4 1 8 bit timer H mode register 1 TMHMD1 This register controls the mode of timer H This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H ...

Page 137: ...l timer mode PWM output mode Setting prohibited TMMD11 0 1 TMMD10 0 0 Timer operation mode Low level High level TOLEV1 0 1 Timer output level control in default mode Disable output Enable output TOEN1 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 Cautions 1 When TMHE1 1 setting the other bits of the TMHMD1 register is prohibited 2 In the PWM output mode be sure to set 8 bit timer H com...

Page 138: ... the output latch of P42 to 0 PM4 can be set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets this register to FFH Figure 8 5 Format of Port Mode Register 4 PM4 Address FF24H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 PM4n P4n pin I O mode selection n 0 to 7 0 Output mode output buffer on 1 Input mode output buffer off ...

Page 139: ...tput from TOH1 1 Usage Generates the INTTMH1 signal repeatedly at the same interval 1 Set each register Figure 8 6 Register Setting During Interval Timer Square Wave Output Operation i Setting timer H mode register 1 TMHMD1 0 0 1 0 1 0 1 0 0 0 1 0 1 TMMD10 TOLEV1 TOEN1 CKS11 CKS12 TMHE1 TMHMD1 CKS10 TMMD11 Timer output setting Timer output level inversion setting Interval timer mode setting Count ...

Page 140: ... 8 bit timer counter H1 clear 2 Level inversion match interrupt occurrence 8 bit timer counter H1 clear 3 1 1 The count operation is enabled by setting the TMHE1 bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the values of 8 bit timer counter H1 and the CMP01 register match the value of 8 bit timer counter H1 is cleared the TOH1 output level is ...

Page 141: ...e Output Operation 2 2 b Operation when CMP01 FFH 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP01 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 00H 00H Interval time ...

Page 142: ... an arbitrary duty and arbitrary cycle can be set is output 1 Set each register Figure 8 8 Register Setting in PWM Output Mode i Setting timer H mode register 1 TMHMD1 0 0 1 0 1 0 1 1 0 0 1 1 TMMD10 TOLEV1 TOEN1 CKS11 CKS12 TMHE1 TMHMD1 CKS10 TMMD11 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock fCNT selection Count operation stopped ii Setting CMP0...

Page 143: ...ter is N the setting value of the CMP11 register is M and the count clock frequency is fCNT the PWM pulse output cycle and duty are as follows PWM pulse output cycle N 1 fCNT Duty Active width Total width of PWM M 1 N 1 Cautions 1 In PWM output mode the setting value for the CMP11 register can be changed during timer count operation However three operation clocks signal selected using the CKS12 to...

Page 144: ...5H 01H 1 2 3 4 1 The count operation is enabled by setting the TMHE1 bit to 1 Start 8 bit timer counter H1 by masking one count clock to count up At this time TOH1 output remains inactive when TOLEV1 0 2 When the values of 8 bit timer counter H1 and the CMP01 register match the TOH1 output level is inverted the value of 8 bit timer counter H1 is cleared and the INTTMH1 signal is output 3 When the ...

Page 145: ...n CMP01 FFH CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP11 FFH 00H c Operation when CMP01 FFH CMP11 FEH Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP11 FFH FEH ...

Page 146: ... Manual U17446EJ3V1UD 146 Figure 8 9 Operation Timing in PWM Output Mode 3 4 d Operation when CMP01 01H CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP11 00H ...

Page 147: ... timer counter H1 is cleared the TOH1 output becomes active and the INTTMH1 signal is output 4 If the CMP11 register value is changed the value is latched and not transferred to the register When the values of 8 bit timer counter H1 and the CMP11 register before the change match the value is transferred to the CMP11 register and the CMP11 register value is changed 2 However three count clocks or m...

Page 148: ...al Oscillation Clock Operation During System Clock Operation 2 11 fRL 4 27 ms 2 13 fX 819 2 μs 2 12 fRL 8 53 ms 2 14 fX 1 64 ms 2 13 fRL 17 07 ms 2 15 fX 3 28 ms 2 14 fRL 34 13 ms 2 16 fX 6 55 ms 2 15 fRL 68 27 ms 2 17 fX 13 11 ms 2 16 fRL 136 53 ms 2 18 fX 26 21 ms 2 17 fRL 273 07 ms 2 19 fX 52 43 ms 2 18 fRL 546 13 ms 2 20 fX 104 86 ms Remarks 1 fRL Low speed internal oscillation clock frequency...

Page 149: ...hdog timer cannot be stopped The watchdog timer can be stopped Note 2 Notes 1 As long as power is being supplied low speed internal oscillator cannot be stopped except in the reset period 2 The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer 1 If the clock source is fX clock supply to the watchdog timer is stopped unde...

Page 150: ...gram of Watchdog Timer Clock input controller Output controller Internal reset signal WDCS2 Internal bus WDCS1 WDCS0 WDCS3 WDCS4 0 1 1 Selector 16 bit counter or 213 fX to 220 fX Watchdog timer enable register WDTE Watchdog timer mode register WDTM 3 2 Clear Option byte to set low speed internal oscillator cannot be stopped or low speed internal oscillator can be stopped by software fRL 22 fX 24 2...

Page 151: ...set 67H R W WDCS4 Note 1 WDCS3 Note 1 Operation clock selection 0 0 Low speed internal oscillation clock fRL 0 1 System Clock fX 1 Watchdog timer operation stopped Overflow time setting WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 During low speed internal oscillation clock operation During system clock operation 0 0 0 2 11 fRL 4 27 ms 2 13 fX 819 2 μs 0 0 1 2 12 fRL 8 53 ms 2 14 fX 1 64 ms 0 1 0 2 13 f...

Page 152: ... overflow time for the watchdog timer so that enough overflow time is secured Example 1 byte writing 200 μs MIN 1 block deletion 10 ms MIN Remarks 1 fRL Low speed internal oscillation clock frequency 2 fX System clock oscillation frequency 3 Don t care 4 Figures in parentheses apply to operation at fRL 480 kHz MAX fX 10 MHz 2 Watchdog timer enable register WDTE Writing ACH to WDTE clears the watch...

Page 153: ...ster WDTM by an 8 bit memory manipulation instructionNotes 1 2 Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 The operation clock low speed internal oscillation clock cannot be changed If any value is written to bits 3 and 4 WDCS3 WDCS4 of WDTM it is ignored 2 As soon as WDTM is written the ...

Page 154: ...d Is Selected by Option Byte Reset WDT clock fRL Overflow time 546 13 ms MAX STOP WDT count continues HALT WDT count continues STOP instruction HALT instruction WDT clock is fixed to fRL Select overflow time settable only once WDT clock fRL Overflow time 4 27 ms to 546 13 ms MAX WDT count continues Interrupt Interrupt WDTE ACH Clear WDT counter ...

Page 155: ...ter the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As soon as WDTM is written the counter of the watchdog timer is cleared 2 Set bits 7 6 and 5 to 0 1 1 respectively Do not set the other values 3 At the first write if the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and respectively an internal reset signal is not generated even...

Page 156: ...DT count continues STOP WDT count stops HALT WDT count stops STOP instruction HALT instruction Interrupt Interrupt WDTE ACH Clear WDT counter WDT operation stops WDCS4 1 WDT clock fX Overflow time 213 fX to 220 fX WDT count continues WDT clock fX Select overflow time settable only once WDT clock fRL WDT count stops WDTE ACH Clear WDT counter LSRSTOP 1 LSRSTOP 0 STOP WDT count stops HALT WDT count ...

Page 157: ...select register OSTS after operation stops in the case of crystal ceramic oscillation and then counting is started again using the operation clock before the operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 9 6 Operation in STOP Mode WDT Operation Clock Clock to Peripheral Hardware 1 CPU clock Crystal ceramic oscillation clock Operation stopped Operatin...

Page 158: ...value Figure 9 7 Operation in STOP Mode WDT Operation Clock Low Speed Internal Oscillation Clock 1 CPU clock Crystal ceramic oscillation clock Operating Oscillation stabilization time Normal operation Oscillation stabilization time set by OSTS register Watchdog timer Operation stopped Operating fRL fCPU CPU operation Normal operation STOP Oscillation stopped Operation stoppedNote 2 CPU clock High ...

Page 159: ...gardless of whether the operation clock of the watchdog timer is the system clock fX or low speed internal oscillation clock fRL After HALT mode is released counting is started again using the operation clock before the operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 9 8 Operation in HALT Mode Watchdog timer Operating fX or fRL fCPU CPU operation Norma...

Page 160: ...ersion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3 Each time an A D conversion operation ends an interrupt request INTAD is generated Figure 10 1 shows the timing of sampling and A D conversion and Table 10 1 shows the sampling time and A D conversion time Figure 10 1 Timing of A D Converter Sampling and A D Conversion ADCS Conversion time Conversion time Sam...

Page 161: ... 3 below are satisfied Example When AVREF 2 7 V fXP 8 MHz The sampling time is 11 0 μs or more and the A D conversion time is 14 0 μs or more and 100 μs or less Set FR2 FR1 and FR0 0 1 1 or 1 1 1 2 Set the sampling time as follows AVREF 4 5 V 1 0 μs or more AVREF 4 0 V 2 4 μs or more AVREF 2 85 V 3 0 μs or more AVREF 2 7 V 11 0 μs or more 3 Set the A D conversion time as follows AVREF 4 5 V 3 0 μs...

Page 162: ...are 1 ANI0 to ANI3 pins These are the analog input pins of the 4 channel A D converter They input analog signals to be converted into digital signals Pins other than the one selected as the analog input pin by the analog input channel specification register ADS can be used as I O port pins 2 Sample hold circuit The sample hold circuit samples the input signal of the analog input pin selected by th...

Page 163: ...ch time A D conversion is completed and the ADCRH register holds the result of A D conversion in its higher 8 bits 8 Controller When A D conversion has been completed INTAD is generated 9 AVREF pin This pin inputs an analog power reference voltage to the A D converter When the A D converter is not used connect this pin to VDD The signal input to ANI0 to ANI3 is converted into a digital signal base...

Page 164: ...Converter The A D converter uses the following six registers A D converter mode register ADM Analog input channel specification register ADS 10 bit A D conversion result register ADCR 8 bit A D conversion result register ADCRH Port mode control register 2 PMC2 Port mode register 2 PM2 ...

Page 165: ...μs 1 0 0 AVREF 4 0 V 24 fXP 72 fXP 3 0 μs 9 0 μs 2 4 μs 7 2 μs 1 1 0 96 fXP 144 fXP 12 0 μs 18 0 μs 9 6 μs 14 4 μs 1 0 1 48 fXP 96 fXP 6 0 μs 12 0 μs 4 8 μs 9 6 μs 0 1 0 48 fXP 72 fXP 6 0 μs 9 0 μs 4 8 μs 7 2 μs 0 0 1 AVREF 2 85 V 24 fXP 48 fXP 3 0 μs 6 0 μs Setting prohibited 2 4 μs Setting prohibited 4 8 μs 1 1 1 176 fXP 224 fXP 22 0 μs 28 0 μs 17 6 μs 22 4 μs 0 1 1 AVREF 2 7 V 88 fXP 112 fXP 11...

Page 166: ...tion stabilization Therefore when ADCS is set to 1 after 1 μs or more has elapsed from the time ADCE is set to 1 the conversion result at that time has priority over the first conversion result If the ADCS is set to 1 without waiting for 1 μs or longer ignore the first conversion data Table 10 2 Settings of ADCS and ADCE ADCS ADCE A D Conversion Operation 0 0 Stop status DC power consumption path ...

Page 167: ...W Symbol Caution Be sure to clear bits 2 to 7 of ADS to 0 3 10 bit A D conversion result register ADCR This register is a 16 bit register that stores the A D conversion result The higher six bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the successive approximation register and is stored in ADCR in order starting from bit 1 of FF19H FF19H indicates the high...

Page 168: ...output latches of P20 to P23 may be 0 or 1 PMC2 and PM2 are set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears PMC2 to 00H and sets PM2 to FFH Figure 10 8 Format of Port Mode Control Register 2 PMC2 Address FF84H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Operation mode specification n 0 to 3 0 Port mode 1 A D converter...

Page 169: ...9 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The D A converter voltage tap is selected according to the preset value of bit 9 as described below Bit 9 1 3 4 AVREF Bit 9 0 1 4 AVREF The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows Analog input voltage Voltage tap Bit 8 1 Analog input voltage Voltage t...

Page 170: ... A D conversion operations are performed continuously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to ADM or the analog input channel specification register ADS during an A D conversion operation the conversion operation is initialized and if the ADCS bit is set 1 conversion starts again from the beginning Reset input makes the A ...

Page 171: ...Function which returns integer part of value in parentheses VAIN Analog input voltage AVREF AVREF pin voltage ADCR 10 bit A D conversion result register ADCR value Figure 10 11 shows the relationship between the analog input voltage and the A D conversion result Figure 10 11 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 03FFH 03FEH 03FDH 0003H 0002H 000...

Page 172: ...d in the A D conversion result register ADCR ADCRH and an interrupt request signal INTAD is generated Once the A D conversion has started and when one A D conversion has been completed the next A D conversion operation is immediately started The A D conversion operations are repeated until new data is written to ADS If ADM or ADS is written during A D conversion the A D conversion operation under ...

Page 173: ... D conversion data to the A D conversion result register ADCR ADCRH Change the channel 7 Change the channel using bits 1 and 0 ADS1 ADS0 of ADS 8 An interrupt request signal INTAD is generated 9 Transfer the A D conversion data to the A D conversion result register ADCR ADCRH Complete A D conversion 10 Clear ADCS to 0 11 Clear ADCE to 0 Cautions 1 Make sure the period of 1 to 4 is 1 μs or more 2 I...

Page 174: ...verall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error integ...

Page 175: ... and the ideal value Figure 10 15 Zero Scale Error Figure 10 16 Full Scale Error 111 011 010 001 Zero scale error Ideal line 000 0 1 2 3 AVREF Digital output Lower 3 bits Analog input LSB 111 110 101 000 0 AVREF 3 Full scale error Ideal line Analog input LSB Digital output Lower 3 bits AVREF 2 AVREF 1 AVREF Figure 10 17 Integral Linearity Error Figure 10 18 Differential Linearity Error 0 AVREF Dig...

Page 176: ...erter mode register ADM write or analog input channel specification register ADS write upon the end of conversion ADM or ADS write has priority ADCR ADCRH write is not performed nor is the conversion end interrupt signal INTAD generated 4 Noise countermeasures To maintain the 10 bit resolution attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI3 1 Connect a capacitor with a...

Page 177: ...rtest conversion time of the reference voltage is used to perform sufficient sampling it is recommended to make the output impedance of the analog input source 1 kΩ or lower or attach a capacitor of around 0 01 μF to 0 1 μF to the ANI0 to ANI3 pins see Figure 10 19 7 Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the analog input channel specification register A...

Page 178: ...ther than the above may cause an incorrect conversion result to be read 10 Operating current at conversion waiting mode The DC characteristic of the operating current during the STOP mode is not satisfied due to the conversion waiting mode only the comparator consumes power when bit 7 ADCS and bit 0 ADCE of the A D converter mode register ADM are set to 0 and 1 respectively 11 Internal equivalent ...

Page 179: ... bits More than 11 bits can be identified for synchronous break field reception SBF reception flag provided Cautions 1 The TXD6 output inversion function inverts only the transmission side and not the reception side To use this function the reception side must be ready for reception of inverted data 2 If clock supply to serial interface UART6 is not stopped e g in the HALT mode normal operation co...

Page 180: ...t and corrects the baud rate error Therefore communication is possible when the baud rate error in the slave is 15 or less Figures 11 1 and 11 2 outline the transmission and reception operations of LIN Figure 11 1 LIN Transmission Operation LIN bus Wakeup signal frame 8 bitsNote 1 55H transmission Data transmission Data transmission Data transmission Data transmission 13 bitNote 2 SBF transmission...

Page 181: ...pletion interrupt processing and measure the bit width pulse width of the sync field refer to 6 4 3 Pulse width measurement operations Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed The shift register holds the reset value FFH 4 Calculate the baud rate error from the bit inter...

Page 182: ...xD6 P44 Selector Selector Selector Remark ISC0 ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 11 11 The peripheral functions used in the LIN communication operation are shown below Peripheral functions used External interrupt INTP0 wakeup signal detection Use Detects the wakeup signal edges and detects start of communication 16 bit timer event counter 00 TI000 baud rate erro...

Page 183: ...er 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface transmission status register 6 ASIF6 Clock selection register 6 CKSR6 Baud rate generator control register 6 BRGC6 Asynchronous serial interface co...

Page 184: ...register 6 RXB6 RXD6 P44 TI000 INTP0Note INTSR6 Baud rate generator Filter INTSRE6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface transmission status register 6 ASIF6 Transmission control Registers fXP fXP 2 fXP 22 fXP 23 fXP 24 fXP 25 fXP 26 fXP 27 fXP 28 fXP 29 fXP 210 fXP 211 8 Rec...

Page 185: ...its In LSB fast transmission data is transferred to bits 0 to 6 of TXB6 and the MSB of TXB6 is not transmitted In MSB fast transmission data is transferred to bits 7 to 1 of TXB6 and the LSB of TXB6 is not transmitted This register can be read or written by an 8 bit memory manipulation instruction Generation of reset signal sets this register to FFH Cautions 1 When starting transmission write tran...

Page 186: ...uring a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 11 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF90H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 Enabling disabling operation of internal operation clock 0 Note 1 Disable operation...

Page 187: ... not occur 1 INTSR6 occurs in case of error at this time INTSRE6 does not occur Notes 1 TXE6 is synchronized by the base clock fXCLK6 set by CKSR6 When re enabling transmission operation set TXE6 to 1 after having set TXE6 to 0 and one clock of the base clock fXCLK6 has elapsed If TXE6 is set to 1 before one clock of the base clock fXCLK6 has elapsed the transmission circuit may not able to be ini...

Page 188: ...emory manipulation instruction Reset signal generation clears this register to 00H if bit 7 POWER6 and bit 5 RXE6 of ASIM6 0 00H is read when this register is read Figure 11 6 Format of Asynchronous Serial Interface Reception Error Status Register 6 ASIS6 Address FF93H After reset 00H R Symbol 7 6 5 4 3 2 1 0 ASIS6 0 0 0 0 0 PE6 FE6 OVE6 PE6 Status flag indicating parity error 0 If POWER6 0 and RX...

Page 189: ...R6 0 or TXE6 0 or if data is transferred to transmit shift register 6 TXS6 1 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If POWER6 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer 1 If data is transferred from transmit buffer register 6 TXB6 if data transmi...

Page 190: ...ck Selection Register 6 CKSR6 Address FF96H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock fXCLK6 selection 0 0 0 0 fXP 10 MHz 0 0 0 1 fXP 2 5 MHz 0 0 1 0 fXP 2 2 2 5 MHz 0 0 1 1 fXP 2 3 1 25 MHz 0 1 0 0 fXP 2 4 625 kHz 0 1 0 1 fXP 2 5 312 5 kHz 0 1 1 0 fXP 2 6 156 25 kHz 0 1 1 1 fXP 2 7 78 13 kHz 1 0 0 0 fXP 2 8 39 06 kHz 1 0 0 ...

Page 191: ...s FF97H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6 8 0 0 0 0 1 0 0 1 9 fXCLK6 9 0 0 0 0 1 0 1 0 10 fXCLK6 10 1 1 1 1 1 1 0 0 252 fXCLK6 252 1 1 1 1 1 1 0 1 253 fXCLK6 253 1 1 1 1 1 1 1 0 254 fXCLK6 254 ...

Page 192: ...ion when bit 7 POWER6 and bit 6 TXE6 of ASIM6 are 1 or when bit 7 POWER6 and bit 5 RXE6 of ASIM6 are 1 if 0 data has been written to ASICL6 by SBRT6 and SBTT6 Figure 11 10 Format of Asynchronous Serial Interface Control Register 6 ASICL6 1 2 Address FF98H After reset 16H R W Note Symbol 7 6 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6 SBRF6 SBF reception status flag 0 If POWE...

Page 193: ...s of the SBRF6 flag will be held 1 For details on SBF reception refer to 2 i SBF reception in 11 4 2 Asynchronous serial interface UART mode described later 2 Before setting the SBRT6 bit to 1 make sure that bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Moreover after setting the SBRT6 bit to 1 do not clear the SBRT6 bit to 0 before the SBF reception ends an interrupt request signal is generated 3 The re...

Page 194: ... 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 P30 1 RxD6 P44 ISC0 INTP0 input source selection 0 INTP0 P30 1 RxD6 P44 8 Port mode register 4 PM4 This register sets port 4 input output in 1 bit units When using the P43 TxD6 INTP1 pin for serial interface data output clear PM43 to 0 and set the output latch of P43 to 1 When using the P44 RxD6 pin for serial interface data input set PM44 t...

Page 195: ...peration of internal operation clock 0 Note 1 Disable operation of the internal operation clock fix the clock to low level and asynchronously reset the internal circuit Note 2 TXE6 Enabling disabling transmission 0 Disable transmission operation synchronously reset the transmission circuit RXE6 Enabling disabling reception 0 Disable reception synchronously reset the reception circuit Notes 1 The o...

Page 196: ... Input switch control register ISC Port mode register 4 PM4 Port register 4 P4 The basic procedure of setting an operation in the UART mode is as follows 1 Set the CKSR6 register see Figure 11 8 2 Set the BRGC6 register see Figure 11 9 3 Set bits 0 to 4 ISRM6 SL6 CL6 PS60 PS61 of the ASIM6 register see Figure 11 5 4 Set bits 0 and 1 TXDLV6 DIR6 of the ASICL6 register see Figure 11 10 5 Set bit 7 P...

Page 197: ...M43 P43 PM44 P44 UART6 Operation TxD6 INTP1 P43 RxD6 P44 0 0 0 Note Note Note Note Stop P43 P44 0 1 Note Note 1 Reception P43 RxD6 1 0 0 1 Note Note Transmission TxD6 P44 1 1 1 0 1 1 Transmission reception TxD6 RxD6 Note Can be set as port function Remark don t care POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 PM4 Port mode r...

Page 198: ...ssion reception Start bit Parity bit D7 D6 D5 D4 D3 1 data frame Character bits D2 D1 D0 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface operation mode regi...

Page 199: ...p bit 1 bit Communication data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4 Data length 7 bits LSB first Parity Odd parity Stop bit 2 bits Communication data 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop St...

Page 200: ...ception The number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The ...

Page 201: ... TXB6 is transferred to transmit shift register 6 TXS6 After that the data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request INTST6 is generated Transmission is stopped until the data to be transmitted next is written to TXB6 Figure 11 15 shows the timing of the transmis...

Page 202: ...er continuous transmission is possible Do not write the next transmit data by making a judgment only by the fact that the TXSF6 flag has been set to 1 2 When the interface is used in LIN communication operation the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer ...

Page 203: ...sfer executed necessary number of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurred Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processing Transfer executed necessary number of times Remark TXB6 Transmit buffer register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 transmit buffer data flag TXSF6...

Page 204: ...a 1 Data 2 Data 3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabled using only the TXBF6 bit Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous seri...

Page 205: ...B6 TXS6 TXBF6 TXSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 TXSF6 Bit 0 of ASIF6 POWER6 Bit 7 of asynchronous serial interface operation mode register ASIM6 TXE6 Bit 6 of asynchronous serial interface operati...

Page 206: ...top bit has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Even if a parity error PE6 occurs while reception is in progress reception continues to the reception position of the stop bit and an error interrupt INTSR6 INTSRE6 is gener...

Page 207: ...tion Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 6 RXB6 The error interrupt can be separated into reception completion interrupt INTSR6 and error interrupt INTSRE6 by clearing bit 0 ISRM6 of as...

Page 208: ... LIN Transmission Operation When bit 7 POWER6 of asynchronous serial interface mode register 6 ASIM6 is set to 1 the TxD6 pin outputs high level Next when bit 6 TXE6 of ASIM6 is set to 1 the transmission enabled status is entered and SBF transmission is started by setting bit 5 SBTT6 of asynchronous serial interface control register 6 ASICL6 to 1 Thereafter a low level of bits 13 to 20 set by bits...

Page 209: ...rrupt request INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial interface reception error status register 6 ASIS6 is suppressed and error detection processing of UART communication is not performed In addition data transfer between receive sh...

Page 210: ...n POWER6 0 Transmission counter This counter stops operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 TXB6 If data are continuously transmitted the counter is cleared to 0 again whe...

Page 211: ...e generator BRGC6 MDL67 to MDL60 1 2 POWER6 TXE6 or RXE6 CKSR6 TPS63 to TPS60 fXP fXP 2 fXP 22 fXP 23 fXP 24 fXP 25 fXP 26 fXP 27 fXP 28 fXP 29 fXP 210 fXP 211 fXCLK6 Base clock Remark POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 CKSR6 Clock selection register 6 BRGC6 Baud rate generator control register 6 ...

Page 212: ...60 bits of CKSR6 register k Value set by MDL67 to MDL60 bits of BRGC6 register k 8 9 10 255 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 P...

Page 213: ... 1H 109 9610 0 11 10400 1H 240 10417 0 16 1H 201 10423 0 22 1H 101 10475 0 28 19200 1H 130 19231 0 16 1H 109 19220 0 11 0H 109 19220 0 11 31250 0H 160 31250 0 00 0H 134 31268 0 06 0H 67 31268 0 06 38400 0H 130 38462 0 16 0H 109 38440 0 11 0H 55 38090 0 80 76800 0H 65 76923 0 16 0H 55 76182 0 80 0H 27 77693 1 03 115200 0H 43 116279 0 94 0H 36 116389 1 03 0H 18 116389 1 03 153600 0H 33 151515 1 36 0...

Page 214: ...it Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 11 25 the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 BRGC6 after the start bit has been de...

Page 215: ...d rate error between UART6 and the transmission source can be calculated from the above minimum and maximum baud rate expressions as follows Table 11 5 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks 1 The permissible error of reception depe...

Page 216: ...ected because the timing is initialized on the reception side when the start bit is detected Figure 11 26 Data Frame Length During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL FL FL FL FL FL FLstp Start bit of second byte Start bit Bit 0 Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fXCLK6 the following expr...

Page 217: ...al generation makes MUL0 undefined Caution Although this register is manipulated with a 16 bit memory manipulation instruction it can be also manipulated with an 8 bit memory manipulation instruction When using an 8 bit memory manipulation instruction however access the register by means of direct addressing 2 Multiplication data registers A and B MRA0 and MRB0 These are 8 bit multiplication data ...

Page 218: ...er value 3 CPU clock Start Clear Counter output 16 bit adder 16 bit multiplication result storage register 0 Master MUL0 16 bit multiplication result storage register 0 Slave Multiplication data register A MRA0 Multiplication data register B MRB0 Internal bus 3 bit counter MULST0 Reset Multiplier control register 0 MULC0 ...

Page 219: ...ontrols the multiplier MULC0 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Figure 12 2 Format of Multiplier Control Register 0 MULC0 Address FFD2H After reset 00H RW Symbol 7 6 5 4 3 2 1 0 MULC0 0 0 0 0 0 0 0 MULST0 MULST0 Multiplier operation start control bit Operating status of multiplier 0 Stops operation after resetting coun...

Page 220: ...he selector is added to the data of MUL0 at each CPU clock and the counter value is incremented by one 3 When the 3 bit counter value is 111B MULST0 is cleared and the operation is stopped At this time MUL0 holds the operation result Remark When MULST0 is low the 3 bit counter is cleared Figure 12 3 Multiplier Operation Timing Example of AAH D3H AA D3 1 2 3 000B 001B 010B 011B 100B 101B 110B 111B ...

Page 221: ... M_DATA_B EQU 0FE90H Address B for multipliers A setup for operation MOV M_DATA_A 0AAH MOV M_DATA_B 0D3H Multiplication of M_DATA_A and M_DATA_B MOV A M_DATA_A MOV MRA0 A MOV A M_DATA_B MOV MRB0 A SET1 MULST0 Multiplication start M_LOOP BT MULST0 M_LOOP Waiting for multiplication completion MOVW AX MUL0 Multiplication completion ...

Page 222: ... table address is executed vector interrupt servicing When several interrupt requests are generated at the same time processing takes place in the priority order of the vector interrupt servicing For details on the priority order see Table 13 1 There are nine internal sources and four external sources of maskable interrupts Reset The CPU and SFR are returned to their initial states by the reset si...

Page 223: ...ister is specified TI000 pin valid edge detection when capture register is specified 0010H 7 INTAD End of A D conversion Internal 0012H A 8 INTP2 0016H 9 INTP3 Pin input edge detection External 0018H B 10 INTTM80 Match between TM80 and CR80 001AH 11 INTSRE6 UART6 reception error occurrence 001CH 12 INTSR6 End of UART6 reception 001EH Maskable 13 INTST6 End of UART6 transmission Internal 0020H A RE...

Page 224: ...IF IE Internal bus Interrupt request Vector table address generator Standby release signal B External maskable interrupt Internal bus External interrupt mode registers 0 1 INTM0 INTM1 MK IF IE Vector table address generator Standby release signal Edge detector Interrupt request IF Interrupt request flag IE Interrupt enable flag MK Interrupt mask flag ...

Page 225: ...0 INTM1 Program status word PSW Table 13 2 lists interrupt requests the corresponding interrupt request flags and interrupt mask flags Table 13 2 Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTLVI INTP0 INTP1 INTTMH1 INTTM000 INTTM010 INTAD INTP2 INTP3 INTTM80 INTSRE6 INTSR6 INTST6 LVIIF PIF0 PIF1 TMIFH1 TMIF000 TMIF010 ADIF...

Page 226: ...Format of Interrupt Request Flag Registers 0 1 IF0 IF1 Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0 Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1 0 STIF6 SRIF6 SREIF6 TMIF80 PIF3 PIF2 0 IF Interrupt request flag 0 No interrupt request signal has been issued 1 An interrupt request signal has been issued an interrupt reques...

Page 227: ...Address FFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0 ADMK TMMK010 TMMK000 TMMKH1 PMK1 PMK0 LVIMK 1 Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1 1 STMK6 SRMK6 SREMK6 TMMK80 PMK3 PMK2 1 MK Interrupt servicing control 0 Enables interrupt servicing 1 Disables interrupt servicing Caution Because P30 P31 P41 and P43 have an alternate function as external interrupt inputs when the...

Page 228: ...e selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 INTP1 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES01 ES00 INTP0 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Cautions 1 Be sure to clear bits 0 and 1 to ...

Page 229: ...sable interrupts To enable interrupts clear PIF3 to 0 then clear PMK3 to 0 5 Program status word PSW The program status word is used to hold the instruction execution result and the current status of the interrupt requests The IE flag used to enable and disable maskable interrupts is mapped to PSW PSW can be read and write accessed in 8 bit units as well as using bit manipulation instructions and ...

Page 230: ... of Maskable Interrupt Request to Servicing Minimum Time Maximum Time Note 9 clocks 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instructions Remark 1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the interrupt request assigned the highest priority A...

Page 231: ...ming Example of MOV A r Clock CPU Interrupt MOV A r Saving PSW and PC jump to interrupt servicing 8 clocks Interrupt servicing program If an interrupt request flag IF is set before an instruction clock n n 4 to 10 under execution becomes n 1 the interrupt is acknowledged after the instruction under execution is complete Figure 13 8 shows an example of the interrupt request acknowledgment timing fo...

Page 232: ...f the interrupt request acknowledgment timing for an interrupt request flag that is set at the second clock of NOP 2 clock instruction In this case the MOV A r instruction after the NOP instruction is executed and then the interrupt acknowledgment processing is performed Caution Interrupt requests will be held pending while the interrupt request flag registers 0 1 IF0 IF1 or interrupt mask flag re...

Page 233: ...eased and the interrupt request acknowledgment enable state is set Caution Multiple interrupts can be acknowledged even for low priority interrupts Example 2 Multiple interrupts are not generated because interrupts are not enabled INTyy EI Main processing RETI INTyy servicing INTxx servicing IE 0 INTxx RETI INTyy is held pending IE 0 Because interrupts are not enabled in interrupt INTxx servicing ...

Page 234: ... is given priority since the INTP0 interrupt was first masked Afterwards once the interrupt mask for INTP0 is released INTP0 processing through multiple interrupts is performed IE 0 Interrupt request acknowledgment disabled 13 4 3 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction e...

Page 235: ... LSRSTOP setting is valid only when Can be stopped by software is set for the low speed internal oscillator by the option byte Remark LSRSTOP Bit 0 of the low speed internal oscillation mode register LSRCM The standby function is designed to reduce the operating current of the system The following two modes are available 1 HALT mode HALT instruction execution sets the HALT mode In the HALT mode th...

Page 236: ...7 μs MAX In either of these two modes all the contents of registers flags and data memory just before the standby mode is set are held The I O port output latches and output buffer statuses are also held Cautions 1 When shifting to the STOP mode be sure to stop the peripheral hardware operation before executing STOP instruction except the peripheral hardware that operates on the low speed internal...

Page 237: ...BYTE OSTS is set by using the 8 bit memory manipulation instruction Figure 14 1 Format of Oscillation Stabilization Time Select Register OSTS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 2 10 fX 102 4 μs 0 1 2 12 fX 409 6 μs 1 0 2 15 fX 3 27 ms 1 1 2 17 fX 13 1 ms Cautions 1 To set and then r...

Page 238: ...ion Continues When Low Speed Internal Oscillation Stops System clock Clock supply to CPU is stopped CPU Operation stops Port latch Holds status before HALT mode was set 16 bit timer event counter 00 Operable 8 bit timer 80 Operable Sets count clock to fXP to fXP 2 12 Operable 8 bit timer H1 Sets count clock to fRL 2 7 Operable Operable Operation stops System clock selected as operating clock Setti...

Page 239: ...nt is disabled the next address instruction is executed Figure 14 2 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation System clock oscillation Status of CPU Standby release signal Interrupt request Remarks 1 The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged...

Page 240: ...n is stopped 277 μs MIN 544 μs TYP 1 075 ms MAX because the option byte is referenced 2 When CPU clock is crystal ceramic oscillation clock HALT instruction Reset signal System clock oscillation Operation mode HALT mode Reset period Operation stopsNote Oscillation stabilization waits Oscillates Oscillation stops Oscillates CPU status Oscillation stabilization time 210 fX to 217 fX Operation mode N...

Page 241: ...l Oscillator Can Be Stopped Note Setting of HALT Mode Item Low Speed Internal Oscillator Cannot Be Stopped Note When Low Speed Internal Oscillation Continues When Low Speed Internal Oscillation Stops System clock Oscillation stops CPU Operation stops Port latch Holds status before STOP mode is set 16 bit timer event counter 00 Operation stops 8 bit timer 80 Operation stops Sets count clock to fXP ...

Page 242: ...de is released STOP mode High speed internal oscillation clock or external clock input Operation stopsNote 2 If crystal ceramic oscillation clock is selected as system clock to be supplied System clock oscillation CPU clock STOP mode is released STOP mode HALT status oscillation stabilization time set by OSTS Crystal ceramic oscillation clock Operation stopsNote Note The operation stop time is 17 ...

Page 243: ... high speed internal oscillation clock or external input clock Operation mode Operation mode Oscillation STOP instruction STOP mode Standby release signal System clock oscillation CPU status Oscillation Oscillation stops Operation stopsNote Interrupt request 2 If CPU clock is crystal ceramic oscillation clock Waiting for stabilization of oscillation Oscillation stabilization time set by OSTS HALT ...

Page 244: ...μs MIN 544 μs TYP 1 075 ms MAX because the option byte is referenced 2 If CPU clock is crystal ceramic oscillation clock STOP instruction Reset signal System clock oscillation Operation mode STOP mode Reset period Operation stopsNote Operation mode Oscillation Oscillation stops Oscillation CPU status Oscillation stabilization time 210 fX to 217 fX Oscillation stabilization waits Note Operation is ...

Page 245: ...after referencing the option byte after the option byte is referenced and the clock oscillation stabilization time elapses if crystal ceramic oscillation is selected A reset generated by the watchdog timer source is automatically released after the reset and the CPU starts program execution after referencing the option byte after the option byte is referenced and the clock oscillation stabilizatio...

Page 246: ...egister RESF Internal bus Reset signal of WDT Reset signal of POC Reset signal of LVI Internal reset signal Reset signal to LVIM LVIS register Clear Set Clear Set Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit Remarks 1 LVIM Low voltage detect register 2 LVIS Low voltage detection level select register ...

Page 247: ...f P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU 2 With crystal ceramic oscillation clock Hi Z RESET Port pin P130 Note 2 Port pin except P130 Delay Normal operation in progress Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock Internal ...

Page 248: ...l If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU 2 With crystal ceramic oscillation clock Hi Z Port pin P130 Note 2 Port pin except P130 Normal operation in progress Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock Internal reset sig...

Page 249: ...μs TYP and 1 075 ms MAX 2 Set high level output using software Remark When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU 2 With crystal ceramic oscillation clock Hi Z RESET Port pin except P130 Port pin P130 Note 2 Delay Normal operation in progress CPU clock Nor...

Page 250: ...rs PU0 PU2 PU3 PU4 PU12 00H Processor clock control register PCC 02H Preprocessor clock control register PPCC 02H Low speed internal oscillation mode register LSRCM 00H Oscillation stabilization time select register OSTS Undefined Timer counter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Mode control register 00 TMC00 00H Prescaler mode register 00 PRM00 00H Capture compare c...

Page 251: ...LC0 00H Reset function Reset control flag register RESF 00H Note Low voltage detection register LVIM 00H Note Low voltage detector Low voltage detection level select register LVIS 00H Note Request flag registers IF0 IF1 00H Mask flag registers MK0 MK1 FFH Interrupt External interrupt mode registers INTM0 INTM1 00H Flash protect command register PFCMD Undefined Flash status register PFS 00H Flash p...

Page 252: ... 4 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer WDT 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage detector LVI 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated Note The value after reset varies depending on the res...

Page 253: ...ignal is generated in the POC circuit the reset control flag register RESF is cleared to 00H 2 Because the detection voltage VPOC of the POC circuit is in a range of 2 1 V 0 1 V use a voltage in the range of 2 2 to 5 5 V Remark This product incorporates multiple hardware functions that generate an internal reset signal A flag that indicates the reset cause is located in the reset control flag regi...

Page 254: ... source Internal reset signal VDD VDD 16 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VDD and detection voltage VPOC 2 1 V 0 1 V are compared and an internal reset signal is generated when VDD VPOC and an internal reset is released when VDD VPOC Figure 16 2 Timing of Internal Reset Signal Generation in Power on Clear Circuit Time Supply voltage VDD POC det...

Page 255: ... uses a timer and then initialize the ports Figure 16 3 Example of Software Processing After Release of Reset 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Check reset sourceNote 2 Initialization of ports Setting WDT Source fXP 2 1 MHz MAX 212 51 ms when the compare value is 25 Timer starts TMHE1 1 Note 1 Setting 8 bit timer H1 50 ms is measured Setting th...

Page 256: ... Example of Software Processing After Release of Reset 2 2 Checking reset cause Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector No WDTRF of RESF register 1 LVIRF of RESF register 1 Yes ...

Page 257: ...re Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF refer to CHAPTER 15 RESET FUNCTION 17 2 Configuration of Low Voltage Detector The block diagram of the low voltage detector is shown in Figure 17 1 Figure 17 1 Block Diagram of Low Voltage Detector LVION Reference voltage source...

Page 258: ...MD Low voltage detection operation mode selection 0 Generate interrupt signal when supply voltage VDD detection voltage VLVI 1 Generate internal reset signal when supply voltage VDD detection voltage VLVI LVIF Note 4 Low voltage detection flag 0 Supply voltage VDD detection voltage VLVI or when operation is disabled 1 Supply voltage VDD detection voltage VLVI Notes 1 Retained only after a reset by...

Page 259: ...3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 Detection level 0 0 0 0 VLVI0 4 3 V 0 2 V 0 0 0 1 VLVI1 4 1 V 0 2 V 0 0 1 0 VLVI2 3 9 V 0 2 V 0 0 1 1 VLVI3 3 7 V 0 2 V 0 1 0 0 VLVI4 3 5 V 0 2 V 0 1 0 1 VLVI5 3 3 V 0 15 V 0 1 1 0 VLVI6 3 1 V 0 15 V 0 1 1 1 VLVI7 2 85 V 0 15 V 1 0 0 0 VLVI8 2 6 V 0 1 V 1 0 0 1 VLVI9 2 35 V 0 1 V Other than above Setting prohibited Note Retained only after a reset by LVI...

Page 260: ...LVION of LVIM to 1 enables LVI operation 4 Use software to instigate a wait of at least 0 2 ms 5 Wait until supply voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM is confirmed 6 Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when supply voltage VDD detection voltage VLVI Figure 17 4 shows the timing of generating the internal reset signal of the low voltage detector Numbers ...

Page 261: ... set by software LVION flag set by software LVIMD flag set by software Cleared by software Not cleared Not cleared Not cleared Not cleared Cleared by software Time Clear Clear Clear 4 0 2 ms or longer Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF refer to CHAPTER 15 RESET FUNCT...

Page 262: ... Numbers 1 to 7 in this figure correspond to 1 to 7 above When stopping operation Either of the following procedures must be executed When using 8 bit memory manipulation instruction Write 00H to LVIM When using 1 bit memory manipulation instruction Clear LVION to 0 Figure 17 5 Timing of Low Voltage Detector Interrupt Signal Generation 2 1 Note 1 3 5 Note 2 Note 2 Supply voltage VDD LVI detection ...

Page 263: ...n used as reset After releasing the reset signal wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer and then initialize the ports see Figure 17 6 2 When used as interrupt a Perform the processingNote for low voltage detection Check that supply voltage VDD detection voltage VLVI in the servicing routine of the LVI interrupt by using bit 0 ...

Page 264: ...ports Setting WDT Reset Initialization processing 1 Setting 8 bit timer H1 50 ms is measured Source fXP 2 1 MHz MAX 212 51 ms when the compare value is 25 Timer starts TMHE1 1 Clears WDT 50 ms has passed TMIFH1 1 Initialization processing 2 Setting the division ratio of the system clock timer A D converter etc The low voltage detector is operated LVION 1 The detection level is set with LVIS Clear ...

Page 265: ...Example of Software Processing After Release of Reset 2 2 Checking reset source Yes No Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector WDTRF of RESF register 1 LVIRF of RESF register 1 ...

Page 266: ...clock source High speed internal oscillation clock Crystal ceramic oscillation clock External clock input 2 Low speed internal oscillation clock oscillation Cannot be stopped Can be stopped by software 3 Control of RESET pin Used as RESET pin RESET pin is used as an input port pin P34 refer to 18 3 Caution When the RESET Pin Is Used as an Input Only Port Pin P34 4 Oscillation stabilization time on...

Page 267: ...34 Caution Because the option byte is referenced after reset release if a low level is input to the RESET pin before the option byte is referenced then the reset state is not released Also when setting 0 to RMCE connect the pull up resistor OSCSEL1 OSCSEL0 Selection of system clock source 0 0 Crystal ceramic oscillation clock 0 1 External clock input 1 High speed internal oscillation clock Caution...

Page 268: ...pplied to the 8 bit timer H1 even in the STOP mode Remarks 1 fX 10 MHz 2 For the oscillation stabilization time of the resonator refer to the characteristics of the resonator to be used 3 An example of software coding for setting the option bytes is shown below OPB OSEG AT 0080H DB 10010001B Set to option byte Low speed internal oscillator cannot be stopped The system clock is a crystal or ceramic...

Page 269: ...s Write unit 1 block at on board off board programming time 1 byte at self programming time Rewriting method Rewriting by communication with dedicated flash memory programmer on board off board programming Rewriting flash memory by user program self programming Supports rewriting of the flash memory at on board off board programming time through security functions Supports security functions in bl...

Page 270: ... Internal high speed RAM 256 bytes Use prohibited Flash memory 4 8 KB FFFFH FF00H FEFFH FE00H FDFFH 0000H 0000H 0100H 00FFH Block 0 256 bytes Block 1 256 bytes Block 2 256 bytes Block 13 256 bytes Block 14 256 bytes Block 15 256 bytes Block 0 256 bytes Block 1 256 bytes Block 2 256 bytes Block 13 256 bytes Block 14 256 bytes Block 15 256 bytes Block 29 256 bytes Block 30 256 bytes Block 31 256 byt...

Page 271: ...nauthorized person Refer to 19 7 3 Security settings for details on the security function Table 19 1 Rewrite Method Rewrite Method Functional Outline Operation Mode On board programming Flash memory can be rewritten after the device is mounted on the target system by using a dedicated flash memory programmer Off board programming Flash memory can be rewritten before the device is mounted on the ta...

Page 272: ...ontents of the flash memory can be rewritten after the 78K0S KB1 has been mounted on the target system The connectors that connect the dedicated flash memory programmer and the test pad must be mounted on the target system The test pad is required only when writing data with the crystal ceramic resonator mounted refer to Figure 19 6 for mounting of the test pad 2 Off board programming Data can be ...

Page 273: ...tten with just the dedicated flash memory programmer after downloading the program from the host machine UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash memory programmer and the 78K0S KB1 To write the flash memory off board a dedicated program adapter FA series is necessary Download the latest programmer firmware GUI and parameter file from t...

Page 274: ...S KB1 and PG FPL2 PG FPL2 Connection Pin 78K0S KB1 Connection Pin Pin Name I O Pin Function Pin Name Pin No CLK Output Clock to 78K0S KB1 X1 P121 8 DGDATA I O Transmit receive signal on board mode signal X2 P122 9 RESET Output Reset signal RESET P34 10 VDD VDD voltage generation VDD 7 GND Ground VSS 6 Figure 19 5 Communication with PG FPL2 DGCLK DGDATA RESET VDD GND PG FPL2 signal name 78K0S KB1 1...

Page 275: ...munication is changed and thus communication may be disabled depending on the capacitor capacitance Make sure to isolate the connection with the capacitor during flash programming Perform the following processing 1 and 2 when on board writing is performed with the resonator mounted when it is difficult to isolate the resonator while a crystal or ceramic resonator is selected as the system clock 1 ...

Page 276: ... environment these values may change so set them after having performed sufficient evaluations 19 6 2 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board signal collision takes place To prevent this collision isolate the connection with the reset signal generator If the reset signal is inp...

Page 277: ... 6 3 Port pins When the flash memory programming mode is set all the pins not used for flash memory programming enter the same status as that immediately after reset If external devices connected to the ports do not recognize the port status immediately after reset the port pin must be connected to VDD or VSS via a resistor The state of the pins in the self programming mode is the same as that in ...

Page 278: ...Y STATVE FlashPro4 Dedicated flash memory programmer Power Status MODE Target 3V Target PG FPL2 PG FPL2 Communication Command Response Communication commands are listed in the table below All these communication commands are issued from the flash memory programmer and the 78K0S KB1 performs processing corresponding to the respective communication commands Table 19 6 Communication Commands Classifi...

Page 279: ...he batch erase chip erase command Write is prohibited Execution of the write and block erase commands for entire blocks in the flash memory is prohibited This prohibition setting can be cancelled using the batch erase chip erase command Remark The security setting is valid when the programming mode is set next time The batch erase chip erase block erase and write commands are enabled by the defaul...

Page 280: ...use the internal flash memory of the 78K0S KB1 as the external EEPROM for storing data refer to 78K0S Kx1 EEPROM Emulation Application Note U17379E 19 8 1 Outline of self programming To execute self programming shift the mode from the normal operation of the user program normal mode to the self programming mode Write erase processing for the flash memory which has been set to the register in advan...

Page 281: ...Erase circuit WEPRERR VCERR FPRERR HALT release signal FLCMD2 FLCMD1 FLCMD0 Internal bus Flash programming command register FLCMD Increment circuit Flash memory Protect byte PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 5 Flash address pointer H FLAPH Flash address pointer L FLAPL Flash address pointer H compare register FLAPHC Matched Matched Flash address pointer L compare register FLAPLC Flash write ...

Page 282: ...entire block Internal verify for 1 block internal verify command executed once 6 8 ms Internal verify 2 This command is used to check if data has been correctly written to the flash memory It is used to check whether data has been written to multiple addresses in the same block Internal verify of 1 byte 27 μs Block erasure This command is used to erase a specified block Specify the block number be...

Page 283: ...ted as the system clock execute the NOP and HALT instructions immediately after executing a specific sequence to set self programming mode wait for 8 μs after releasing the HALT status and then execute self programming Check FPRERR using a 1 bit memory manipulation instruction The state of the pins in self programming mode is the same as that in HALT mode Since the security function set via on boa...

Page 284: ...ange modes while in normal mode Set a command an address and data to be written then execute the HALT instruction to execute self programming PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 The set value of the protect byte is read to these bits Notes 1 Bit 0 FLSPM is cleared to 0 when reset is released The set value of the protect byte is read to bits 2 to 6 PRSELF0 to PRSELF4 after reset is released 2 B...

Page 285: ...the value of the register so that the register cannot be written illegally Occurrence of an illegal write operation can be checked by bit 0 FPRERR of the flash status register PFS A5H must be written to PFCMD each time the value of FLPMC is changed Check FPRERR using a 1 bit memory manipulation instruction PFCMD can be set with an 8 bit memory manipulation instruction Reset signal generation makes...

Page 286: ... is written by the first store instruction after 3 Remark The numbers in angle brackets above correspond to the those in 2 Flash protect command register PFCMD Reset conditions If 0 is written to the FPRERR flag If the reset signal is generated 2 Operating conditions of VCERR flag Setting conditions Erasure verification error Internal writing verification error If VCERR is set it means that the fl...

Page 287: ... 2 This command is used to check if data has been correctly written to the flash memory It is used to check whether data has been written to multiple addresses in the same block If an error occurs bit 1 VCERR or bit 2 WEPRERR of the flash status register PFS is set to 1 0 1 1 Block erase This command is used to erase specified block It is used both in the on board mode and self programming mode 1 ...

Page 288: ... 1 the device may malfunction 6 Flash address pointer H compare register and flash address pointer L compare register FLAPHC and FLAPLC These registers are used to specify the address range in which the internal sequencer operates when the flash memory is verified in the self programming mode Set FLAPHC to the same value as that of FLAPH Set the last address of the range in which verification is t...

Page 289: ...ritten to the protected area is guaranteed Figure 19 19 Format of Protect Byte 1 2 Address 0081H 7 6 5 4 3 2 1 0 1 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 1 1 μPD78F9232 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 Status 0 1 0 0 0 Blocks 15 to 0 are protected 0 1 0 0 1 Blocks 13 to 0 are protected Blocks 14 and 15 can be written or erased 0 1 0 1 0 Blocks 11 to 0 are protected Blocks 12 to 15 can be w...

Page 290: ... Blocks 20 to 31 can be written or erased 0 0 1 1 1 Blocks 17 to 0 are protected Blocks 18 to 31 can be written or erased 0 1 0 0 0 Blocks 15 to 0 are protected Blocks 16 to 31 can be written or erased 0 1 0 0 1 Blocks 13 to 0 are protected Blocks 14 to 31 can be written or erased 0 1 0 1 0 Blocks 11 to 0 are protected Blocks 12 to 31 can be written or erased 0 1 0 1 1 Blocks 9 to 0 are protected ...

Page 291: ...flash status register PFS 4 Set self programming mode using a specific sequenceNote Write a specific value A5H to PFCMD Write 01H to FLPMC writing in this step is invalid Write 0FEH inverted value of 01H to FLPMC writing in this step is invalid Write 01H to FLPMC writing in this step is valid 5 Execute NOP instruction and HALT instruction 6 Check the execution result of the specific sequence using...

Page 292: ...sed If the CPU clock is lower than 1 MHz set it to be 1 MHz or higher 3 Clear PFS 2 Clear FLCMD FLCMD 00H 7 Termination FLPMC 01H set value FLPMC 0FEH inverted set value FLPMC 01H set value NOP instruction HALT instruction Set value is invalid Set value is valid 4 5 instruction Caution Be sure to perform the series of operations described above using the user program at an address where data is no...

Page 293: ...op Configure settings so that the CPU clock 1 MHz MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC 0FEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode with FLPMC register control sets value NOP HALT BT PFS O ModeOnLoop Checks completion of write to specific registers Repeats t...

Page 294: ...ting in this step is invalid Write 0FFH inverted value of 00H to FLPMC writing in this step is invalid Write 00H to FLPMC writing in this step is valid 4 Check the execution result of the specific sequence using bit 0 FPRERR of PFSNote Abnormal 2 normal 5 5 Enable interrupt servicing by executing the EI instruction and changing MK0 and MK1 to restore the original state 6 Mode shift is completed No...

Page 295: ...FFH inverted set value FLPMC 00H set value Set value is invalid Set value is valid 5 Enable interrupts by executing EI instruction and changing MK0 When interrupt function is used 3 Restore the CPU clock to its setting before the self programming Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased nor written Remark 1 to...

Page 296: ...PMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs Restore the CPU clock to its setting before the self programming after normal completion of the specific sequence ...

Page 297: ...ter FLAPHC 5 Set the flash address pointer L compare register FLAPLC to 00H 6 Clear the flash status register PFS 7 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 8 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed 9 Check if a self prog...

Page 298: ...CERR and WEPRERR flags 8 Execute HALT instruction Normal 6 Clear PFS 1 Set erase command FLCMD 03H 2 Set no of block to be erased to FLAPH Block erasure 4 Set the same value as that of FLAPH to FLAPHC 10 Abnormal termination Abnormal 3 Set FLAPL to 00H 5 Set FLAPLC to 00H Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 19 22 correspond to 1 to 11 in 1...

Page 299: ...s number of block to be erased block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAPLC 00H Fixes FLAPLC to 00H MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 normal terminat...

Page 300: ...ess pointer H compare register FLAPHC 5 Set the flash address pointer L compare register FLAPLC to FFH 6 Clear the flash status register PFS 7 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 8 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been exec...

Page 301: ...d WEPRERR flags 8 Execute HALT instruction Normal Abnormal 6 Clear PFS 1 Set block blank check command FLCMD 04H 2 Set no of block for blank check to FLAPH Block blank check 10 Abnormal termination 5 Set FLAPLC to 00H 4 Set the same value as that of FLAPH to FLAPHC 3 Set FLAPL to 00H Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 19 23 correspond to ...

Page 302: ... Sets number of block for blank check block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets blank check block compare number same value as that of FLAPH MOV FLAPLC 0FFH Fixes FLAPLC to FFH MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 n...

Page 303: ...ite buffer register FLW 5 Clear the flash status register PFS 6 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 7 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed 8 Check if a self programming error has occurred using bit 1 VCERR and bit...

Page 304: ...ERR and WEPRERR flags 7 Execute HALT instruction Normal Abnormal 5 Clear PFS 1 Set byte write command FLCMD 05H Byte write 9 Abnormal termination 4 Set data to be written to FLW 2 Set no of block to be written to FLAPH 3 Set address at which data is to be written to FLAPL Note This setting is not required when the watchdog timer is not used Remark 1 to 10 in Figure 19 24 correspond to 1 to 10 in 1...

Page 305: ...ta is to be written with FLAPH block 7 is specified here MOV FLAPL 20H Sets address to which data is to be written with FLAPL address 20H is specified here MOV FLW 10H Sets data to be written 10H is specified here MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 n...

Page 306: ...d bit 2 WEPRERR of PFS Abnormal 10 Normal 11 10 Internal verify processing is terminated abnormally 11 Internal verify processing is terminated normally Internal verify 2 1 Set 02H internal verify 2 to the flash program command register FLCMD 2 Set the block number for which internal verify is performed to flash address pointer H FLAPH 3 Set the verify start address to the flash address pointer L ...

Page 307: ...ags 8 Execute HALT instruction Normal Abnormal 6 Clear PFS 1 Set internal verify 1 command FLCMD 01H Internal verify 1 10 Abnormal termination 2 Set block no for internal verify to FLAPH 4 Set the same value as that of FLAPH to FLAPHC 5 Set FFH to FLAPLC 3 Set 00H to FLAPL Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 19 25 correspond to 1 to 11 of ...

Page 308: ...T instruction Normal Abnormal 6 Clear PFS 1 Set internal verify 2 command FLCMD 02H Internal verify 2 10 Abnormal termination 2 Set block no for internal verify to FLAPH 4 Set the same value as that of FLAPH to FLAPHC 5 Sets FLAPLC to the end address 3 Sets FLAPL to the start address Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 19 26 correspond to ...

Page 309: ...tion result is stored in variable CmdStatus 0 normal termination other than 0 abnormal termination END Internal verify 2 START FlashVerify MOV FLCMD 02H Sets flash control command internal verify 2 MOV FLAPH 07H Sets block number for which internal verify is performed to FLAPH Example Block 7 is specified here MOV FLAPL 00H Sets FLAPL to the start address for verify Example Address 00H is specifie...

Page 310: ...ted from self programming mode to normal mode 1 to 6 in 19 8 5 Figure 19 27 Example of Operation When Command Execution Time Should Be Minimized from Erasure to Blank Check 4 Shift to normal mode Abnormal 1 Shift to self programming mode Erasure to blank check Abnormal terminationNote 2 Execute block erase 3 Execute block blank check 2 Check execution result VCERR and WEPRERR flags 3 Check executi...

Page 311: ...ol sets value NOP HALT BT PFS 0 ModeOnLoop Checks completion of write to specific registers Repeats the same processing when an error occurs FlashBlockErase MOV FLCMD 03H Sets flash control command block erase MOV FLAPH 07H Sets number of block to be erased block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAP...

Page 312: ...r control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs Restore the CPU clock to its setting before the self programming after normal completion of the sp...

Page 313: ...mand Execution Time Should Be Minimized from Write to Internal Verify 6 Shift to normal mode Abnormal 1 Shift to self programming mode Write to internal verify 3 Execute byte write command 5 Execute internal verify 2 command 3 Check execution result VCERR and WEPRERR flags 5 Check execution result VCERR and WEPRERR flags Normal termination Normal Abnormal Normal Figure 19 24 1 to 10 Figure 19 25 1...

Page 314: ...Loop Checks completion of write to specific registers Repeats the same processing when an error occurs FlashWrite MOVW HL DataAdrTop Sets address at which data to be written is located MOVW DE WriteAdr Sets address at which data is to be written FlashWriteLoop MOV FLCMD 05H Sets flash control command byte write MOV A D MOV FLAPH A Sets address at which data is to be written MOV A E MOV FLAPL A Set...

Page 315: ...ion processing when an error occurs MOV FLCMD 00H Clears FLCMD register ModeOffLoop MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific regi...

Page 316: ...1UD 316 StatusError END normal termination processing StatusNormal Data to be written DataAdrTop DB XXH DB XXH DB XXH DB XXH DB XXH DataAdrBtm Remark Internal verify 2 is used in the above program example Use internal verify 1 to verify a whole block ...

Page 317: ...ase command 1 to 5 in 19 8 6 2 Mode is shifted from normal mode to self programming mode 1 to 7 in 19 8 4 3 Execution of block erase command Error check 6 to 11 in 19 8 6 4 Mode is shifted from self programming mode to normal mode 1 to 6 in 19 8 5 5 Specification of block blank check command 1 to 5 in 19 8 7 6 Mode is shifted from normal mode to self programming mode 1 to 7 in 19 8 4 7 Execution o...

Page 318: ...o self programming mode Figure 19 20 1 to 7 3 Execute block erase command Figure 19 22 6 to 11 4 Shift to normal mode Figure 19 21 1 to 6 5 Specify block blank check command 7 Check execution result VCERR and WEPRERR flags Figure 19 23 1 to 5 6 Shift to self programming mode Figure 19 20 1 to 7 7 Execute block blank check command Figure 19 23 6 to 11 8 Shift to normal mode Figure 19 21 1 to 6 Norm...

Page 319: ...WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks erase error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode Sets blank check command MOV FLCMD 04H Sets flash control command block blank check MOV FLAPH 07H Sets block number for blank check block 7 is specified here MOV FLAPL 00H Fixes FLAPL to...

Page 320: ...1111111B Masks all interrupts MOV MK1 11111111B MOV FLCMD 00H Clears FLCMD register DI ModeOnLoop Configure settings so that the CPU clock 1 MHz MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC 0FEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode via FLPMC register control sets...

Page 321: ...control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value BT PFS 0 ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs Restore the CPU clock to its setting before the self programming after normal completion of the specific sequence MOV MK0 INT_MK0 Restore...

Page 322: ...tion of byte write command Error check 5 to 10 in 19 8 8 5 Mode is shifted from self programming mode to normal mode 1 to 6 in 19 8 5 6 2 to 5 is repeated until all data are written 7 The internal verify command is specified 1 to 5 in 19 8 9 8 Mode is shifted from normal mode to self programming mode 1 to 7 in 19 8 4 9 Execution of internal verify command Error check 6 to 11 in 19 8 9 10 Mode is s...

Page 323: ...cute byte write command Figure 19 24 5 to 10 5 Shift to normal mode Figure 19 21 1 to 6 7 Specify internal verify command 9 Check execution result VCERR and WEPRERR flags Figure 19 25 1 to 5 8 Shift to self programming mode Figure 19 20 1 to 7 9 Execute internal verify command Figure 19 25 6 to 11 10 Shift to normal mode Figure 19 21 1 to 6 Normal 1 Set source data for write Write to internal veri...

Page 324: ... at which data is to be written MOV A HL MOV FLW A Sets data to be written CALL ModeOn Shift to self programming mode Execution of write command MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks write error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal m...

Page 325: ...erify end address CALL ModeOn Shift to self programming mode Execution of internal verify command MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks internal verify error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode BR StatusNormal END abnormal term...

Page 326: ...p Checks completion of write to specific registers Repeats the same processing when an error occurs RET Processing to shift to normal mode ModeOffLoop MOV FLCMD 00H Clears FLCMD register MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode...

Page 327: ...MORY User s Manual U17446EJ3V1UD 327 Data to be written DataAdrTop DB XXH DB XXH DB XXH DB XXH DB XXH DataAdrBtm Remark Internal verify 2 is used in the above program example Use internal verify 1 to verify a whole block ...

Page 328: ...irect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 20 1 Operand Identifiers and Description Methods Identifier...

Page 329: ...k pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displacem...

Page 330: ...sfr sfr A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte MOV HL byte A 2 6 HL byte A A X 1 4 A X A r Note 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL XCH A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One instru...

Page 331: ...addr16 A HL 1 6 A CY A HL ADD A HL byte 2 6 A CY A HL byte A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY A HL 1 6 A CY A HL CY ADDC A HL byte 2 6 A CY A HL byte CY A byte 2 4 A CY A byte saddr byte 3 6 saddr CY saddr byte A r 2 4 A CY A r A saddr 2 4 A CY A saddr A addr16 3 8 A CY A addr16 A HL 1 6 A CY...

Page 332: ... 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL AND A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL OR A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL ...

Page 333: ... DEC saddr 2 4 saddr saddr 1 INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 ROL A 1 1 2 CY A0 A7 Am 1 Am 1 RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 saddr bit 3 6 saddr bit 1 sfr bit 3 6 sfr bit 1 A bit 2 4 A bit 1 PSW bit 3 6 PSW bit 1 SET1 HL bit 2 10 HL bit 1 saddr bit 3 6 saddr bit 0 sfr bit 3 6 sfr bit 0 A bit 2 4 A bit 0 PSW bit 3 6 PSW bit...

Page 334: ... saddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 BT PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8 i...

Page 335: ...HL byte addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC D...

Page 336: ...rp Note saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 337: ...3V1UD 337 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 338: ...23 44 0 mA Per pin 20 0 mA Total of pins other than P20 to P23 44 0 mA Output current low IOL Total of P20 to P23 44 0 mA In normal operation mode Operating ambient temperature TA During flash memory programming 40 to 85 C Flash memory blank status 65 to 150 C Storage temperature Tstg Flash memory programming already performed 40 to 125 C Note Must be 6 5 V or lower Caution Product quality may suf...

Page 339: ...etection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the...

Page 340: ...ency fX Note 2 2 0 V VDD 2 7 V 5 5 MHz Notes 1 Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Low Speed Internal Oscillator Characteristics TA 40 to 85 C VDD 2 0 to 5 5 V Note VSS 0 V Resonator Parameter Cond...

Page 341: ... P122 0 0 2VDD V Total of pins other than P20 to P23 IOH1 15 mA 4 0 V VDD 5 5 V IOH1 5 mA VDD 1 0 V VOH1 IOH1 100 μA 2 0 V VDD 4 0 V VDD 0 5 V Total of pins P20 to P23 IOH2 10 mA 4 0 V AVREF 5 5 V IOH2 5 mA AVREF 1 0 V Output voltage high VOH2 2 0 V AVREF 4 0 V IOH2 100 μA AVREF 0 5 V Total of pins other than P20 to P23 IOL1 30 mA 4 0 V VDD 5 5 V IOL1 10 mA 1 3 V VOL1 IOL1 400 μA 2 0 V VDD 4 0 V 0...

Page 342: ...h speed internal oscillation operating mode Note7 fX 8 MHz VDD 5 0 V 10 Note 4 When A D converter is operating Note 8 6 5 13 0 mA When peripheral functions are stopped 1 4 3 2 IDD4 High speed internal oscillation HALT mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When peripheral functions are operating 5 9 mA When low speed internal oscillation is stopped 3 5 20 0 VDD 5 0 V 10 When low speed internal o...

Page 343: ...RSL 2 μs Notes 1 Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V 2 Selection of fsam fXP fXP 4 or fXP 256 is possible using bits 0 and 1 PRM000 PRM001 of prescaler mode register 00 PRM00 Note that when selecting the valid edge of the TI000 pin as the count clock fsam fXP CPU Clock Frequency Peripheral Clock Fre...

Page 344: ... TCY vs VDD Crystal Ceramic Oscillation Clock External Clock Input Supply voltage VDD V 1 2 3 4 5 6 0 1 0 4 1 0 10 60 Cycle time T CY s Guaranteed operation range 0 33 2 7 5 5 μ 16 TCY vs VDD High speed internal oscillator Clock 1 2 3 4 5 6 0 1 1 0 10 60 2 7 5 5 0 23 4 22 0 47 0 95 Supply voltage VDD V Cycle time T CY s Guaranteed operation range μ ...

Page 345: ...enerator output Parameter Symbol Conditions MIN TYP MAX Unit Transfer rate 312 5 kbps Note Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V AC Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD 0 8VDD 0 2VDD Test points Clock Timing 1 fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing INTP0...

Page 346: ... tCONV 2 7 V AVREF 2 85 V 14 0 100 μs 4 0 V AVREF 5 5 V 0 4 FSR Zero scale error Notes 1 2 Ezs 2 7 V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 0 4 FSR Full scale error Notes 1 2 Efs 2 7 V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 2 5 LSB Integral non linearity error Note 1 ILE 2 7 V AVREF 4 0 V 4 5 LSB 4 0 V AVREF 5 5 V 1 5 LSB Differential non linearity error Note 1 DLE 2 7 V AVREF 4 0 V 2 0 LSB Analog i...

Page 347: ...tPTH VDD 0 V 2 1 V 1 5 μs Response delay time 1 Note 1 tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note 2 tPD When power supply falls 1 0 ms Minimum pulse width tPW 0 2 ms Notes 1 Time required from voltage detection to internal reset release 2 Time required from voltage detection to internal reset signal generation POC Circuit Timing Supply volt...

Page 348: ...ms Minimum pulse width tLW 0 2 ms Operation stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset signal generation 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 2 VPOC VLVIm m 0 to 9 LVI Circuit Timing Supply voltage VDD Detection...

Page 349: ...E 1000 2 7 V VDD 3 5 V 12 3 s 4 5 V VDD 5 5 V 0 4 s 3 5 V VDD 4 5 V 0 5 s TA 10 to 85 C NERASE 100 2 7 V VDD 3 5 V 0 6 s 4 5 V VDD 5 5 V 2 6 s 3 5 V VDD 4 5 V 2 8 s TA 10 to 85 C NERASE 1000 2 7 V VDD 3 5 V 2 3 s 4 5 V VDD 5 5 V 0 9 s 3 5 V VDD 4 5 V 1 0 s TA 40 to 85 C NERASE 100 2 7 V VDD 3 5 V 1 1 s 4 5 V VDD 5 5 V 4 9 s 3 5 V VDD 4 5 V 5 4 s Block erase time TBERASE TA 40 to 85 C NERASE 1000 2...

Page 350: ...tal of P20 to P23 30 0 mA Per pin 14 0 mA Total of pins other than P20 to P23 30 0 mA Output current low IOL Total of P20 to P23 30 0 mA TA 40 to 85 C 120 mW Total loss PT Note 2 TA 85 to 125 C 110 mW In normal operation mode 40 to 125 C Operating ambient temperature TA During flash memory programming 40 to 105 C Flash memory blank status 65 to 150 C Storage temperature Tstg Flash memory programmi...

Page 351: ...20 125 110 Use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss PT use at 80 or less of the rated value is recommended Total power consumption VDD IDD IOH VDD VOH IOH VOL IOL When guaranteeing the internal pull up resistor use the following formula to calculate its power consumption and add the result to the re...

Page 352: ...voltage VPOC of the power on clear POC circuit is 2 26 V MAX 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring wi...

Page 353: ...Note 2 2 0 V VDD 2 7 V 5 5 MHz Notes 1 Use this product in a voltage range of 2 26 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 26 V MAX 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Low Speed Internal Oscillator Characteristics TA 40 to 125 C VDD 2 0 to 5 5 V Note VSS 0 V Resonator Parameter Conditions ...

Page 354: ...121 P122 0 0 2VDD V Total of pins other than P20 to P23 IOH1 10 5 mA 4 0 V VDD 5 5 V IOH1 3 5 mA VDD 1 0 V VOH1 IOH1 100 μA 2 0 V VDD 4 0 V VDD 0 5 V Total of pins P20 to P23 IOH2 7 mA 4 0 V AVREF 5 5 V IOH2 3 5 mA AVREF 1 0 V Output voltage high VOH2 2 0 V AVREF 4 0 V IOH2 100 μA AVREF 0 5 V Total of pins other than P20 to P23 IOL1 21 mA 4 0 V VDD 5 5 V IOL1 7 mA 1 3 V VOL1 2 0 V VDD 4 0 V IOL1 4...

Page 355: ...eed internal oscillation operating mode Note7 fX 8 MHz VDD 5 0 V 10 Note 4 When A D converter is operating Note 8 6 5 15 2 mA When peripheral functions are stopped 1 4 4 4 IDD4 High speed internal oscillation HALT mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When peripheral functions are operating 7 1 mA When low speed internal oscillation is stopped 3 5 1200 VDD 5 0 V 10 When low speed internal oscil...

Page 356: ... Notes 1 Use this product in a voltage range of 2 26 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 26 V MAX 2 Selection of fsam fXP fXP 4 or fXP 256 is possible using bits 0 and 1 PRM000 PRM001 of prescaler mode register 00 PRM00 Note that when selecting the valid edge of the TI000 pin as the count clock fsam fXP CPU Clock Frequency Peripheral Clock Frequency P...

Page 357: ... Crystal Ceramic Oscillation Clock External Clock Input Supply voltage VDD V 1 2 3 4 5 6 0 1 0 4 1 0 10 60 Cycle time T CY s Guaranteed operation range 0 33 2 7 5 5 μ 16 0 25 TCY vs VDD High speed internal oscillator Clock 1 2 3 4 5 6 0 1 1 0 10 60 2 7 5 5 0 23 4 22 0 47 0 95 Supply voltage VDD V Cycle time T CY s Guaranteed operation range μ ...

Page 358: ... output Parameter Symbol Conditions MIN TYP MAX Unit Transfer rate 312 5 kbps Note Use this product in a voltage range of 2 26 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 26 V MAX AC Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD 0 8VDD 0 2VDD Test points Clock Timing 1 fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing INTP0 to INTP...

Page 359: ...7 V AVREF 2 85 V 14 0 30 μs 4 0 V AVREF 5 5 V 0 7 FSR Zero scale error Notes 1 2 Ezs 2 7 V AVREF 4 0 V 0 9 FSR 4 0 V AVREF 5 5 V 0 7 FSR Full scale error Notes 1 2 Efs 2 7 V AVREF 4 0 V 0 9 FSR 4 0 V AVREF 5 5 V 5 5 LSB Integral non linearity error Note 1 ILE 2 7 V AVREF 4 0 V 7 5 LSB 4 0 V AVREF 5 5 V 2 5 LSB Differential non linearity error Note 1 DLE 2 7 V AVREF 4 0 V 3 0 LSB Analog input volta...

Page 360: ...D 0 V 2 1 V 1 5 μs Response delay time 1 Note 1 tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note 2 tPD When power supply falls 1 0 ms Minimum pulse width tPW 0 2 ms Notes 1 Time required from voltage detection to internal reset release 2 Time required from voltage detection to internal reset signal generation POC Circuit Timing Supply voltage VDD...

Page 361: ...Minimum pulse width tLW 0 2 ms Operation stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset signal generation 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 2 VPOC VLVIm m 0 to 9 LVI Circuit Timing Supply voltage VDD Detection vo...

Page 362: ... 4 s 3 5 V VDD 4 5 V 0 5 s TA 10 to 105 C NERASE 100 2 7 V VDD 3 5 V 0 6 s 4 5 V VDD 5 5 V 2 6 s 3 5 V VDD 4 5 V 2 8 s TA 10 to 105 C NERASE 1000 2 7 V VDD 3 5 V 3 3 s 4 5 V VDD 5 5 V 0 9 s 3 5 V VDD 4 5 V 1 0 s TA 40 to 105 C NERASE 100 2 7 V VDD 3 5 V 1 1 s 4 5 V VDD 5 5 V 4 9 s 3 5 V VDD 4 5 V 5 4 s Block erase time TBERASE TA 40 to 105 C NERASE 1000 2 7 V VDD 3 5 V 6 6 s Byte write time TWRITE...

Page 363: ...the power consumption of the device is less than or equal to the total loss PT use at 80 or less of the rated value is recommended Total power consumption VDD IDD IOH VDD VOH IOH VOL IOL When guaranteeing the internal pull up resistor use the following formula to calculate its power consumption and add the result to the result above Power consumption of internal pull up resistor Σ VDD RPU VDD Rema...

Page 364: ...62 mm 300 A K D E F G H J P 30 16 1 1 5 A detail of lead end M M T MILLIMETERS 0 65 T P 0 45 MAX 0 13 0 5 6 1 0 2 0 10 9 85 0 15 0 17 0 03 0 1 0 05 0 24 1 3 0 1 8 1 0 2 1 2 0 08 0 07 1 0 0 2 3 5 3 0 25 0 6 0 15 U NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition S30MC 65 5A4 2 ...

Page 365: ...nditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count 3 times or less Exposure limit 7 days Note 2 after that prebake at 125 C for 20 to 72 hours IR35 207 3 VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher Count 3 times or less Exposure limit 7 days Note 2 after that prebake at 125 C for 20 to 72 h...

Page 366: ...tion Symbol Infrared reflow Package peak temperature 260 C Time 30 seconds max at 210 C or higher Count 3 times or less Exposure limit 7 days Note 2 after that prebake at 125 C for 20 to 72 hours IR60 207 3 Wave soldering For details contact an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Notes 1 Under development 2 After opening the...

Page 367: ...mpatibility with PC98 NX series Unless stated otherwise products which are supported by IBM PC ATTM and compatibles can also be used with the PC98 NX series When using the PC98 NX series therefore refer to the explanations for IBM PC AT and compatibles WindowsTM Unless stated otherwise Windows refers to the following operating systems Windows 98 Windows NTTM Ver 4 0 Windows 2000 Windows XP ...

Page 368: ...or emulation probe Pin header or conversion socket Target system Flash memory programmer Flash memory writing adapter Flash memory Power supply unit Software package Control software Project Manager Windows version only Note 2 Software package Flash memory writing environment Notes 1 The C library source file is not included in the software package 2 The Project Manager PM is included in the assem...

Page 369: ...emory writing environment In circuit emulatorNote 3 QB 78K0SMINI Assembler package C compiler package Device file C library source fileNote 1 Integrated debugger System simulator Software package Project Manager Windows version only Note 2 Notes 1 The C library source file is not included in the software package 2 The Project Manager PM is included in the assembler package PM is used only in the W...

Page 370: ...parately Caution when used in PC environment The assembler package is a DOS based application but may be used under the Windows environment by using PM included in the assembler package RA78K0S Assembler package Part number μS RA78K0S Program that converts program written in C language into object codes that can be executed by microcontroller Used in combination with assembler package RA78K0S and ...

Page 371: ...h Windows 3P17 HP9000 series 700 TM HP UX TM Rel 10 10 3K17 SPARCstation TM SunOS TM Rel 4 1 4 Solaris TM Rel 2 5 1 CD ROM μS DF789234 Host Machine OS Supply Media AB13 Japanese Windows BB13 PC 9800 series IBM PC AT and compatibles English Windows 3 5 2HD FD A 3 Control Software PM Project manager This control software is designed so that the user program can be efficiently developed in the Window...

Page 372: ...programmer Remark FL PR4 FA 30MC 5A4 A and FA 78F9234MC 5A4 MX are products of Naito Densei Machida Mfg Co Ltd For further information contact Naito Densei Machida Mfg Co Ltd TEL 81 42 750 4172 A 5 Debugging Tools Hardware A 5 1 When using in circuit emulator QB 78K0SKX1 under development QB 78K0SKX1 under development In circuit emulator This in circuit emulator serves to debug hardware and softwa...

Page 373: ...is adapter is required when using a personal computer incorporating the PCI bus is used as the host machine IE 789234 NS EM1 Emulation board This emulation board serves to emulate peripheral hardware inherent to the device It is used in combination with an in circuit emulator A target cable is provided NP 30MC Emulation probe This probe is used to connect the in circuit emulator to the target syst...

Page 374: ...le This is a system simulator for the 78K 0S series SM for 78K0S is a Windows based software This simulator can execute C source level or assembler level debugging while simulating the operations of the target system on the host machine By using SM for 78K0S the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can b...

Page 375: ...f parts to be mounted on the target system when designing a system Figure B 1 Distance Between In Circuit Emulator IE 78K0S NS IE 78K0S NS A and Conversion Connector NP 30MC In circuit emulator IE 78K0S NS IE 78K0S NS A Emulation board IE 789234 NS EM1 Target system CN5 Emulation probe NP 30MC Conversion connector YSPACK30BK NSPACK30BK NP 30MC tip board 150 mm Remarks 1 The NP 30MC is a product ma...

Page 376: ...K0S NS IE 78K0S NS A 31 mm 37 mm Target system Emulation probe NP 30MC 13 mm Emulation board IE 789234 NS EM1 15 mm 20 mm 5 mm NP 30MC tip board Conversion connector YSPACK30BK NSPACK30BK Guide pin YQ GUIDE Remarks 1 The NP 30MC is a product made by Naito Densei Machida Mfg Co Ltd 2 The YSPACK30BK and NSPACK30BK are products by Naito Densei Machida Mfg Co Ltd ...

Page 377: ...on result storage register L MUL0L 217 A A D converter mode register ADM 165 Analog input channel specification register ADS 167 Asynchronous serial interface control register 6 ASICL6 192 Asynchronous serial interface operation mode register 6 ASIM6 186 Asynchronous serial interface reception error status register 6 ASIS6 188 Asynchronous serial interface transmission status register 6 ASIF6 189 ...

Page 378: ...Oscillation stabilization time select register OSTS 74 237 P Port mode control register 2 PMC2 66 168 Port mode register 0 PM0 64 Port mode register 2 PM2 64 168 Port mode register 3 PM3 64 95 Port mode register 4 PM4 64 138 194 Port mode register 12 PM12 64 Port register 0 P0 65 Port register 2 P2 65 Port register 3 P3 65 Port register 4 P4 65 Port register 12 P12 65 Port register 13 P13 65 Prepr...

Page 379: ...EX User s Manual U17446EJ3V1UD 379 Reset control flag register RESF 252 T Transmit buffer register 6 TXB6 185 Transmit shift register 6 TXS6 185 W Watchdog timer enable register WDTE 152 Watchdog timer mode register WDTM 151 ...

Page 380: ...bit timer H compare register 11 135 CR000 16 bit timer capture compare register 000 87 CR010 16 bit timer capture compare register 010 89 CR80 8 bit compare register 80 128 CRC00 Capture compare control register 00 92 F FLAPH Flash address pointer H 288 FLAPHC Flash address pointer H compare register 288 FLAPL Flash address pointer L 288 FLAPLC Flash address pointer L compare register 288 FLCMD Fl...

Page 381: ...tatus register 285 PM0 Port mode register 0 64 PM2 Port mode register 2 64 168 PM3 Port mode register 3 64 95 PM4 Port mode register 4 64 138 194 PM12 Port mode register 12 64 PMC2 Port mode control register 2 66 168 PPCC Preprocessor clock control register 72 PRM00 Prescaler mode register 00 94 PU0 Pull up resistor option register 0 67 PU2 Pull up resistor option register 2 67 PU3 Pull up resisto...

Page 382: ...ENDIX C REGISTER INDEX User s Manual U17446EJ3V1UD 382 TXB6 Transmit buffer register 6 185 TXS6 Transmit shift register 6 185 W WDTE Watchdog timer enable register 152 WDTM Watchdog timer mode register 151 ...

Page 383: ...to the stack pointer p 33 P121 X1 and P122 X2 pins The P121 X1 and P122 X2 pins are pulled down during reset p 50 P34 pin Because the P34 pin functions alternately as the RESET pin if it is used as an input port pin the function to input an external reset signal to the RESET pin cannot be used The function of the port is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE Also ...

Page 384: ...rrent flows Do not fetch signals from the oscillator p 75 pp Even if TM00 is read the value is not captured by CR010 87 119 pp Hard TM00 16 bit timer counter 00 When TM00 is read count misses do not occur since the input of the count clock is temporarily stopped and then resumed after the read 87 119 pp Set CR000 to other than 0000H in the clear start mode entered on match between TM00 and CR000 T...

Page 385: ...e trigger input takes precedence and the read data is undefined Also if the timer count stop and the input of the capture trigger conflict the capture data is undefined 90 122 CR010 16 bit timer capture compare register 010 Changing the CR010 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 bit Timer Event Counter 00 17 Changing compar...

Page 386: ...0 set TOE00 LVS00 and LVR00 at the same time with the 8 bit memory manipulation instruction When TOE00 is 1 LVS00 and LVR00 can be set with the 1 bit memory manipulation instruction p 93 pp Always set data to PRM00 after stopping the timer operation 95 120 pp Soft If the valid edge of the TI000 pin is to be set as the count clock do not set the clear start mode and the capture trigger at the valid...

Page 387: ... output Changing the CR000 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 bit Timer Event Counter 00 17 Changing compare register during timer operation p 109 Changing the CRC0n0 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 bit Timer Event Counter 00 17 Changing compa...

Page 388: ... capture compare register 0n0 CR0n0 used as a compare register when changing CR0n0 around the timing of a match between 16 bit timer counter 00 TM00 and 16 bit timer capture compare register 0n0 CR0n0 during timer counting the change timing may conflict with the timing of the match so the operation is not guaranteed in such cases To change CR0n0 during timer counting follow the procedure below usi...

Page 389: ...11 p 135 When TMHE1 1 setting the other bits of the TMHMD1 register is prohibited p 137 Soft TMHMD1 8 bit timer H mode register 1 In the PWM output mode be sure to set 8 bit timer H compare register 11 CMP11 when starting the timer count operation TMHE1 1 after the timer count operation was stopped TMHE1 0 be sure to set again even if setting the same value to the CMP11 register p 137 Hard In PWM ...

Page 390: ... STOP instruction execution After HALT STOP mode is released counting is started again using the operation clock of the watchdog timer set before HALT STOP instruction execution by WDTM At this time the counter is not cleared to 0 but holds its value p 155 Sampling time and conversion time The above sampling time and conversion time do not include the clock frequency error Select the sampling time...

Page 391: ...els may also be affected p 176 ADCR ADCRH read has priority After the read operation the new conversion result is written to ADCR ADCRH p 176 Soft Conflicting operations ADM or ADS write has priority ADCR ADCRH write is not performed nor is the conversion end interrupt signal INTAD generated p 176 Noise countermeasures To maintain the 10 bit resolution attention must be paid to noise input to the ...

Page 392: ... and removing the first conversion result p 178 Soft A D conversion result register ADCR ADCRH read operation When a write operation is performed to the A D converter mode register ADM and analog input channel specification register ADS the contents of ADCR and ADCRH may become undefined Read the conversion result following conversion completion before writing to ADM and ADS Using a timing other t...

Page 393: ...startup reception enable status is entered after having set POWER6 to 1 then setting RXE6 to 1 and one clock of the base clock fXCLK6 has elapsed When stopping reception operation set POWER6 to 0 after having set RXE6 to 0 p 188 Set POWER6 1 RXE6 1 in a state where a high level has been input to the RxD6 pin If POWER6 1 RXE6 1 is set during low level input reception is started and correct data wil...

Page 394: ...ASIM6 are 1 or when bit 7 POWER6 and bit 5 RXE6 of ASIM6 are 1 if 0 data has been written to ASICL6 by SBRT6 and SBTT6 p 192 In the case of an SBF reception error return to SBF reception mode again The status of the SBRF6 flag will be held 1 For details on SBF reception refer to 2 i SBF reception in 11 4 2 Asynchronous serial interface UART mode described later p 193 Before setting the SBRT6 bit t...

Page 395: ...ze the transmission unit upon completion of continuous transmission be sure to check that the TXSF6 flag is 0 after generation of the transmission completion interrupt and then execute initialization If initialization is executed while the TXSF6 flag is 1 the transmit data cannot be guaranteed p 202 Be sure to read receive buffer register 6 RXB6 even if a reception error occurs Otherwise an overru...

Page 396: ... even for low priority interrupts p 233 Soft The LSRSTOP setting is valid only when Can be stopped by software is set for the low speed internal oscillator by the option byte p 235 STOP mode When shifting to the STOP mode be sure to stop the peripheral hardware operation before executing STOP instruction except the peripheral hardware that operates on the low speed internal oscillation clock p 236...

Page 397: ... reset by overflow of watchdog timer The watchdog timer is also reset in the case of an internal reset of the watchdog timer p 248 Chapter 15 Hard Reset function RESF Reset control flag register Do not read data by a 1 bit memory manipulation instruction p 252 Soft If an internal reset signal is generated in the POC circuit the reset control flag register RESF is cleared to 00H p 253 Hard Function...

Page 398: ...r depending on the selected system clock source 1 Crystal ceramic oscillation clock is selected The X1 and X2 pins cannot be used as I O port pins because they are used as clock input pins 2 External clock input is selected Because the X1 pin is used as an external clock input pin P121 cannot be used as an I O port pin 3 High speed internal oscillation clock is selected P121 and P122 can be used a...

Page 399: ...et signal is input while the flash memory is being written or erased writing erasing is not guaranteed p 283 The value of the blank data set during block erasure is FFH p 283 Set the CPU clock beforehand so that it is 1 MHz or higher during self programming p 283 Execute self programming after executing the NOP and HALT instructions immediately after executing a specific sequence to set self progr...

Page 400: ...n while MK0 and MK1 FFH between the points before executing the specific sequence that sets self programming mode and after executing the specific sequence that changes the mode to the normal mode p 285 PFS Flash status register Check FPRERR using a 1 bit memory manipulation instruction p 285 FLAPH and FLAPL Flash address pointers H and L Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 befor...

Page 401: ...ation The operating voltage range may also change p 350 Absolute maximum ratings Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ...

Page 402: ...rial Interface Control Register 6 ASICL6 p 196 Modification of Caution in 11 4 2 1 Registers used p 201 Partial modification of description in 11 4 2 2 c Normal transmission p 202 Partial modification of description in and addition of Caution 1 to 11 4 2 2 d Continuous transmission p 259 Addition of Caution 2 to 17 3 2 Low voltage detection level select register LVIS p 268 Addition of 18 3 Caution...

Page 403: ...ification of MAX values of high level input leakage current low level input leakage current high level output leakage current and low level output leakage current Modification of MAX values of supply current IDD5 in STOP mode Addition of setting range of CPU clock and peripheral clock frequency to AC Characteristics Modification of Caution in A D Converter Characteristics pp 351 354 356 359 363 CH...

Page 404: ...and One Capture Register with Both Edges Specified and Note Modification of Figure 6 22 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified and Note Modification of Figure 6 24 Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge Specified and Note Modification of 3 and 4 in 2 16 bit timer counter...

Page 405: ... Cautions for Low Voltage Detector Modification of Figure 17 6 Example of Software Processing After Release of Reset 1 2 CHAPTER 17 LOW VOLTAGE DETECTOR Modification of description and configuration in CHAPTER 18 OPTION BYTE CHAPTER 18 OPTION BYTE Modification of and addition to 19 1 Features Figure 19 2 Environment for Writing Program to Flash Memory is divided into two figures in the case of Fla...

Page 406: ... Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com For further information please contact G06 11A Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 Düsseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 ...

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