CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U17446EJ3V1UD
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(14) Conflicting operations
If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture
register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of
the timer and the input of the capture trigger conflict, the captured data is undefined.
Figure 6-38. Capture Register Data Retention Timing
N
N + 1
N + 2
M
M + 1
M + 2
X
N + 2
M + 1
Count clock
TM00 count value
Edge input
INTTM010
Capture read signal
CR010 capture value
Capture, but
read value is
not guaranteed
Capture
(15) Capture operation
<1> If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the
capture trigger at the valid edge of the TI000 pin.
<2> If both the rising and falling edges are selected as the valid edges of the TI000 pin, capture is not
performed.
<3> When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a
valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external
interrupt source because INTTM000 is generated at that timing.
<4> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two
cycles of the count clock selected by prescaler mode register 00 (PRM00).
<5> The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0),
however, occurs at the rise of the next count clock.
<6> To use two capture registers, set the TI000 and TI010 pins.
Remark
n = 0, 1
