User’s Manual U17446EJ3V1UD
402
APPENDIX E REVISION HISTORY
E.1 Major Revisions in This Edition
(1/2)
Page Description
Throughout
Deletion of description on (T) product, (S) product, (R) product, (T2) product
p. 17
Modification of
1.4 78K0S/Kx1+ Product Lineup
p. 33
Addition of
Caution 2
to
3.2.1 (3) Stack pointer (SP)
p. 56
Modification of
Figure 4-7 Block Diagram of P34
p. 66
Addition of
Caution
to
Figure 4-17 Format of Port Mode Control Register 2
p. 87
Modification of
Caution 2
in
6.2 (1) 16-bit timer counter 00 (TM00)
p. 125
Addition of
6.5 (23) External clock limitation
p. 168
Addition of
Caution
to
Figure 10-8
Format of Port Mode Control Register 2 (PMC2)
p. 178
Addition of
10.6 (10) Operating current at conversion waiting mode
p. 185
Addition of
Caution
to
11.2 (1) Receive buffer register 6 (RXB6)
p. 185
Addition of
Caution 1
to and modification of
Caution 3
in
11.2 (3) Transmit buffer register 6 (TXB6)
p. 186
Correction of
Note 3
in
Figure 11-5 Format of Asynchronous Serial Interface Operation Mode Register 6
(ASIM6) (1/2)
pp. 187, 188
Addition of
Notes 1
and
2
to and modification of
Cautions 1
,
2
and
3
in
Figure 11-5 Format of Asynchronous
Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
p. 192
Modification of
Caution
in
11.3 (6)
Asynchronous serial interface control register 6 (ASICL6)
p. 193
Modification of
Caution 1
in
Figure 11-10
Format of Asynchronous Serial Interface Control Register 6
(ASICL6)
p. 196
Modification of
Caution
in
11.4.2 (1) Registers used
p. 201
Partial modification of description in
11.4.2 (2) (c) Normal transmission
p. 202
Partial modification of description in and addition of
Caution 1
to
11.4.2 (2) (d) Continuous transmission
p. 259
Addition of
Caution 2
to
17.3 (2) Low-voltage detection level select register (LVIS)
p. 268
Addition of
18.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34)
p. 275
Addition of description to
19.6.1 X1 and X2 pins
p. 280
Addition of
Remark 1
to
19.8 Flash Memory Programming by Self Writing
p. 282
Modification of description of internal verify 1 in and addition of description and
Remark
of internal verify 2 to
Table 19-11 Self Programming Controlling Commands
p. 283
Partial modification of and addition to
19.8.2 Cautions on self programming function
p. 284
Addition of
Cautions 2
,
3
and
5
to and modification of
Caution 4
in
Figure 19-12 Format of Flash
Programming Mode Control Register (FLPMC)
p. 285
Modification of
Caution
in and addition of description on FPRERR to
19.8.3 (2) Flash protect command
register (PFCMD)
p. 285
Addition of
Caution
to
19.8.3 (3) Flash status register (PFS)
p. 287
Modification of description and
Note
of internal verify 1 in and addition of description of internal verify 2 to
Figure
19-15 Format of Flash Programming Command Register (FLCMD)
p. 288
Modification of
Caution
in
Figure 19-16 Format of Flash Address Pointer H/L (FLAPH/FLAPL)
and
Caution 1
in
Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC)
