CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ1V0UD
239
Figure 14-3. Timing of Reset by Overflow of Watchdog Timer
<1> With high-speed Ring-OSC clock or external clock input
Hi-Z
Note
Normal operation
in progress
CPU clock
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Internal reset signal
Port pin
High-speed Ring-OSC clock or
external clock input
Operation stops because option byte is referenced.
(8/f
RL
+ 96/f
RH
)
Watchdog timer
overflow
<2> With crystal/ceramic oscillation clock
Hi-Z
Note
Normal operation
in progress
CPU clock
Reset period
(oscillation stops)
Oscillation stabilization
time (2
10
/f
X
to 2
17
/f
X
)
Normal operation
(reset processing, CPU clock)
Internal reset signal
Port pin
Crystal/ceramic
oscillation clock
Operation stops because option byte is referenced.
(8/f
RL
+ 96/f
RH
)
Watchdog timer
overflow
Note P130 outputs a low level, and the other port pins go into a high-impedance state.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark f
X
: System clock oscillation frequency
f
RL
: Low-speed Ring-OSC clock oscillation frequency
f
RH
: High-speed Ring-OSC clock oscillation frequency
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