CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ1V0UD
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(8) Timer
operation
<1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare
register 010 (CR010).
<2> Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins TI000/TI010
are not acknowledged.
<3> One-shot pulse output normally operates only in the free-running mode or in the clear & start mode at
the valid edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a
match between TM00 and CR000, one-shot pulse output is not possible.
(9) Capture
operation
<1> If the TI000 pin is specified as the valid edge of the count clock, a capture operation by the capture
register specified as the trigger for the TI000 pin is not possible.
<2> If both the rising and falling edges are selected as the valid edges of the TI000 pin, capture is not
performed.
<3> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two
cycles of the count clock selected by prescaler mode register 00 (PRM00).
<4> The capture operation is performed at the fall of the count clock. A interrupt request input (INTTM0n0),
however, occurs at the rise of the next count clock.
Remark n = 0, 1
(10) Compare operation
The capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger
is input.
(11) Changing compare register during timer operation
<1> When changing CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit
timer capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with
the timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during
timer counting, follow the procedure below using an INTTM000 interrupt.
<Changing cycle (CR000)>
1. Disable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 0).
2. Disable the INTTM000 interrupt (TMMK000 = 1).
3. Rewrite CR000.
4. Wait for 1 cycle of the TM00 count clock.
5. Enable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 1).
6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0).
7. Enable the INTTM000 interrupt (TMMK000 = 0).
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