CHAPTER 13 STANDBY FUNCTION
Preliminary User’s Manual U16898EJ1V0UD
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(2) STOP
mode
STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops,
stopping the whole system, thereby considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, select the HALT mode if processing must be immediately started by an interrupt request when the
STOP mode is released because the operation stops for the duration of eight clocks of the low-speed Ring-
OSC clock (because an additional wait time for stabilizing oscillation elapses when crystal/ceramic oscillation
is used).
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing STOP instruction (except the peripheral hardware that operates on the low-speed
Ring-OSC clock).
2. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the HALT or STOP instruction.
3. If the low-speed Ring-OSC oscillator is operating before the STOP mode is set, oscillation of
the low-speed Ring-OSC clock cannot be stopped in the STOP mode (refer to Table 13-1).
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