CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ1V0UD
78
Figure 5-16. Status Transition of Low-Speed Ring-OSC Oscillator
LSRSTOP = 0
Cannot be stopped
Can be stopped
Clock source of
WDT is selected
by software
Note
Clock source of
WDT is fixed to f
RL
Low-speed Ring-OSC
oscillator can be stopped
Low-speed Ring-OSC
oscillator cannot be stopped
Low-speed Ring-OSC
oscillator stops
LSRSTOP = 1
V
DD
> 2.1 V
±
0.1 V
Reset signal
Power
application
Reset by
power-on clear
Select by option byte
if low-speed Ring-OSC
can be stopped or not
Note The clock source of the watchdog timer (WDT) is selected from f
XP
or f
RL
, or it may be stopped. For details,
refer to CHAPTER 9 WATCHDOG TIMER.
www.DataSheet4U.com
www.DataSheet4U.com
