CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16898EJ1V0UD
149
9.4.3
Watchdog timer operation in STOP mode (when “low-speed Ring-OSC can be stopped by software” is
selected by option byte)
The watchdog timer stops counting during STOP instruction execution regardless of whether the clock to peripheral
hardware or low-speed Ring-OSC clock is being used.
(1) When the watchdog timer operation clock is the clock to peripheral hardware (f
XP
) when the STOP
instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
operation stops for 8 clocks of the low-speed Ring-OSC clock (after waiting for the oscillation stabilization time set
by the oscillation stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic
oscillation) and then counting is started again using the operation clock before the operation was stopped. At this
time, the counter is not cleared to 0 but holds its value.
Figure 9-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
<1> CPU clock: Crystal/ceramic oscillation clock
Operation stopped
Operating
Oscillation stabilization time
Normal operation
STOP
Oscillation stabilization time
(set by OSTS register)
Oscillation stopped
Watchdog timer
Operating
f
CPU
CPU operation
Normal
operation
Operation
stopped
(8/f
RL
)
<2> CPU clock: High-speed Ring-OSC clock or external clock input
Operation stopped
Operating
Normal operation
Oscillation stopped
Watchdog timer
f
CPU
CPU operation
STOP
Operating
Normal
operation
Operation
stopped
(8/f
RL
)
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