NEC 78K0S/KA1+ Preliminary User'S Manual Download

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CHAPTER 11 SERIAL INTERFACE UART6

Preliminary User’s Manual U16898EJ1V0UD

210

(4) Permissible baud rate range during reception

The permissible error from the baud rate at the transmission destination during reception is shown below.

Caution Make sure that the baud rate error during reception is within the permissible error range, by

using the calculation expression shown below.

Figure 11-26. Permissible Baud Rate Range During Reception

1 data frame (11

FL)

FLmin

FLmax

Data frame length

of UART6

Start bit

Bit 0

Bit 1

Bit 7

Parity bit

Minimum permissible

data frame length

Maximum permissible

data frame length

Stop bit

Start bit

Bit 0

Bit 1

Bit 7

Parity bit

Latch timing

Stop bit

Start bit

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

As shown in Figure 11-26, the latch timing of the receive data is determined by the counter set by baud rate

generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this

latch timing, the data can be correctly received.

Assuming that 11-bit data is received, the theoretical values can be calculated as follows.

FL = (Brate)

−

Brate: Baud rate of UART6

Set value of BRGC6

FL: 1-bit

data

length

Margin of latch timing: 2 clocks

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Summary of Contents for 78K0S/KA1+

Page 1: ...er s Manual PD78F9221 PD78F9222 78K0S KA1 8 Bit Single Chip Microcontrollers Printed in Japan Document No U16898EJ1V0UD00 1st edition Date Published November 2003 N CP K 2003 www DataSheet4U com www D...

Page 2: ...Preliminary User s Manual U16898EJ1V0UD 2 MEMO www DataSheet4U com www DataSheet4U com...

Page 3: ...Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possib...

Page 4: ...e possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers m...

Page 5: ...Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore T...

Page 6: ...ectrical specifications target CPU function Instruction set Instruction description How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineerin...

Page 7: ...User s Manual This manual 78K 0S Series Instructions User s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No Operation U14876E Language U14877E R...

Page 8: ...nual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Dis...

Page 9: ...X2 22 2 2 8 AVREF 22 2 2 9 VDD 23 2 2 10 VSS 23 2 3 Pin I O Circuits and Connection of Unused Pins 23 CHAPTER 3 CPU ARCHITECTURE 25 3 1 Memory Space 25 3 1 1 Internal program memory space 27 3 1 2 Int...

Page 10: ...illator for interval time generation 62 5 2 Configuration of Clock Generators 63 5 3 Registers Controlling Clock Generators 65 5 4 System Clock Oscillators 68 5 4 1 High speed Ring OSC oscillator 68 5...

Page 11: ...Watchdog Timer 143 9 4 Operation of Watchdog Timer 145 9 4 1 Watchdog timer operation when low speed Ring OSC cannot be stopped is selected by option byte 145 9 4 2 Watchdog timer operation when low...

Page 12: ...ding 225 CHAPTER 13 STANDBY FUNCTION 226 13 1 Standby Function and Configuration 226 13 1 1 Standby function 226 13 1 2 Registers used during standby 228 13 2 Standby Function Operation 229 13 2 1 HAL...

Page 13: ...9 INSTRUCTION SET OVERVIEW 271 19 1 Operation 271 19 1 1 Operand identifiers and description methods 271 19 1 2 Description of Operation column 272 19 1 3 Description of Flag column 272 19 2 Operation...

Page 14: ...event counter 1 channel 8 bit timer 2 channels Watchdog timer 1 channel O Serial interface UART LIN Local Interconnect Network bus supported 1 channel O 10 bit resolution A D converter 4 channels O Su...

Page 15: ...AVREF P20 ANI0 P21 ANI1 P22 ANI2 P23 ANI3 P130 P45 P44 RxD6 P43 TxD6 INTP1 P42 TOH1 1 2 3 4 5 6 7 8 9 10 P40 Note VSS and AVSS are internally connected in the 78K0S KA1 Be sure to connect VSS to a sta...

Page 16: ...5 V 4 0 s 500 kHz VDD 2 0 to 5 5 V System clock oscillation frequency Internal high speed Ring OSC oscillation 8 MHz TYP Crystal ceramic oscillation 1 to 10 MHz X1 external clock input oscillation 1 t...

Page 17: ...Port 12 System control High speed Ring OSC RESET P34 X1 P121 X2 P122 Low speed Ring OSC INTP0 P30 INTP1 P43 INTP2 P31 INTP3 P41 ANI0 P20 to ANI3 P23 4 A D converter AVREF 8 bit timer 80 Watchdog time...

Page 18: ...operation Bit manipulation set reset test etc I O port Total 17 pins CMOS I O 15 pins CMOS input 1 pin CMOS output 1 pin Timer 16 bit timer event counter 1 channel 8 bit timer timer H1 1 channel 8 bi...

Page 19: ...ts An on chip pull up resistor can be connected by setting software Input TI010 TO00 INTP2 P34 Input Port 3 Input only Input RESET P40 P41 INTP3 P42 TOH1 P43 TxD6 INTP1 P44 RxD6 P45 I O Port 4 6 bit I...

Page 20: ...ounter 00 Capture trigger input to capture registers CR000 and CR010 of 16 bit timer event counter 00 P30 INTP0 TI010 Input Capture trigger input to capture register CR000 of 16 bit timer event counte...

Page 21: ...ernal interrupt request signal P34 is a 1 bit input only port This pin is also used as a RESET pin P30 and P31 can be set to the following operation modes in 1 bit units 1 Port mode P30 and P31 functi...

Page 22: ...t request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified b TOH1 This is the output pin of 8 bit timer H1 c TxD6 This pin outputs serial...

Page 23: ...Pin I O Circuits and Connection of Unused Pins Pin Name I O Circuit Type I O Recommended Connection of Unused Pin P20 ANI0 to P23 ANI3 11 P30 TI000 INTP0 P31 TI010 TO00 INTP2 8 A I O Input Independen...

Page 24: ...ge VSS P ch N ch Input enable Pull up enable VDD P ch Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch P ch Feedback cut off X1 IN OUT X2 IN OUT OSC enable Data Output disable VDD P ch...

Page 25: ...nternal high speed RAM 256 8 bits Flash memory 4 096 8 bits Program memory space Data memory space Program area Option byte area Program area CALLT table area Vector table area Use prohibited F F F F...

Page 26: ...bits Program memory space Data memory space Program area Option byte area Program area CALLT table area Vector table area Use prohibited F F F F H 0 F F F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 0 8 2 H 0 0...

Page 27: ...st generation Of a 16 bit address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request Vector...

Page 28: ...80H to FFFFH or FE00H to FFFFH can be accessed using a unique addressing mode according to its use such as a special function register SFR Figures 3 3 and 3 4 illustrate the data memory addressing Fig...

Page 29: ...6 8 bits Internal high speed RAM 256 8 bits Flash memory 4 096 8 bits Use prohibited Direct addressing Register indirect addressing Based addressing SFR addressing Short direct addressing F F F F H F...

Page 30: ...n 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction e...

Page 31: ...o the stack memory and is incremented after reading restoring from the stack memory Each stack operation saves restores data as shown in Figures 3 8 and 3 9 Caution Since reset input makes SP contents...

Page 32: ...pairs can be used as a 16 bit register AX BC DE and HL Registers can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figure 3 10 Gene...

Page 33: ...perand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When specifying an a...

Page 34: ...Port mode register 3 PM3 FF24H Port mode register 4 PM4 FF2CH Port mode register 12 PM12 FFH FF32H Pull up resistance option register 2 PU2 FF33H Pull up resistance option register 3 PU3 FF34H Pull up...

Page 35: ...Clock selection register 6 CKSR6 00H FF97H Baud rate generator control register 6 BRGC6 FFH FF98H Asynchronous serial interface control register 6 ASICL6 16H FFCCH 8 bit timer mode control register 80...

Page 36: ...ressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program coun...

Page 37: ...dr 3 3 3 Table indirect addressing Function The table contents branch destination address of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 ar...

Page 38: ...ressing Function The register pair AX contents to be specified with an instruction word are transferred to the program counter PC to branch This function is carried out when the BR AX instruction is e...

Page 39: ...on 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Desc...

Page 40: ...timer counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is cleared to 0 When it is...

Page 41: ...addressing is applied to the 256 byte space FF00H to FFFFH However SFRs mapped at FF00H to FF1FH are accessed with short direct addressing Operand format Identifier Description sfr Special function r...

Page 42: ...When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be d...

Page 43: ...ecified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A D...

Page 44: ...ormat Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area is indire...

Page 45: ...d for various control operations Table 4 1 shows the functions of each port In addition to digital I O port functions each of these ports has an alternate function For details refer to CHAPTER 2 PIN F...

Page 46: ...or can be connected setting software Input P121 X1 P122 X2 P123 I O Port 12 3 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected only to P123 by s...

Page 47: ...option register 2 PU2 This port is also used as the analog input pins of the internal A D converter Reset input sets port 2 to the input mode Figure 4 2 shows the block diagram of port 2 Figure 4 2 B...

Page 48: ...Because the P34 pin functions alternately as the RESET pin if it is used as an input port pin the function to input an external reset signal to the RESET pin cannot be used The function of the port i...

Page 49: ...the input or output mode by using port mode register 4 PM4 When the P40 to P45 pins are used as an input port an on chip pull up resistor can be connected in 1 bit units by using pull up resistor opti...

Page 50: ...4 5 Block Diagram of P40 and P45 P40 P45 WRPU RD WRPORT WRPM PU40 PU45 Output latch P40 P45 PM40 PM45 VDD P ch PU4 PM4 Internal bus Selector PU4 Pull up resistor option register 4 PM4 Port mode regist...

Page 51: ...am of P41 and P44 P41 INTP3 P44 RxD6 WRPU RD WRPORT WRPM PU41 PU44 Alternate function Output latch P41 P44 PM41 PM44 VDD P ch PU4 PM4 Internal bus Selector PU4 Pull up resistor option register 4 PM4 P...

Page 52: ...4 7 Block Diagram of P42 P42 TOH1 WRPU RD WRPORT WRPM PU42 Output latch P42 PM42 Alternate function VDD P ch PM4 PU4 Internal bus Selector PU4 Pull up resistor option register 4 PM4 Port mode registe...

Page 53: ...iagram of P43 P43 Tx6 INTP1 WRPU RD WRPORT WRPM PU43 Alternate function Alternate function Output latch P43 PM43 VDD P ch PU4 PM4 Internal bus Selector PU4 Pull up resistor option register 4 PM4 Port...

Page 54: ...stem clock oscillators can be used 1 High speed Ring OSC circuit The P121 and P122 pins can be used as I O port pins 2 Crystal ceramic oscillator The P121 and P122 pins cannot be used as I O port pins...

Page 55: ...Figure 4 10 Block Diagram of P123 P123 WRPU RD WRPORT WRPM PU123 Output latch P123 PM123 VDD P ch PM12 PU12 Internal bus Selector PU12 Pull up resistor option register 12 PM12 Port mode register 12 RD...

Page 56: ...P12 P13 Port mode control register 2 PMC2 Pull up resistor option registers PU2 PU3 PU4 PU12 1 Port mode registers PM2 PM3 PM4 PM12 These registers are used to set the corresponding port to the input...

Page 57: ...M123 PM122 PM121 1 PMmn Selection of I O mode of Pmn pin m 2 3 4 or 12 n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 2 Port registers P2 P3 P4 P12 P13 These registers are used...

Page 58: ...0 0 P123 P122 P121 0 Address FF0DH After reset 00H Output latch R W Symbol 7 6 5 4 3 2 1 0 P13 0 0 0 0 0 0 0 P130 m 2 3 4 12 or 13 n 0 7 Pmn Controls of output data in output mode Input data read in...

Page 59: ...of Port Mode Register Port Register Output Latch and Port Mode Control Register When Alternate Function Is Used Alternate Function Pin Pin Name Name I O PM P PMC2n n 0 to 3 P20 to P23 ANI0 to ANI3 In...

Page 60: ...instruction Reset input set these registers to 00H Figure 4 15 Format of Pull up Resistor Option Register Address FF32H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU2 0 0 0 0 PU23 PU22 PU21 PU20 Addr...

Page 61: ...r instruction Because the output buffer is off however the pin status remains unchanged Once data is written to the output latch it is retained until new data is written to the output latch 4 4 2 Read...

Page 62: ...It can oscillate a clock of 500 kHz to 10 MHz Oscillation of this circuit can be stopped by execution of the STOP instruction External clock input circuit This circuit supplies a clock from an extern...

Page 63: ...Configuration Control registers Processor clock control register PCC Preprocessor clock control register PPCC Low speed Ring OSC mode register LSRCM High speed Ring OSC mode register HSRCM Oscillatio...

Page 64: ...nter Selector Prescaler Clock to peripheral hardware fXP 8 bit timer H1 watchdog timer Option byte 1 Cannot be stopped 0 Can be stopped Low speed Ring OSC mode register LSRCM High speed Ring OSC mode...

Page 65: ...are set by using a 1 bit or 8 bit memory manipulation instruction Reset input sets PCC and PPCC to 02H Figure 5 2 Format of Processor Clock Control Register PCC Address FFFBH After reset 02H R W Symb...

Page 66: ...ed by software If it is specified by the option byte that the low speed Ring OSC oscillator cannot be stopped by software setting of this register is invalid and the low speed Ring OSC oscillator cont...

Page 67: ...stal ceramic oscillation clock is selected as the system clock and after the STOP mode is released If the high speed Ring OSC oscillator or external clock input is selected as the system clock source...

Page 68: ...following three types of system clock oscillators are available High speed Ring OSC oscillator Internally oscillates a clock of 8 MHz TYP Crystal ceramic oscillator Oscillates a clock of 500 kHz to 1...

Page 69: ...of the crystal ceramic oscillator Figure 5 7 External Circuit of Crystal Ceramic Oscillator VSS X1 X2 Crystal resonator or ceramic resonator Caution When using the crystal ceramic oscillator wire as...

Page 70: ...ncorrect Resonator Connection 1 2 a Too long wiring of connected circuit b Crossed signal lines VSS X1 X2 VSS X1 X2 PORT c Wiring near high fluctuating current d Current flowing through ground line of...

Page 71: ...RT FUNCTIONS Figure 5 9 shows an external circuit of the external clock input circuit Figure 5 9 External Circuit of External Clock Input Circuit X1 External clock 5 4 4 Prescaler The prescaler divide...

Page 72: ...cted as the oscillator the CPU can be started without having to wait for the oscillation stabilization time of the system clock Therefore the start time can be shortened Improvement of expandability I...

Page 73: ...LT STOP Interrupt Reset signal Interrupt Power application Reset by power on clear High speed Ring OSC selected by option byte Clock division ratio variable during CPU operation Remark PCC Processor c...

Page 74: ...by the oscillation stabilization time select register OSTS Remark fRL Low speed Ring OSC clock oscillation frequency fRH High speed Ring OSC clock oscillation frequency a The internal reset signal is...

Page 75: ...ntrol register 3 External clock input circuit If external clock input is selected by the option byte the following is possible High speed operation The accuracy of processing is improved as compared w...

Page 76: ...tion on power application the option byte is referenced after reset and the system clock is selected b The option byte is referenced and the system clock is selected Then the external clock operates a...

Page 77: ...ed by software If it is specified that the low speed Ring OSC oscillator can be stopped by software oscillation can be started or stopped by using the low speed Ring OSC mode register LSRCM If it is s...

Page 78: ...Low speed Ring OSC oscillator can be stopped Low speed Ring OSC oscillator cannot be stopped Low speed Ring OSC oscillator stops LSRSTOP 1 VDD 2 1 V 0 1 V Reset signal Power application Reset by powe...

Page 79: ...ally Valid level pulse width 16 fXP or more 3 Pulse width measurement 16 bit timer event counter 00 can measure the pulse width of an externally input signal Valid level pulse width 2 fXP or more 4 Sq...

Page 80: ...3 PM3 Port register 3 P3 Figures 6 1 shows a block diagram of these counters Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC00 TI010 TO00...

Page 81: ...re compare register 000 CR000 CR000 is a 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a capture register or as a compare register is...

Page 82: ...he free running mode and in the clear start mode using the valid edge of TI000 if CR000 is set to 0000H an interrupt request INTTM000 is generated when CR000 changes from 0000H to 0001H following over...

Page 83: ...TI000 Pin CRC002 1 CR010 Capture Trigger TI000 Pin Valid Edge ES010 ES000 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Rema...

Page 84: ...PRM00 Port mode register 3 PM3 Port register 3 P3 1 16 bit timer mode control register 00 TMC00 This register sets the 16 bit timer operating mode the 16 bit timer counter 00 TM00 clear mode and outpu...

Page 85: ...et value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H the OVF00 flag is set to 1 Remark TM00 16 bit timer counter 00 CR000 16 bit timer capture compare register 000 CR010 16 bit ti...

Page 86: ...r selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase CRC000 CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register...

Page 87: ...rol using match of CR010 and TM00 0 Disables inversion operation 1 Enables inversion operation LVS00 LVR00 Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F...

Page 88: ...external clock requires a pulse longer than two cycles of the internal count clock fXP Cautions 1 Always set data to PRM00 after stopping the timer operation 2 If the valid edge of the TI000 pin is t...

Page 89: ...00 TI010 INTP2 pins as a timer input set PM30 and PM31 to 1 At this time the output latches of P30 and P31 can be either 0 or 1 PM3 is set by a 1 bit or 8 bit memory manipulation instruction Reset inp...

Page 90: ...ution Changing the CR000 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 11 Changing compare register during...

Page 91: ...l register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register c Prescaler mode register 00 PRM00 ES110 0 1 ES100 0 1 ES010 0 1 ES000 0 1 3 0 2 0 PRM001 0...

Page 92: ...N Timer operation enabled Clear Clear Interrupt acknowledged Interrupt acknowledged Remark Interval time N 1 t N 0001H to FFFFH When the compare register is changed during timer count operation if th...

Page 93: ...e number of external clock pulses to be input to the TI000 pin with using 16 bit timer counter 00 TM00 TM00 is incremented each time the valid edge specified by prescaler mode register 00 PRM00 is inp...

Page 94: ...are control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register c Prescaler mode register 00 PRM00 ES110 0 1 ES100 0 1 ES010 0 ES000 1 3 0 2 0 PRM...

Page 95: ...e INTTM000 Noise eliminator fXP Valid edge of TI000 Note OVF00 is 1 only when 16 bit timer capture compare register 000 is set to FFFFH Figure 6 16 External Event Counter Operation Timing with Rising...

Page 96: ...in the count clock cycle selected by prescaler mode register 00 PRM00 and the valid level of the TI000 or TI010 pin is detected twice thus eliminating noise with a short pulse width Figure 6 17 CR010...

Page 97: ...oise with a short pulse width Figure 6 18 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register When TI000 and CR010 Are Used a 16 bit timer mode con...

Page 98: ...capture compare register 010 CR010 Internal bus INTTM010 Selector Figure 6 20 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified t 0...

Page 99: ...d ES110 of PRM00 Sampling is performed using the count clock cycle selected by prescaler mode register 00 PRM00 and a capture operation is only performed when a valid level of the TI000 or TI010 pin i...

Page 100: ...ter with Both Edges Specified t 0000H 0000H FFFFH 0001H D0 D0 D1 D0 t D3 D2 t 10000H D1 D2 t 10000H D1 D2 1 t D1 D2 1 D1 D2 D2 D3 D0 1 D1 D1 1 D2 1 D2 2 Note TI010 pin input CR000 capture value INTTM0...

Page 101: ...only performed when a valid level of the TI000 pin is detected twice thus eliminating noise with a short pulse width Figure 6 23 Control Register Settings for Pulse Width Measurement with Free Running...

Page 102: ...timer counter 00 TM00 is taken into 16 bit timer capture compare register 010 CR010 and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count...

Page 103: ...d as capture register Captures to CR000 at inverse edge to valid edge of TI000 CR010 used as capture register c Prescaler mode register 00 PRM00 ES110 0 1 ES100 0 1 ES010 0 ES000 1 3 0 2 0 PRM001 0 1...

Page 104: ...e TO00 pin see 6 3 5 Port mode register 3 PM3 2 For how to enable the INTTM000 interrupt see CHAPTER 12 INTERRUPT FUNCTIONS A square wave with any selected frequency can be output at intervals determi...

Page 105: ...h between TM00 and CR010 Disables one shot pulse output d Prescaler mode register 00 PRM00 ES110 0 1 ES100 0 1 ES010 0 1 ES000 0 1 3 0 2 0 PRM001 0 1 PRM000 0 1 PRM00 Selects count clock Setting inval...

Page 106: ...using the PRM00 register 6 Set the TMC00 register to start the operation see Figure 6 29 for the set value Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction To change...

Page 107: ...OE00 1 TOC00 Enables TO00 output Inverts output on match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts output on match between TM00 and CR010 Disab...

Page 108: ...uit Noise eliminator fXP fXP fXP 22 fXP 28 TI000 INTP0 P30 16 bit timer capture compare register 010 CR010 TO00 TI010 INTP2 P31 Selector Output controller Figure 6 31 PPG Output Operation Timing t 000...

Page 109: ...g bit 6 OSPT00 of the TOC00 register to 1 by software By setting the OSPT00 bit to 1 16 bit timer event counter 00 is cleared and started and its output becomes active at the count value N set in adva...

Page 110: ...output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00...

Page 111: ...r 00 TOC00 as shown in Figure 6 34 and by using the valid edge of the TI000 pin as an external trigger The valid edge of the TI000 pin is specified by bits 4 and 5 ES000 ES010 of prescaler mode regist...

Page 112: ...ter 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 TOC001 TOE00 OSPE00 OSPT00 TOC004 LVS00 Enables TO00 output Inverts output upon match between TM00 and CR000 Speci...

Page 113: ...N N N M M M M M N 1 N 2 M 1 M 2 M 2 M 1 0001H 0000H Count clock TM00 count value CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output When TMC00 is set to 08H TM00 count s...

Page 114: ...tting Set the valid edge of the TI000 pin after setting bits 2 and 3 TMC002 and TMC003 of 16 bit timer mode control register 00 TMC00 to 0 0 respectively and then stopping the timer operation The vali...

Page 115: ...d clear is disabled 7 Conflicting operations 1 When the 16 bit timer capture compare register CR000 CR010 is used as a compare register if the write period and the match timing of 16 bit timer counter...

Page 116: ...s of the count clock selected by prescaler mode register 00 PRM00 4 The capture operation is performed at the fall of the count clock A interrupt request input INTTM0n0 however occurs at the rise of t...

Page 117: ...e TO00 pin at each rewrite 12 Edge detection 1 If the TI000 pin or the TI010 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as...

Page 118: ...tion 2 6 fXP 8 s 2 14 fXP 2 05 ms 2 6 fXP 8 s 2 8 fXP 32 s 2 16 fXP 8 19 ms 2 8 fXP 32 s 2 10 fXP 128 s 2 18 fXP 32 7 ms 2 10 fXP 128 s fXP 8 0 MHz 2 16 fXP 8 19 ms 2 24 fXP 2 01 s 2 16 fXP 8 19 ms 2...

Page 119: ...0 Register 8 bit compare register 80 CR80 Control register 8 bit timer mode control register 80 TMC80 Figure 7 1 Block Diagram of 8 Bit Timer 80 Internal bus Internal bus 8 bit compare register 80 CR8...

Page 120: ...re 7 2 Format of 8 Bit Compare Register 80 CR80 Symbol CR80 Address FFCDH After reset Undefined W 7 6 5 4 3 2 1 0 Caution When changing the value of CR80 be sure to stop the timer operation If the val...

Page 121: ...clears TMC80 to 00H Figure 7 4 Format of 8 Bit Timer Mode Control Register 80 TMC80 Address FFCCH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TMC80 TCE80 0 0 0 0 TCL801 TCL800 0 TCE80 Control of operat...

Page 122: ...If the value of CR80 is changed with the timer operation enabled a match interrupt request signal may be generated immediately 2 If the count clock of TMC80 is set and the operation of TM80 is enabled...

Page 123: ...imer Operation Clear Clear Interrupt acknowledged Interrupt acknowledged Count start Interval time Interval time Interval time Count clock TM80 count value CR80 TCE80 INTTM80 TO80 N 01H 00H N 01H 00H...

Page 124: ...6 Figure 7 6 Case Where Error of 1 5 Clocks Max Occurs 8 bit timer counter 80 TM80 Count pulse Clear signal Selected clock TCE80 Delay A Delay B Selected clock TCE80 Clear signal Count pulse TM80 coun...

Page 125: ...8 bit timer H1 consists of the following hardware Table 8 1 Configuration of 8 Bit Timer H1 Item Configuration Timer register 8 bit timer counter H1 Registers 8 bit timer H compare register 01 CMP01...

Page 126: ...1 8 bit timer H mode register 1 TMHMD1 8 bit timer H compare register 11 CMP11 Decoder TOH1 P42 INTTMH1 Selector fXP fXP 22 fXP 24 fXP 26 fXP 212 fRL 27 Interrupt generator Output controller Level inv...

Page 127: ...ipulation instruction Reset input clears this register to 00H Figure 8 3 Format of 8 Bit Timer H Compare Register 11 CMP11 Symbol CMP11 Address FF0FH After reset 00H R W 7 6 5 4 3 2 1 0 CMP11 can be r...

Page 128: ...d to control 8 Bit Timer H1 8 bit timer H mode register 1 TMHMD1 Port mode register 4 PM4 Port register 4 P4 1 8 bit timer H mode register 1 TMHMD1 This register controls the mode of timer H This regi...

Page 129: ...M output mode Setting prohibited TMMD11 0 1 TMMD10 0 0 Timer operation mode Low level High level TOLEV1 0 1 Timer output level control in default mode Disable output Enable output TOEN1 0 1 Timer outp...

Page 130: ...output latch of P42 to 0 PM4 can be set by a 1 bit or 8 bit memory manipulation instruction Reset input sets this register to FFH Figure 8 5 Format of Port Mode Register 4 PM4 Address FF24H After rese...

Page 131: ...1 Usage Generates the INTTMH1 signal repeatedly at the same interval 1 Set each register Figure 8 6 Register Setting During Interval Timer Square Wave Output Operation i Setting timer H mode register...

Page 132: ...clear 2 Level inversion match interrupt occurrence 8 bit timer counter H1 clear 3 1 1 The count operation is enabled by setting the TMHE1 bit to 1 The count clock starts counting no more than 1 clock...

Page 133: ...ion 2 2 b Operation when CMP01 FFH 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP01 00H Coun...

Page 134: ...uty and arbitrary cycle can be set is output 1 Set each register Figure 8 8 Register Setting in PWM Output Mode i Setting timer H mode register 1 TMHMD1 0 0 1 0 1 0 1 1 0 0 1 1 TMMD10 TOLEV1 TOEN1 CKS...

Page 135: ...f the setting value of the CMP01 register is N the setting value of the CMP11 register is M and the count clock frequency is fCNT the PWM pulse output cycle and duty are as follows PWM pulse output cy...

Page 136: ...t operation is enabled by setting the TMHE1 bit to 1 Start 8 bit timer counter H1 by masking one count clock to count up At this time TOH1 output remains inactive when TOLEV1 0 2 When the values of 8...

Page 137: ...11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP11 FFH 00H c Operation when CMP01 FFH CMP11 FEH Count clock 8 bit timer c...

Page 138: ...J1V0UD 138 Figure 8 9 Operation Timing in PWM Output Mode 3 4 d Operation when CMP01 01H CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 01H 00H 01H 00H 01H 00H 00H 01H...

Page 139: ...is cleared the TOH1 output becomes active and the INTTMH1 signal is output 4 If the CMP11 register value is changed the value is latched and not transferred to the register When the values of 8 bit t...

Page 140: ...ion of Clock to Peripheral Hardware fRL 2 11 8 53 ms fXP 2 13 819 2 s fRL 2 12 17 07 ms fXP 2 14 1 64 ms fRL 2 13 34 13 ms fXP 2 15 3 28 ms fRL 2 14 68 27 ms fXP 2 16 6 55 ms fRL 2 15 136 53 ms fXP 2...

Page 141: ...dog timer can be stopped Note 2 Notes 1 As long as power is being supplied low speed Ring OSC oscillation cannot be stopped except in the reset period 2 The conditions under which clock supply to the...

Page 142: ...er enable register WDTE Figure 9 1 Block Diagram of Watchdog Timer fRL 22 Clock input controller Output controller Internal reset signal WDCS2 Internal bus WDCS1 WDCS0 fXP 24 WDCS3 WDCS4 0 1 1 Selecto...

Page 143: ...te 1 WDCS3 Note 1 Operation clock selection 0 0 Low speed Ring OSC clock fRL 0 1 Clock to peripheral hardware fXP 1 Watchdog timer operation stopped Overflow time setting WDCS2 Note 2 WDCS1 Note 2 WDC...

Page 144: ...peripheral hardware 3 Don t care 4 Figures in parentheses apply to operation at fRL 240 kHz TYP fXP 10 MHz 2 Watchdog timer enable register WDTE Writing ACH to WDTE clears the watchdog timer counter...

Page 145: ...t memory manipulation instructionNotes 1 2 Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 Th...

Page 146: ...Option Byte Reset WDT clock fRL Overflow time 1 09 s TYP STOP WDT count continues HALT WDT count continues STOP instruction HALT instruction WDT clock is fixed to fRL Select overflow time settable onl...

Page 147: ...og timer operation stopped Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As soon as WDTM is...

Page 148: ...DT count stops HALT WDT count stops STOP instruction HALT instruction Interrupt Interrupt WDTE ACH Clear WDT counter WDT operation stops WDCS4 1 WDT clock fXP Overflow time fXP 213 to fXP 220 WDT coun...

Page 149: ...he oscillation stabilization time select register OSTS after operation stops in the case of crystal ceramic oscillation and then counting is started again using the operation clock before the operatio...

Page 150: ...er is not cleared to 0 but holds its value Figure 9 7 Operation in STOP Mode WDT Operation Clock Low Speed Ring OSC Clock 1 CPU clock Crystal ceramic oscillation clock Operating Oscillation stabilizat...

Page 151: ...operation clock of the watchdog timer is the clock to peripheral hardware fXP or low speed Ring OSC clock fRL After HALT mode is released counting is started again using the operation clock before th...

Page 152: ...bit resolution A D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3 Each time an A D conversion operation ends an interrupt request INTAD is generated Figu...

Page 153: ...0 0 24 fXP 72 fXP 3 0 s 9 0 s 2 4 s 7 2 s 1 0 1 48 fXP 96 fXP 6 0 s 12 0 s 4 8 s 9 6 s 1 1 0 96 fXP 144 fXP 12 0 s 18 0 s 9 6 s 14 4 s 1 1 1 176 fXP 224 fXP 22 0 s 28 0 s 17 2 s 22 4 s Notes 1 Set th...

Page 154: ...ator Controller A D conversion result register ADCR ADCRH Analog input channel specification register ADS A D converter mode register ADM Internal bus Successive approximation register SAR ANI0 P20 AN...

Page 155: ...circuit samples the input signal of the analog input pin selected by the selector when A D conversion is started and holds the sampled analog input voltage value during A D conversion 3 Series resisto...

Page 156: ...ot used connect this pin to VDD The signal input to ANI0 to ANI3 is converted into a digital signal based on the voltage applied across AVREF and VSS In the standby mode the current flowing through th...

Page 157: ...D converter uses the following six registers A D converter mode register ADM Analog input channel specification register ADS 10 bit A D conversion result register ADCR 8 bit A D conversion result reg...

Page 158: ...7 2 s 1 0 1 48 fXP 96 fXP 6 0 s 12 0 s 4 8 s 9 6 s 1 1 0 96 fXP 144 fXP 12 0 s 18 0 s 9 6 s 14 4 s 1 1 1 176 fXP 224 fXP 22 0 s 28 0 s 17 2 s 22 4 s ADCE Boost reference voltage generator operation c...

Page 159: ...rates Note Data of first conversion cannot be used Figure 10 5 Timing Chart When Boost Reference Voltage Generator Is Used ADCE Boost reference voltage ADCS Conversion operation Conversion operation C...

Page 160: ...six bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the successive approximation register and is stored in ADCR in order starting from bit 1 of FF19H FF19H indi...

Page 161: ...to PM23 to 1 At this time the output latches of P20 to P23 may be 0 or 1 PMC2 and PM2 are set by a 1 bit or 8 bit memory manipulation instruction Reset input clears PMC2 to 00H and sets PM2 to FFH Fi...

Page 162: ...REF the MSB is reset to 0 8 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset val...

Page 163: ...operations are performed continuously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to ADM or the analog input channel specification...

Page 164: ...part of value in parentheses VAIN Analog input voltage AVREF AVREF pin voltage ADCR 10 bit A D conversion result register ADCR value SAR Successive approximation register Figure 10 12 shows the relati...

Page 165: ...nversion result register ADCR ADCRH and an interrupt request signal INTAD is generated Once the A D conversion has started and when one A D conversion has been completed the next A D conversion operat...

Page 166: ...R ADCRH Change the channel 6 Change the channel using bits 1 and 0 ADS1 ADS0 of ADS 7 An interrupt request signal INTAD is generated 8 Transfer the A D conversion data to the A D conversion result reg...

Page 167: ...the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is c...

Page 168: ...value Figure 10 16 Zero Scale Error Figure 10 17 Full Scale Error 111 011 010 001 Zero scale error Ideal line 000 0 1 2 3 AVREF Digital output Lower 3 bits Analog input LSB 111 110 101 000 0 AVREF 3 F...

Page 169: ...ADCR ADCRH read has priority After the read operation the new conversion result is written to ADCR ADCRH 2 Conflict between ADCR ADCRH write and A D converter mode register ADM write or analog input c...

Page 170: ...internal sampling capacitor is charged and sampling is performed for approx one sixth of the conversion time Since only the leakage current flows other than during sampling and the current for chargin...

Page 171: ...RH ADIF ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended Remarks 1 n 0 to 3 2 m 0 to 3 9 Conversion results just after A D con...

Page 172: ...In Pin ANIn COUT CIN RIN LSI internal Table 10 4 Resistance and Capacitance Values of Equivalent Circuit AVREF RIN COUT CIN 2 7 V T B D T B D T B D 4 5 V T B D T B D T B D Remarks 1 The resistance and...

Page 173: ...from 13 to 20 bits More than 11 bits can be identified for synchronous break field reception SBF reception flag provided Cautions 1 The TXD6 output inversion function inverts only the transmission sid...

Page 174: ...ible when the baud rate error in the slave is 15 or less Figures 11 1 and 11 2 outline the transmission and reception operations of LIN Figure 11 1 LIN Transmission Operation Sleep bus Wakeup signal f...

Page 175: ...n completion interrupt enables the capture timer Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the shift register and RXB...

Page 176: ...elector Selector Remark ISC0 ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 11 11 The peripheral functions used in the LIN communication operation are shown below Peripheral fun...

Page 177: ...mit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception error status register...

Page 178: ...er 6 RXB6 RXD6 P44 TI000 INTP0Note INTSR6 Baud rate generator Filter INTSRE6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mode register...

Page 179: ...ly manipulated by a program 3 Transmit buffer register 6 TXB6 This buffer register is used to set transmit data Transmission is started when data is written to TXB6 This register can be read or writte...

Page 180: ...6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 11 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF90H After reset 01H R W Symbol 7...

Page 181: ...1 INTSR6 occurs in case of error at this time INTSRE6 does not occur Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE6 of asynchronous serial interface reception e...

Page 182: ...RXE6 0 or if ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if A...

Page 183: ...data is transferred to transmit shift register 6 TXS6 1 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If POWER6 0 or TXE6 0 or...

Page 184: ...6 CKSR6 Address FF96H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock fXCLK6 selection 0 0 0 0 fXP 10 MHz 0 0 0 1 fXP 2 5 MHz 0 0 1...

Page 185: ...H R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 Setting prohibite...

Page 186: ...of ASIM6 1 Note however that communication is started by the refresh operation because bit 6 SBRT6 of ASICL6 is cleared to 0 when communication is completed when an interrupt signal is generated Figur...

Page 187: ...LSB TXDLV6 Enabling disabling inverting TXD6 output 0 Normal output of TXD6 1 Inverted output of TXD6 Cautions 1 In the case of an SBF reception error return the mode to the SBF reception mode and ho...

Page 188: ...0 TI000 P30 1 RxD6 P44 ISC0 INTP0 input source selection 0 INTP0 P30 1 RxD6 P44 8 Port mode register 4 PM4 This register sets port 4 input output in 1 bit units When using the P43 TxD6 INTP1 pin for...

Page 189: ...f internal operation clock 0 Note 1 Disable operation of the internal operation clock fix the clock to low level and asynchronously reset the internal circuit Note 2 TXE6 Enabling disabling transmissi...

Page 190: ...onous serial interface control register 6 ASICL6 Input switch control register ISC Port mode register 4 PM4 Port register 4 P4 The basic procedure of setting an operation in the UART mode is as follow...

Page 191: ...4 UART6 Operation TxD6 INTP1 P43 RxD6 P44 0 0 0 Note Note Note Note Stop P43 P44 0 1 Note Note 1 Reception P43 RxD6 1 0 0 1 Note Note Transmission TxD6 P44 1 1 1 0 1 1 Transmission reception TxD6 RxD6...

Page 192: ...Start bit Parity bit D7 D6 D5 D4 D3 1 data frame Character bits D2 D1 D0 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits Parity bit Even parity odd p...

Page 193: ...munication data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TXD6 pin inverted output 1 data frame...

Page 194: ...ts that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is control...

Page 195: ...t shift register 6 TXS6 After that the data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission comple...

Page 196: ...the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6...

Page 197: ...ecessary number of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurred Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processing Transfer executed...

Page 198: ...3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writi...

Page 199: ...XSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission st...

Page 200: ...n received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not writ...

Page 201: ...e Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before d...

Page 202: ...e same the output of the match detector changes and the data is sampled as input data Because the circuit is configured as shown in Figure 11 21 the internal processing of the reception operation is d...

Page 203: ...ting of 10 bits 1 bit start bit 8 bits character bits 1 bit parity bit Adjust the baud rate value to adjust this 10 bit low level to the targeted 13 bit SBF length SBL62 SBL61 SBL60 1 0 1 Example If L...

Page 204: ...E6 bit of ASIM6 register to 1 to enable transmission Set SBTT6 bit to 1 and set TXB6 register to 00H to start transmission INTST6 occurred No Yes Clear TXE6 and RXE6 bits of ASIM6 register to 0 SBTT6...

Page 205: ...nerated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial inte...

Page 206: ...smission counter This counter stops operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TX...

Page 207: ...or BRGC6 MDL67 to MDL60 1 2 POWER6 TXE6 or RXE6 CKSR6 TPS63 to TPS60 fXP fXP 2 fXP 22 fXP 23 fXP 24 fXP 25 fXP 26 fXP 27 fXP 28 fXP 29 fXP 210 fXP 211 fXCLK6 Remark POWER6 Bit 7 of asynchronous serial...

Page 208: ...6 register k Value set by MDL67 to MDL60 bits of BRGC6 register k 8 9 10 255 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 100 Cautions 1 Keep the baud...

Page 209: ...11 10400 2H 120 10417 0 16 2H 96 10417 0 16 1H 101 10475 0 28 19200 1H 130 19231 0 16 1H 104 19231 0 16 0H 109 19220 0 11 31250 1H 80 31250 0 00 0H 128 31250 0 00 0H 67 31268 0 06 38400 0H 130 38462 0...

Page 210: ...Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bi...

Page 211: ...between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 11 5 Maximum Minimum Permissible Baud Rate Error Division Rat...

Page 212: ...ing is initialized on the reception side when the start bit is detected Figure 11 27 Data Frame Length During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL...

Page 213: ...rupts Maskable interrupts These interrupts undergo mask control If two or more interrupt requests are simultaneously generated each interrupt has a predetermined priority as shown in Table 12 1 A stan...

Page 214: ...are register is specified 0010H 7 INTAD End of A D conversion 0012H 8 INTFLC End of flash memory programming Internal 0014H A 9 INTP2 0016H 10 INTP3 Pin input edge detection External 0018H B 11 INTTM8...

Page 215: ...l bus Interrupt request Vector table address generator Standby release signal B External maskable interrupt Internal bus External interrupt mode register INTM0 INTM1 MK IF IE Vector table address gene...

Page 216: ...W Table 12 2 lists interrupt requests the corresponding interrupt request flags and interrupt mask flags Table 12 2 Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt...

Page 217: ...st Flag Registers IF0 IF1 Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0 Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1 0 STIF...

Page 218: ...H R W Symbol 7 6 5 4 3 2 1 0 MK0 ADMK TMMK010 TMMK000 TMMKH1 PMK1 PMK0 LVIMK 1 Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1 1 STMK6 SRMK6 SREMK6 TMMK80 PMK3 PMK2 FLMK MK Interrupt serv...

Page 219: ...ng edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 INTP1 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and fallin...

Page 220: ...upts To enable interrupts clear PIF3 to 0 then clear PMK3 to 0 5 Program status word PSW The program status word is used to hold the instruction execution result and the current status of the interrup...

Page 221: ...to Servicing Minimum Time Maximum Time Note 9 clocks 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instructions Remark 1 clock fCPU CPU cl...

Page 222: ...e of MOV A r Clock CPU Interrupt MOV A r Saving PSW and PC jump to interrupt servicing 8 clocks Interrupt servicing program If an interrupt request flag IF is set before an instruction clock n n 4 to...

Page 223: ...tion the interrupt acknowledgment processing starts after the next instruction is executed Figure 12 9 shows an example of the interrupt request acknowledgment timing for an interrupt request flag tha...

Page 224: ...RETI IE 0 During interrupt INTxx servicing interrupt request INTyy is acknowledged and multiple interrupts are generated The EI instruction is issued before each interrupt request acknowledgment and t...

Page 225: ...tion of the execution of the next instruction even if the interrupt request maskable interrupt and external interrupt is generated during the execution The following shows such instructions interrupt...

Page 226: ...setting is valid only when Can be stopped by software is set for the low speed Ring OSC oscillator by the option byte Remark LSRSTOP Bit 0 of the low speed Ring OSC mode register LSRCM The standby fun...

Page 227: ...ither of these two modes all the contents of registers flags and data memory just before the standby mode is set are held The I O port output latches and output buffer statuses are also held Cautions...

Page 228: ...is set by using the 8 bit memory manipulation instruction Figure 13 1 Format of Oscillation Stabilization Time Select Register OSTS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 OSTS...

Page 229: ...er event counter 00 Operable 8 bit timer 80 Operable Sets count clock to fXP to fXP 2 12 Operable Low speed Ring OSC cannot be stopped Note 2 8 bit timer H1 Sets count clock to fRL 2 7 Low speed Ring...

Page 230: ...d the next address instruction is executed Figure 13 2 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation System clock osc...

Page 231: ...oscillation clock HALT instruction Reset signal System clock oscillation Operation mode HALT mode Reset period Operation stopsNote Oscillation stabilization waits Oscillates Oscillation stops Oscilla...

Page 232: ...n Low Speed Ring OSC Oscillation Stops Note 1 System clock Oscillation stops CPU Operation stops Port latch Holds status before STOP mode is set 16 bit timer event counter 00 Operation stops 8 bit tim...

Page 233: ...d STOP mode High speed Ring OSC clock or external clock input Operation stops 8 fRL 2 If crystal ceramic oscillation clock is selected as system clock to be supplied System clock oscillation CPU clock...

Page 234: ...mode Operation mode Oscillation STOP instruction STOP mode Standby release signal System clock oscillation CPU status Oscillation Oscillation stops Operation stops Interrupt request 8 fRL 2 If CPU clo...

Page 235: ...STOP instruction Reset signal System clock oscillation Operation mode STOP mode Reset period Operation stopsNote Operation mode Oscillation Oscillation stops Oscillation CPU status Oscillation stabili...

Page 236: ...referenced and the clock oscillation stabilization time elapses if crystal ceramic oscillation is selected A reset generated by the watchdog timer source is automatically released after the reset and...

Page 237: ...hdog timer RESET Reset signal of power on clear circuit Reset signal of low voltage detector Reset signal Reset signal Reset signal to LVIM LVIS register Clear Set Clear Set Caution The LVI circuit is...

Page 238: ...fRL 96 fRH 2 With crystal ceramic oscillation clock Delay Hi ZNote Normal operation in progress CPU clock Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operati...

Page 239: ...lation clock Hi ZNote Normal operation in progress CPU clock Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock Internal reset s...

Page 240: ...operation in progress CPU clock Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock RESET Internal reset signal Port pin Crystal...

Page 241: ...elect register OSTS Undefined Timer counter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Mode control register 00 TMC00 00H Prescaler mode register 00 PRM00 00H Capture compare co...

Page 242: ...rol register 6 BRGC6 FFH Asynchronous serial interface control register 6 ASICL6 16H Serial interface UART6 Input select control register ISC 00H Reset function Reset control flag register RESF 00H No...

Page 243: ...WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer WDT 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by...

Page 244: ...F is cleared to 00H 2 Because the detection voltage VPOC of the POC circuit is in a range of 2 1 V 0 1 V use a voltage in the range of 2 2 to 5 5 V Remark This product incorporates multiple hardware f...

Page 245: ...voltage source VPOC Internal reset signal VDD VDD 15 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VDD and detection voltage VPOC 2 1 V 0 1 V are compared and...

Page 246: ...er and then initialize the ports Figure 15 3 Example of Software Processing After Release of Reset 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Power on clea...

Page 247: ...tware Processing After Release of Reset 2 2 Checking reset cause Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage de...

Page 248: ...OP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF refer to CHAPTER 14 RESET FUNCTION 16 2 Confi...

Page 249: ...interrupt signal when supply voltage VDD detection voltage VLVI 1 Generate internal reset signal when supply voltage VDD detection voltage VLVI LVIF Note 4 Low voltage detection flag 0 Supply voltage...

Page 250: ...el Select Register LVIS Address FF51H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 Detection level 0 0 0 0 VLVI0 4 3 V 0 2 V 0 0 0 1 VLVI1 4...

Page 251: ...tion 4 Use software to instigate a wait of at least 0 2 ms 5 Wait until supply voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM is confirmed 6 Set bit 1 LVIMD of LVIM to 1 generates internal r...

Page 252: ...Cleared by software Not cleared Not cleared Not cleared Not cleared Cleared by software 2 1 3 5 6 Time Clear Clear Clear 4 0 2 ms or longer LVIMK flag set by software LVION flag set by software LVIMD...

Page 253: ...shows the timing of generating the interrupt signal of the low voltage detector Numbers 1 to 7 in this figure correspond to 1 to 7 above When stopping operation Either of the following procedures must...

Page 254: ...y reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action 1 below 2 When used...

Page 255: ...er TMIFH1 1 Interrupt request is generated Initialization of ports 8 bit timer H1 can operate with the low speed Ring OSC clock Source fRL 480 kHz MAX 27 compare value 200 53 ms fRL low speed Ring OSC...

Page 256: ...en used as interrupt Check that supply voltage VDD detection voltage VLVI in the servicing routine of the LVI interrupt by using bit 0 LVIF of the low voltage detection register LVIM Clear bit 1 LVIIF...

Page 257: ...eramic oscillation clock External clock input 2 Low speed Ring OSC clock oscillation Cannot be stopped Can be stopped by software 3 Control of RESET pin Used as RESET pin RESET pin is used as an input...

Page 258: ...1 OSCSEL0 Selection of system clock source 0 0 Crystal ceramic oscillation clock 0 1 External clock input 1 High speed Ring OSC clock Caution Because the X1 and X2 pins are also used as the P121 and P...

Page 259: ...27 ms 1 1 2 17 fx 13 1 ms Caution The setting of this option is valid only when the crystal ceramic oscillation clock is selected as the system clock source No wait time elapses if the high speed Rin...

Page 260: ...ious models For facilitating inventory management For updating software after shipment Caution For the electrical specifications related to the flash memory rewriting refer to CHAPTER 20 ELECTRICAL SP...

Page 261: ...s Block 1 256 bytes Block 2 256 bytes Block 3 256 bytes Block 4 256 bytes Block 5 256 bytes Block 6 256 bytes Block 7 256 bytes Block 0 256 bytes Block 1 256 bytes Block 2 256 bytes Block 3 256 bytes...

Page 262: ...it is assumed that the program is changed after production shipment of the target system Table 18 1 Rewrite Method Rewrite Method Functional Outline Operation Mode On board programming Flash memory c...

Page 263: ...y rewriting via on board off board programming Each security function can be used in combination with the others at the same time Table 18 3 Security Functions Rewriting Operation When Prohibited Exec...

Page 264: ...ring Between 78K0S KA1 and Dedicated Flash Programmer Pin Configuration of Dedicated Flash Programmer Pin Configuration of 78K0S KA1 Pin Name I O Pin Function Pin Name Pin No CLK Note Output Clock to...

Page 265: ...apter for flash memory writing are shown below Figure 18 2 Example of Wiring Adapter for Flash Memory Writing 18 17 16 20 19 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VDD2 VDD GND SI SO SCK CLK RESET VPP WR...

Page 266: ...that controls the dedicated flash programmer is necessary UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash programmer and the 78K0S KA1 To write...

Page 267: ...gnal collision takes place To prevent this collision isolate the connection with the reset signal generator If the reset signal is input from the user system while the flash memory programming mode is...

Page 268: ...ethod 18 8 1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory Figure 18 6 Flash Memory Manipulation Procedure Start Manipulate flash memory End Ye...

Page 269: ...YYY XXXXX XXXXXX XXXX XXXX YYYY STATVE The flash memory control commands of the 78K0S KA1 are listed in the table below All these commands are issued from the programmer and the 78K0S KA1 perform proc...

Page 270: ...gram making it possible to upgrade programs in the field Cautions 1 Self programming processing must have been implemented before performing self writing 2 Temporarily store the data to be rewritten i...

Page 271: ...pecification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either func...

Page 272: ...AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in pare...

Page 273: ...fr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte MOV HL byte A 2 6...

Page 274: ...A CY A HL ADD A HL byte 2 6 A CY A HL byte A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY A HL 1 6 A CY...

Page 275: ...byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL AND A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A...

Page 276: ...saddr saddr 1 INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 ROL A 1 1 2 CY A0 A7 Am 1 Am 1 RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 saddr bit 3 6...

Page 277: ...PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bi...

Page 278: ...1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD...

Page 279: ...SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1s...

Page 280: ...l instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ 5 Oth...

Page 281: ...put current high IOH Total of pins other than P20 to P23 30 mA Per pin 20 mA Output current low IOL Total of all pins 35 mA In normal operation mode 40 to 85 C Operating ambient temperature TA During...

Page 282: ...ernal clock X1 X1 input high low level width tXH tXL 2 0 V VDD 2 7 V 1 1 s Note Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using...

Page 283: ...IN TYP MAX Unit 2 7 V VDD 5 5 V 7 60 8 00 8 40 MHz On chip high speed Ring OSC Oscillation frequency fX 2 0 V VDD 2 7 V T B D MHz Low Speed Ring OSC Oscillator Characteristics TA 40 to 85 C VDD 2 0 to...

Page 284: ...3AVREF V Input voltage low VIL3 P121 P122 0 0 3VDD V Total of pins other than P20 to P23 IOH 15 mA 4 0 V VDD 5 5 V IOH 5 mA T B D V VOH1 IOH 100 A 2 0 V VDD 4 0 V VDD 0 5 V 4 5 V AVREF 5 5 V IOH 5 mA...

Page 285: ...nverter is stopped T B D T B D IDD3 High speed Ring OSC operation mode Note 6 fX 4 MHz VDD 2 7 V 10 Note 3 When A D converter is operating Note 7 T B D T B D mA When peripheral functions are stopped T...

Page 286: ...7 V VDD 4 0 V 0 5 4 s Cycle time minimum instruction execution time TCY High speed Ring OSC clock 2 0 V VDD 2 7 V 4 4 s 4 0 V VDD 5 5 V 2 fsam 0 1 Note s TI000 input high level width low level width...

Page 287: ...ation Clock External Clock Input 1 2 3 4 5 6 0 1 0 4 1 0 10 60 0 33 2 7 5 5 Guaranteed operation range Supply voltage VDD V Cycle time T CY s TCY vs VDD High speed Ring OSC Clock 1 2 3 4 5 6 0 1 1 0 1...

Page 288: ...ted baud rate generator output Parameter Symbol Conditions MIN TYP MAX Unit Transfer rate 312 5 kbps AC Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD 0 8VDD 0 2VDD Test points Clock Timing 1 fX...

Page 289: ...V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 0 4 FSR Full scale error Notes 1 2 Efs 2 7 V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 2 5 LSB Integral non linearity error Note 1 ILE 2 7 V AVREF 4 0 V 4 5 LSB 4 0...

Page 290: ...TH VDD 0 V 2 0 V 1 5 s Response delay time 1 Note tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note tPD When power supply falls 1 0 ms Minimum pulse...

Page 291: ...eration stabilization wait time Note 2 tWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or RESET output 2 Time required from setting LVION to 1 to operation stabilizat...

Page 292: ...TYP MAX Unit Chip unit teraca T B D T B D ms Erase time Note 1 Sector unit terasa T B D T B D ms Write time twrwa T B D T B D s Number of rewrites per chip Cerwr 1 erase 1 write after erase 1 rewrite...

Page 293: ...0 PIN PLASTIC SSOP 7 62 mm 300 A K D E F G H J P T MILLIMETERS 0 65 T P 0 475 MAX 0 13 0 5 6 1 0 2 0 10 6 65 0 15 0 17 0 03 0 1 0 05 0 24 1 3 0 1 8 1 0 2 1 2 0 08 0 07 1 0 0 2 3 5 3 0 25 0 6 0 15 U NO...

Page 294: ...ith PC98 NX series Unless stated otherwise products which are supported by IBM PC ATTM and compatibles can also be used with the PC98 NX series When using the PC98 NX series therefore refer to the exp...

Page 295: ...Emulation board Emulation probe Conversion socket or conversion adapter Target system Flash programmer Flash memory writing adapter Flash memory Power supply unit Software package Control software Pr...

Page 296: ...RA78K0S Program that converts program written in C language into object codes that can be executed by microcontroller Used in combination with assembler package RA78K0S and device file DF78K0S Kx1 bot...

Page 297: ...Software Project Manager This is control software designed so that the user program can be efficiently developed in the Windows environment With this software a series of user program development oper...

Page 298: ...ersonal computer incorporating the PCI bus is used as the host machine IE 789244 NS EM1 provisional name Note Emulation board Emulation board for emulating the peripheral hardware inherent to the devi...

Page 299: ...ing SM78K0S Kx1 provisional name the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can be enhanced and the softwar...

Page 300: ...gning a system Figure B 1 Connection Condition of Target In circuit emulator IE 78K0S NS or IE 78K0S NS A CN1 185 mm 45 mm 10 mm 43 mm 100 mm 30 mm Target system 15 mm 1 pin Emulation board IE 789244...

Page 301: ...A D converter mode register ADM 158 Analog input channel specify register ADS 160 Asynchronous serial interface operation mode register 6 ASIM6 180 Asynchronous serial interface reception error statu...

Page 302: ...0 188 Port mode register 12 PM12 56 Port register 2 P2 57 Port register 3 P3 57 Port register 4 P4 57 Port register 12 P12 57 Port register 13 P13 57 Preprocessor clock control register PPCC 65 Presca...

Page 303: ...8 bit timer H compare register 01 127 CMP11 8 bit timer H compare register 11 127 CR000 16 bit timer capture compare register 000 81 CR010 16 bit timer capture compare register 010 83 CR80 8 bit comp...

Page 304: ...register 65 PRM00 Prescaler mode register 00 88 PU2 Pull up resistance option register 2 60 PU3 Pull up resistance option register 3 60 PU4 Pull up resistance option register 4 60 PU12 Pull up resist...

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NEC 78K0S/KA1+, Preliminary User'S Manual

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