National Instruments cDAQ-9133, User Manual

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Chapter 2 Analog Input
• AI Reference Trigger Signal *
• AI Pause Trigger Signal *
Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, Digital
Input/Output and PFI , for more information.
Refer to the AI Convert Clock Signal Behavior For Analog Input Modules section for AI Convert
Clock signals and the cDAQ controller.
AI Sample Clock Signal
A sample consists of one reading from each channel in the AI task. Sample Clock signals the
start of a sample of all analog input channels in the task. Sample Clock can be generated from
external or internal sources as shown in Figure 2-1.
Figure 2-1. AI Sample Clock Timing Options
Routing the Sample Clock to an Output Terminal
You can route Sample Clock to any output PFI terminal. Sample Clock is an active high pulse
by default.
AI Sample Clock Timebase Signal
The AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock.
AI Sample Clock Timebase can be generated from external or internal sources. AI Sample Clock
Timebase is not available as an output from the controller.
AI Convert Clock Signal Behavior For Analog Input
Modules
Refer to the Scanned Modules , Simultaneous Sample-and-Hold Modules , Sigma-Delta Modules ,
and Slow Sample Rate Modules sections for information about the AI Convert Clock signal and
C Series analog input modules.
Progr a mm ab le
Clock
Divider
AI Sa mple Clock
Time bas e
PFI
An a log Comp a ri s on Event
Ctr n Intern a l O u tp u t
AI Sa mple Clock
S igm a -Delt a Mod u le Intern a l O u tp u t
An a log Comp a ri s on
Event
20 MHz Time bas e
8 0 MHz Time bas e
PFI
100 kHz Time bas e