AL3A-RM User Guide Version B
Document Number: 451-93156-002B
136 of 172
Table 5: Standard S-Registers
Register
Number
Range
Default Description
Sr=n Command
Write-Protected
in SAC0201
S36
0 – 255 7
Bitmap register where bits 0, 1, and 2
reflect the link type setting.
No action, compatibility only
Yes
S39
0 – 255 3
Bitmap register where bits 0, 1 and 2
reflect the &Kn setting.
Yes
S40
0 – 255 192
Bitmap register where bits 2, 3, and 4
reflect the \K setting, and bits 6 and 7
reflect the \An setting, bits 3-5 reflects the
\Kn setting.
No action, compatibility only
Yes
S41
0 – 255 3
Bitmap registers where bits 2 and 6 enable
retrain on bad signal quality setting, bit 4
reflects xon/xoff usage setting, and bit 5
reflects DTE auto rate adjustment setting.
No action, compatibility only
Yes
S95
0 – 255 0
Bitmap register for extended result codes
(overrides Wn setting).
0 = CONNECT shows DCE speed
2 = Enable CARRIER XXXX
3 = Enable PROTOCOL: XXXX
5
= Enable COMPRESSION: XXXX
