NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
53
11.3.26
External Reference Output Control Register
The value of the External Reference Output Control Register enables and configures the
external clock outpu.
Table 57:
EXT_REF_OUTP_CTL Register
External ReferenceOutput Control - Address 0x2E
Default value 0x00
Bit
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Func EN_OUTP
HIGH-
AMPL
-EXT_REF_OUT_MUX
Table 58:
EXT_REF_OUTP_CTL Register Bits
Bit
Name
Function
[5..0] EXT_REF_O
UT_MUX
These bits control the EXT_REF_OUT_MUX multiplexer.
The output of this multiplexer is driven out of the external
reference clock connector on the MCH face-plate.
0x01 – C19o
0x02 – #C16o
0x03 – C8/C32o
0x04 – #C4/C65o
0x05 – C2o
0x06 – C1.5o
0x07 – C3o
0x08 – C6/8.4/34/44o
0x09 – F16o
0x0B – PLL_REF0
0x0C – PLL_REF1
0x0D – EXTREF_IN
0x0E – TIC_100u
0x0F – RES (do not use!)
0x10 – RES (do not use!)
0x11 – SW_CLK
0x12 – SYNC_CLK
0x13 – 20MHz from Stratum 3 oscillator (only HW v2.3)
0x14 – Output of holdover function
0x21 – CLK2 of AMC1
0x22 – CLK2 of AMC2
:
0x2C – CLK2 of AMC12
0x2D – CLK1 Update (from 2
nd
MCH)
0x2E – CLK3 Update (from 2
nd
MCH)
