NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
45
11.3.19
PLL Control 1 Register
The PLL Control 1 Register manages together with the PLL_CTR2 Register the control
inputs of the Zarlink PLL.
Table 39:
PLL_CTR1 Register
PLL Control 1 - Address 0x12
Default value 0x00
Bit
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Func
OUT_SEL
2
OUT_SEL
1
OUT_SEL
0
MODE_
SEL1
MODE_
SEL0
REF_SEL1 REF_SEL0 PLL_RST
Table 40:
PLL_CTR1 – Register Bits
Bit
Name
Function
0
PLL_RST
Setting this bit to a logic high resets the PLL
[2..1] REF_SEL
Selects which Reference input is the active reference
of the PLL
0b00 – REF0 Reference as defined by
REF0_SEL Register
0b01 – REF1 Reference as defined by
REF1_SEL Register
0b10 – REF2 ( External reference CLK from face Plate
connector)
0b11 – REF2
[4..3] MODE_SEL
Selects the PLL MODE
00 – Normal Mode
01 – Holdover Mode
10 – Free running Mode
11 – Automatic (Normal with automatic Holdover and
automatic reference switching)
[7..5]
OUT_SEL
this bit selects the signals on the combined output clock
pins
OUTSEL2 : Generated outputs
0 : C2o, /C4o, C8o, /C16o
1 : C2o, /C16o, C32, C65o
OUTSEL[1..0]: Generated outputs
00 : C6o
01 : C8.4o
10 : C34o
