NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
19
8.2 Microprocessor
An Atmel 8-bit microprocessor resides on the
CLK Module
. With the help of this
microprocessor, the ColdFire of the base board can configure all multiplexers
implemented in the FPGA and enable the M-LVDS/HCSL transceivers for the
connection to each AMCs. The Atmel firmware can be updated by the ColdFire on the
Base Module
over the SPI interface. The ColdFire communicates with the
CLK
Module
via IPMI (using the I²C interface).
8.3 CLK-Multiplex Function
Flexible multiplexing of the various clock signals is achieved by an Altera Cyclone
FPGA. Multiplexing of source clock signals to destination clock signals is performed by
programming a register interface provided by the microcontroller.
The FPGA for these multiplexers is only assembled with the TC-option
8.4 M-LVDS / HCSL Transceiver
The MicroTCA R1.0 Specification recommends that all clock interfaces are equipped
with M-LVDS compliant driver/receiver and termination. Against that the AMC.0 R2.0
allows for FCLKA (formerly CLK3) also HCSL compliant driver/receiver and
termination.
The main difference between the two signal specifications, which makes it difficult to
realize both with the same hardware, is the different termination. M-LVDS uses a dual
differential termination between the two complimentary clock lines at both ends of the
bus. This termination is shown in Figure 3.
Figure 3: M-LVDS Termination
HCSL uses a source-only termination with two series and term-to-ground resistors. This
termination is depicted in Figure 4.
