NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
50
Table 52:
SYNC_CLK - Register Bits
Bit
Name
Function
[4..0] SYNC_CLK_
SEL
The Sync Clock Selection bits control the SYNC_CLK
multiplexer. The output of this multiplexer can be
selected as a source for the CLK1-3.
0x01 – C19o
0x02 – #C16o
0x03 – C8/C32o
0x04 – #C4/C65o
0x05 – C2o
0x06 – C1.5o
0x07 – C3o
0x08 – C6/8.4/34/44o
0x09 – F16o
0x0B – PLL_REF0
0x0C – PLL_REF1
0x0D – EXTREF_IN
0x0E – TIC_100u
0x0F – RES (do not use!)
0x10 – RES (do not use!)
0x11 – SW_CLK
all other values result in no connection
Note: The output of the SYNC_CLK multiplexer is low
until the SYNC_CLK_EN bit is set.
5
SW_CLK
The SW_CLK can be selected as source, to be
transmitted to the AMCs. The actual value of this bit is
then transmitted to the AMCs.
6 SYNC_CLK_
EN
A logic high in this bit enables the output of the
SYNC_CLK multiplexer.
7 -
no
function
write as 0 and ignore when read
