NAT-MCH Clock-PCB – Technical Reference Manual
Version 1.4
© N.A.T. GmbH
52
11.3.25
Holdover Function Control Register
The value of the Holdover Function Control Register controls the mode of the holdover
function.
Table 55:
H_OVER_FUNKT_CTL Register
Holdover Function Control - Address 0x2d
Default value 0x00
Bit
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Func H_OVER_MUX
HOLDOVER
MODE
Table 56:
H_OVER_FUNKT_CTL - Register Bits
Bit
Name
Function
[1..0] MODE
These bits control the functionality of the holdover
function.
00 = Holdover function in reset
01 = Automatic holdover/switch-back (Switches over to
internal generated 10MHz clock if reference fails.
Switches back to reference if reference is again valid.)
10 = Automatic holdover, no switch-back
11 = permanent connected to internal generated 10MHz
Clock
2 HOLDOVER
Shows the state of the holdover function.
0 – Holdover inactive (Clock selected by
H_OVER_MUX is used)
1 – Holdover active (internal generated 10MHz clock is
used)
[7..3] H_OVER_
MUX
Selects the input of the Holdover function
0x00 – external clock (from face plate)
0x01 – CLK2 of AMC1
0x02 – CLK2 of AMC2
:
0x0C – CLK2 of AMC12
0x0D – CLK1 Update (from 2
nd
MCH)
0x0E – CLK3 Update (from 2
nd
MCH)
0x11 – CLK1 of AMC1
0x12 – CLK1 of AMC2
:
0x1C – CLK1 of AMC12
all other values result in no connection
