A920:
Helen
Description
The Helen(adjunct processor) is a dual core processor architecture which incorporates a high-performane TI925T MPU core and a TI TMS320C55x DSP core. The fol-
lowing provides a brief description of the cores and associated peripherals being used in this design.
·Flash I/F, SDRAM I/F - Interfaces to FLASH and SDRAM
·Keypad Interface
·LCD I/F - Display Interface
·UART3 - IrDA interface
·MMC interface
·GPIO - For A/Ds
·Secondary SPI - PCAP interface
·Bluetooth Interface
·Camera IF - Backend Pixel Processor interface
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·I2C - Inter-Integrated Circuit Master and Slave interface
·IPCL - Inter-Processor Communications Link for Helen to POG interface
·ULPD - Ultralow-Power Device
·1 wire Communication for Battery EPROM
·USB(client) - Helen USB is used as a client, signals are routed through PCAP’s USB transceiver
·UART1 - RS232 interface to CE bus
·McBSP1 - Multichannel Buffered Serial Port (VSAP) for the PCAP stereo audio interface
·McBSP2 - Multichannel Buffered Serial Port (ASAP) for the PCAP and Bluetooth audio interface
Helen
1 Wire
Bus
RAM
1.5Mb
API
MMU
Bridge
McBSP2
(SAP)
HP0
HP2
HP1
USB
(host)
USB
(client)
Internal
XCVR
Single
Ended
Converter
C55x
DSP
icache
12KW
SRAM
48kW
DRAM
32kW
ARM925
icache
16KB
dcache
8KB
RTC
UART1
LCD
I/F
DMA
FLASH
256 Mbit
FLASH
I/F
SDRAM
I/F
uWIRE
GPIO
Keypad
Camera
IF
I
2
C
Backend
Pixel
Processor
32kHz
OSC
12MHz
OSC
UART2
McBSP3
McBSP1
MCSI2
MCSI1
MMC/SD
MMC
UART3
IrDA
Keypad
8x8
ULPD
12 MHz
SDRAM
256 Mbit
Display
Image
Sensor
PCAP
Codec
PCAP
Stereo
Codec
Battery
Bluetooth
POG
IPCL
PCAP
Secondary SPI
CE Bus
USB Client
Bluetooth
Audio