Motorola A920 Service Manual Download

Page: 56 / 131

A920:

MAGIC LV Control Functions

Description

The MAGIC LV contains 4 tracking regulators and one superfilter, which will generate the supplies for most of the IC as well as the front end and the main VCO. The
tracking regulators derive their internal power from the REG_REF pins. The reference voltages are filtered and buffered for use on the IC. The buffered voltages should
track the references /-1.5%. A raw supply voltage is provided to the tracking regulators which is higher than REG_REF as specified below for each regulator. A
superfilter is needed for the external VCO power supply. This superfilter, cascaded with an external regulator and any filtering in front of the IC, will need to provide
80dB of rejection to a 0.1V step occurring at a 217Hz rate with a risetime of 20us on the raw supply (battery) and a duty cycle of 0.125. The superfilter will use an inter-
nal pass transistor that is capable of driving a 30 mA load with a voltage drop of less than 0.4V relative to SF_SPLY from the SF_OUT pin. An external 1uf cap is
required on SF_OUT. As the superfilter will track SF_SPLY it will need to sense the power on reset and turn off even though its supply may remain active. All supplies
within the IC must be within 5% of their final values after 5msec from the start of POR_LB. The power on reset circuit contained within the crystal reference oscillator is
used to aid this functionality.

The MAGIC_LV has two sets of SPI interfaces; one set is for handling the control interface for the LIFE IC (AUXSPI lines) and ones for interfacing with POG (SPI
lines). AUX_SPI_DX is the serial data input line. AUX_SPI_CLK is the clock input line, where data shifting occurs at the rising edge of this signal. LIFE_CE is the
clock enable line, active high, for the LIFE IC.

MAGIC_LV will integrate a system of D/As and control logic to generate the power amplifier control ramps. In addition, MAGIC_LV will integrate the op-amps and
comparators which receive the detected output of the power amplifier and create the necessary control voltage to drive the power amplifier control port based on the con-
trol ramps. When TX_KEYM goes high, the ramp controller receives an positive input. This will cause the AOC_DRIVE pin to linearly rise which in turn will cause the
PA output power to rise. The rising PA output power will cause DET_AOC to begin to rise until the DC level on DET_AOC exceeds the DC level on DET_REF by the
intentional offset of the RF detector versus it‘s reference. At this point the “Active Detect” comparator will go low and break the input voltage to the integrator with the
ramp controller. This will cause the PA power to stop rising and hold the present power level as determined by the 8 bit offset value fed to the ramp controller. The PA
control loop is now at a minimal power needed to keep the control system in a closed loop for a controlled ramp up of the power.

The MAGIC uses two SPI driven GPO lines which are used to control the operating bands of the GSM RF circuits. They are N_BAND_0 and N_BAND_1.

When the MAGIC LV is set to battery save mode it will shutdown the receiver analog sectioins (via RX_EN_LIFE), the AOC, the main synthesizer and the superfilter.

Motor

Conf

ide
n

tia
l Pr

opr
ie