A920:
MAGIC LV (Synthesizers/Transmitter)
Description
The MAGIC_LV receives SSI Tx data at DMCS (digital input to start Tx modulation), TXCLK (clock for serial transfer) and SDTX ( serial Tx data) from POG. The
present serial data bit and the three previous data bits are used to set up one of 16 possible waveforms based on the sum of Gaussian pulses stored in a look up ROM.
The resulting signal will then be clocked out at a 16x over-sampling rate. This data pattern input to three-accumumalator fractional N synthesizer with a 24-bit resolu-
tion. The VCO control lines must have compliance over an output voltage range of 0.3VDC to Vcc-0.3V. The charge pumps will have their own supply pin. The voltage
on this pin is expected to be 2.775V typically to obtain sufficient compliance. This will drive external loop filters, which will in turn drive external VCOs. A dual port
modulation mode is obtained with a 9 bit D/A which follows the modulation look up table output waveform is output on the GPO3 pin.This signal is then coupled into
the loop filter to add in the higher frequency components of the modulation which may have been attenuated in the main PLL path. This will allow the use of a lower
bandwidth main PLL to improve the spectral purity of the transmit signal.For EGSM the synthesizer output is 880 - 915MHz, DCS is 1710 - 1785MHz with GMSK mod-
ulation and is directly amplified to the transmitter output.
The prescaler for the main LO is able to accept input frequencies as high as 2.0GHz. The level of this signal shall be between -20dbm and -10dbm. There are two
prescaler inputs to this point each has a 100W resistor in series between the pin and the actual prescaler input.
The reference oscillator is a free running 26MHz crystal. AFC is provided through the SPI bus as a programming offset to the fractional N division system. Since the
26MHz crystal is not locked to the AFC, a second fractional divider system is necessary to derive an accurate 200KHz system reference. This reference is then multiplied
in a PLL to 13MHz for use as an accurate clock to the logic sections of the transceiver.
Motor
o
la
Conf
ide
n
tia
l Pr
opr
ie
ta
ry
4-
10
Ø
PLL_CP
3 Acc
FN Seq
Gen
Σ
BB_CLK_13M
CLK_SEL
FL510
Ø
CP_TX
PRSC
TX Data
Interface
GSM
Look-up
Table
GSM
Pre-Distort
Σ
3 Acc
FN Seq
Gen
RX_VCO
TX_VCO_PRSC
TXCLK
DMCS_MAGIC
SDTX
BFSX
AMPS
Interpolator
RX_VTUNE
POG
Y500
MAGIC LV
U500
(Synthesizer Section)
Mod_sel
LIFE
TX
VCO
