3 – Key Components Description and Operation
18
IGLOO2 FPGA Evaluation Kit User Guide
USB Interface
The SMSC USB3320 is a high speed USB 2.0 ULPI transceiver. It includes full support for the optional OTG protocol.
CPEN: External 5 V supply enables. It controls the external VBUS power switch.
IGLOO2
FPGA
USB- PHY
USB3320
Control lines
DATA[7:0]
Micro-AB
USB
Connector
ID
DM
DP
VBUS
ESD
Diodes
Jumper
MAX1823B
5P0V
CPEN
Bank2
26 MHz
REFCLK
XO
P1
J24
U19
U20
VBUS
VBUS
2.2uF
1K
OTG
Capable
Figure 9.
USB Interface
Note:
For more information, refer to page 10 of Board Level Schematics document (provided separately).
Marvell PHY (88E1340S)
The IGLOO2 Evaluation Kit utilizes the on board Marvell Alaska PHY device (88E1340S) for Ethernet
communications at 100 or 1000 Mbps. 88E1340S has four independent Gigabit Ethernet transceivers, but the board
uses only one transceiver. Each transceiver performs all the physical layer functions for 100BASE-TX and
1000BASE-T full or half duplex Ethernet on CAT5 twisted pair cable. The PHY connection to a user-provided
Ethernet cable is through an RJ-45 connector with built-in magnetics.
The 88E1340S device supports the quad SGMII for direct connection to an IGLOO2 chip. Refer to
Figure 10
.
The 88E1340S is configured through the CONFIG [3:0] pins and CLK_SEL [1:0].
CLK_SEL [1:0] is used to select the reference clock input option. On board, the status of CLK_SEL0 is High and
CLK_SEL1 is Low. REF_CLK is the 125 MHz reference differential clock input. It consists of LVDS differential inputs
with a 100Ω differential internal termination resistor.
•
RCLK – Gigabit recovered clock
•
SCLK – 25 MHz synchronous input reference clock
•
Expected reference clock (REF_CLK) specifications
Voltage level: 3.3 (± 0.3)V
Differential LVDS
Symmetry: 50% (± 10%)
Rise/Fall Time: 1nsec Max @ 20% to 80% of supply (3.3 V)
Output Voltage Levels: “0”=0.90 Minimum, 1.10 Typical
“1”=1.43 Typical, 1.60 Maximum
Differential Output Voltage: 247 mV Minimum, 454 mV Maximum
