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7 – Manufacturing Test

IGLOO2 FPGA Evaluation Kit User Guide

55

Figure 33.

Enabling PRBS Pattern Generation

Once the PRBS GEN+CHECKER is enabled, observe the PRBS error count for Lane 1. It should be 0.
0 on PRBS error count shows that the internal loopback test is successful for SERDES Lane 1. Value
otherthan 0 indicated that the external loopback test is not successful and it has the number of errors it
shown.

3. Close

SERDES TEST APP

window once the test is completed.

LPDDR and SPI Test

Use the following procedure to initiate LPDDR and SPI tests on IGLOO2 Evaluation Kit:

1. Connect USB cable (mini USB to Type A USB cable) to J18 and other end of the cable to the USB port

of test PC. This is required for SERDES GUI UART communication.

2. Switch

ON

the SW7 power supply switch.

3. Make sure that the board is programmed with IGLOO2_MTD_top.stp file.

4. Double-click the MTD_TESTER.exe file to open the MTD TESTER to test the Evaluation Kit board.

Figure 34

shows the MTD TESTER window.

Figure 34.

MTD TESTER Window

5. Click the

port settings

tab in the

MTD TESTER

window.

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Summary of Contents for IGLOO2 FPGA DSP FIR Filter

Page 1: ...IGLOO2 FPGA Evaluation Kit User Guide ...

Page 2: ......

Page 3: ...Components Description and Operation 13 Powering Up the Board 13 Current Measurement 13 Memory Interface 15 SERDES0 Interface 16 USB Interface 18 Marvell PHY 88E1340S 18 Programming 20 FTDI Interface 20 I2C Port Header 21 System Reset 22 Clock Oscillator 22 Debugging 23 GPIO Header Pin Out 25 4 Pin List 27 5 Board Components Placement 41 6 Demo Design 45 M2GL EVAL KIT Board Demo Design 45 7 Manufa...

Page 4: ...GLOO2 FPGA Evaluation Kit User Guide Product Support 61 Customer Service 61 Customer Technical Support Center 61 Technical Support 61 Website 61 Contacting the Customer Technical Support Center 61 ITAR Technical Support 62 ...

Page 5: ...pga soc design resources dev kits igloo2 igloo2 evaluation kit overview Board Description The IGLOO2 Evaluation Kit offers a full featured Evaluation Board for IGLOO2 FPGAs This kit inherently integrates the following on a single chip Reliable flash based FPGA fabric Advanced security processing accelerators Digital signal processing DSP blocks Static random access memory SRAM Embedded nonvolatile...

Page 6: ...Bank1 SGMII MSIO Bank7 SERDES0 SPI flash W25Q64FV SSIG LPDDR MT46H32M16LF 8 Meg x 16 x 4 banks MDDR Bank0 JTAG Bank4 SC_SPI ETM Bank1 MDIO Bank7 Debug Switches 4 Bank2 MSIO Bank4 MSIO Bank1 U15 J4 J5 J9 J1 P1 REFCLK0 Lane 1 Lane 2 SMA Connectors REFCLK1 JTAG PHY 23 pin header Debug LEDs 8 Bank7 On Board Oscillator 125MHz SMA Connectors Mux Figure 1 IGLOO2 FPGA Evaluation Kit Block Diagram Board Ov...

Page 7: ...I mode interfacing with the Ethernet port of the IGLOO2 FPGA on chip MAC and external PHY RVI header RVI header for application programming and debugging from Keil ULINK or IAR J Link FP4 header FlashPro4 programming header for IGLOO2 programming and debugging with Microsemi tools Future Technology Devices International FTDI programmer FTDI programmer interface J18 to program the external SPI flas...

Page 8: ... FPGA Evaluation Kit User Guide Name Description USB3320 interfacing with FPGA pins of the IGLOO2 HPMS OSC 125 125 MHz clock oscillator differential output OSC 50 50 MHz clock oscillator OSC 32 32 768 KHz low power oscillator ...

Page 9: ...to enable the pre programmed demonstration design to function correctly Table 4 shows the jumpers along with default settings Note Location of all the jumpers and test points are searchable in Figure 17 page 42 of 5 Board Components Placement section Table 4 Jumper Settings Jumper Function Default Settings J23 Jumper to select switch side Mux inputs of A or B to the line side Pin 1 2 Input A to th...

Page 10: ...f Marvell PHY DS4 Green Connected to parallel LED output port 0 P0_LED 2 of Marvell PHY DS6 Green Connected to parallel LED output port 0 P0_LED 3 of Marvell PHY Table 6 lists the USB ground and other test points Table 6 Test Points Test Point Description TP8 USB switch in out for DP signal TP9 USB switch in out for DM signal TP1 TP2 TP4 TP5 TP6 TP7 TP10 TP11 GND TP3 Test point for DDR_VTT TP12 Te...

Page 11: ...3V VDDI 5 6 2P5V 1P0V_PHY LX7167 LX13043 TPS51200 LX8240 LPDDR VREF0 VDDI 0 PHY_1P8V 1P8V 0 9V for LPDDR DDR_VTT VPP PLL Supply 3P3V_LDO VDDAPLL 2P5V_LDO SERDES_0_Lxy_VDDAPLL SERDES_0_Lxy_REFRET SERDES_0_PLL_VDDA SERDES_0_PLL_VSSA IGLOO2 Figure 3 Voltage Rails in the IGLOO2 FPGA Evaluation Kit Testing the Hardware If the board is shipped directly from Microsemi it contains a test program that dete...

Page 12: ......

Page 13: ...k as Diode D3 becomes reverse biased and path will be open for 12P0_PCIE When the external DC voltage is not present the board can be powered up using the PCIe connector 12P0V_IN 12P0V PCIe CON1 12 V DC Jack ENABLE_FT4232 2 5 1 3 4 6 SW7 J3 J6 Figure 4 Powering Up the Board Current Measurement 1 2 V Current Sensing for Normal Operation For applications which require current measurement high precis...

Page 14: ...To convert the voltage measured across sense resistor to power use the following equation 𝑃𝑜𝑤𝑒𝑟 voltage_measured_in_milli_volts 0 05 1 2 1 8 V Current Sensing For applications which require current measurement high precision Operational Amplifier circuitry U32 with gain 100 is placed on the board to measure the output voltage at TP15 test point with reference to the ground 1 8 V power can be measu...

Page 15: ...ns of LPDDR SDRAM are listed below MT46H32M16LF 8 Meg x 16 x 4 banks Density 512 Mb Data rate LPDDR 16 bit at 400 Mbps 6 4 Gbps Note For more information refer to page 3 of Board Level Schematics document provided separately SPI Serial Flash The specifications of SPI Flash are listed below Density 64 Mb Voltage 2 7 V 3 6 V Frequency 104 MHz Supports SPI modes 0 and 3 IGLOO2 HPMS SPI0 interfaced to...

Page 16: ...ttom layer trace via to top layer SMA connector Pad 4 Lane3 is routed to Marvell PHY 88E1340S TX pad trace AC Coupling trace via trace routed in 6th layer via to top layer Marvel PHY pin RX pad via trace routed in 6th layer via to top layer trace AC Coupling trace Marvel PHY pin SERDES0 reference clock 0 is routed directly from the PCIe connector to IGLOO2 FPGA SERDES0 reference clock 1 is routed ...

Page 17: ...Lane3 SMA O P Sel MUX Sel J23 J22 3 3 V Figure 8 SERDES0 Interface For more information on J22 and J23 jumpers refer to Table 4 Note SERDES0 TXD pairs are capacitively coupled to the IGLOO2 device Series AC coupling capacitors are used to provide Common mode voltage independence The AC coupling capacitors are not provided for SERDES 0 RXD signals The mating board should have the AC coupling capaci...

Page 18: ...ransceiver performs all the physical layer functions for 100BASE TX and 1000BASE T full or half duplex Ethernet on CAT5 twisted pair cable The PHY connection to a user provided Ethernet cable is through an RJ 45 connector with built in magnetics The 88E1340S device supports the quad SGMII for direct connection to an IGLOO2 chip Refer to Figure 10 The 88E1340S is configured through the CONFIG 3 0 p...

Page 19: ...ll PHY 88E1340S 1588 REFCLK 25 MHz JTAG J13 U14 RCLK1 Clocks SCLK REF_CLKP REF_CLKN XTAL_IN XTAL_OUT RCLK2 Differential Clocks MDC MDIO INT PHY_RST On Board Oscillator 125MHz Mux SMA Connectors 1588 REFCLK G1 H1 Bank7 Figure 10 IGLOO2 Marvell PHY Interface Note For more information refer to page 11 and 12 of Board Level Schematics document provided separately ...

Page 20: ...LINK debugger or IAR J Link debugger FlashPro4 Programming Header The IGLOO2 device on the Evaluation Kit can be programmed using a FlashPro4 programmer In addition FlashPro4 is used for software debugging by SoftConsole Note For more information refer to page 13 of Board Level Schematics document provided separately For more details refer to the IGLOO2 Programming User Guide FTDI Interface FT4232...

Page 21: ..._SPI Figure 12 FTDI Interface Note For more information refer to page 14 of Board Level Schematics document provided separately I2C Port Header Table 7 shows the two I2C ports routed to header H1 Table 7 I2C Port Header Pin Number IGLOO2 Pin Name Board Signal Name Header H1 G16 MSIO28NB1 I2C0_SCL 10 14 G17 MSIO28PB1 I2C0_SDA 11 15 R22 MSIO11NB2 CCC_NE0_CLKI2 I2C1_SCL 2 6 P22 MSIO11PB2 CCC_NE0_CLKI...

Page 22: ...nformation refer to page 13 of Board Level Schematics document provided separately Clock Oscillator 50 MHz Clock Source Figure 14 shows the 50 MHz clock oscillator with 50 ppm is available on the board This clock oscillator is connected to the FPGA fabric to provide a system reference clock An on chip IGLOO2 PLL can be configured to generate a wide range of high precision clock frequencies Table 8...

Page 23: ...OO2 Dev Kit IGLOO2 Pkg No IGLOO2 Pin Name LED0 Yellow E1 MSIO73PB7 LED1 Yellow F4 MSIO74NB7 LED2 Green F3 MSIO74PB7 LED3 Green G7 MSIO75NB7 LED4 Red H7 MSIO75PB7 LED5 Red J6 MSIO76NB7 LED6 Blue H6 MSIO76PB7 LED7 Blue H5 MSIO77NB7 IGLOO2 FPGA 499 ohms 3 3V Figure 15 LEDs Interface Note For more information refer to page 15 of Board Level Schematics document provided separately Push Button Switches ...

Page 24: ... page 15 of Board Level Schematics document provided separately Slide Switches DPDT SW7 Power ON OFF switch from external DC Jack 12 V DC DIP Switch SPST SW5 is a DIP switch that has four connections to the IGLOO2 device Table 10 lists the onboard DIP switches Table 11 DIP Switches IGLOO2 Dev Kit IGLOO2 Pkg No IGLOO2 Pin Name DIP1 L19 MSIO16PB2 DIP2 L18 MSIO16NB2 DIP3 K21 MSIO17PB2 DIP4 K20 MSIO17...

Page 25: ... Table 12 GPIO Header Pin Out GPIO Header J1 IGLOO2 U1 GPIO Header J1 IGLOO2 U1 Pin No Pkg No Pin Name Pin No Pkg No Pin Name 1 AB15 MSIO110PB4 2 3P3V 3 AA15 MSIO110NB4 4 VSS 5 VSS 6 AA16 MSIO114PB4 7 AB18 MSIO118PB4 8 AA17 MSIO114NB4 9 AB19 MSIO118NB4 10 VSS 11 VSS 12 AB17 MSIO113PB4 13 Y18 MSIO117PB4 14 AA18 MSIO113NB4 15 Y19 MSIO117NB4 16 VSS 17 VSS 18 Y17 MSIO116PB4 19 W16 MSIO115PB4 20 W17 MS...

Page 26: ...Pkg No Pin Name 37 F5 MSIO67PB7 38 G6 MSIO66NB7 39 F6 MSIO67NB7 40 VSS 41 VSS 42 E4 MSIO70PB7 43 C4 MSIO64PB7 44 E5 MSIO70NB7 45 D5 MSIO64NB7 46 VSS 47 VSS 48 C3 MSIO65PB7 49 B2 MSIO69PB7 50 B3 MSIO65NB7 51 A2 MSIO69NB7 52 VSS 53 VSS 54 C1 MSIO71PB7 55 D1 MSIO72PB7 56 B1 MSIO71NB7 57 D2 MSIO72NB7 58 VSS 59 VSS 60 D3 MSIO68PB7 61 3P3V 62 D4 MSIO68NB7 63 3P3V 64 VSS ...

Page 27: ...DDRIO48PB0 MDDR_DQ8 A13 DDRIO48NB0 MDDR_DQ9 A14 DDRIO44PB0 MDDR_DQ12 A15 DDRIO44NB0 MDDR_DQ13 A16 DDRIO39PB0 MDDR_CLK A17 DDRIO39NB0 MDDR_CLK_N A18 DDRIO38PB0 MDDR_BA0 A19 DDRIO38NB0 MDDR_BA1 A2 MSIO69NB7 A20 DDRIO34NB0 MDDR_ADDR6 A21 DDRIO31PB0 MDDR_ADDR10 A22 VSS A3 DDRIO63NB0 A4 DDRIO63PB0 A5 DDRIO62NB0 A6 DDRIO59NB0 GB4 A7 DDRIO56PB0 MDDR_DQ_ECC1 A8 DDRIO56NB0 MDDR_DQ_ECC0 A9 DDRIO54NB0 MDDR_D...

Page 28: ...SS AA6 SERDES_0_TXD2_N AA7 VSS AA8 SERDES_0_TXD3_N AA9 VSS AB1 VSS AB10 NC AB11 NC AB12 VDDI4 AB13 MSIO105PB4 CCC_NE0_CLKI0 AB14 MSIO105NB4 AB15 MSIO110PB4 AB16 VSS AB17 MSIO113PB4 AB18 MSIO118PB4 AB19 MSIO118NB4 AB2 SERDES_0_TXD0_P AB20 VDD AB21 XTLOSC_MAIN_XTAL AB22 VSS AB3 VSS AB4 SERDES_0_TXD1_P AB5 VSS AB6 SERDES_0_TXD2_P AB7 VSS AB8 SERDES_0_TXD3_P AB9 VSS B1 MSIO71NB7 B10 VSS B11 DDRIO52PB0...

Page 29: ...O65NB7 B4 VSS B5 DDRIO62PB0 B6 DDRIO59PB0 GB0 B7 DDRIO58NB0 MDDR_DQS_ECC_N B8 VDDI0 B9 DDRIO54PB0 MDDR_DQ0 C1 MSIO71PB7 C10 VDDI0 C11 DDRIO52NB0 MDDR_DQS0_N C12 VSS C13 DDRIO46NB0 MDDR_DQS1_N C14 VDDI0 C15 DDRIO41NB0 MDDR_CS_N C16 DDRIO37PB0 MDDR_BA2 C17 DDRIO35PB0 MDDR_ADDR3 C18 DDRIO35NB0 MDDR_ADDR4 C19 DDRIO33NB0 MDDR_ADDR7 C2 VDDI7 C20 DDRIO33PB0 MDDR_ODT C21 VSS C22 MSIO27PB1 C3 MSIO65PB7 C4 ...

Page 30: ...DR13 D21 MSI26NB1 D22 FLASH_GOLDEN_N D3 MSIO68PB7 D4 MSIO68NB7 D5 MSIO64NB7 D6 DDRIO61NB0 D7 MDDR_IMP_CALIB_ECC D8 DDRIO57NB0 MDDR_DM_RDQS_ECC D9 DDRIO55PB0 CCC_NE0_CLKI3 E1 MSIO73PB7 E10 DDRIO53NB0 MDDR_DQ3 E11 VDDI0 E12 DDRIO49PB0 MDDR_DQ7 E13 DDRIO43NB0 MDDR_DQ15 E14 VSS E15 DDRIO40PB0 MDDR_RESET_N E16 DDRIO36NB0 MDDR_ADDR2 E17 DDRIO32PB0 MDDR_ADDR8 E18 DDRIO29NB0 MDDR_ADDR15 E19 DDRIO30PB0 MDD...

Page 31: ...O40NB0 MDDR_CAS_N F16 VSS F17 DDRIO32NB0 MDDR_ADDR9 F18 MSIO24NB1 F19 MSIO24PB1 F2 NC F20 MSIO23NB1 F21 MSIO23PB1 F22 VDDI1 F3 MSIO74PB7 F4 MSIO74NB7 F5 MSIO67PB7 F6 MSIO67NB7 F7 VDDI0 F8 DDRIO60NB0 CCC_NE1_CLKI3 F9 VDDI0 G1 MSIO78NB7 G10 VREF0 G11 VREF0 G12 DDRIO45PB0 MDDR_TMATCH_0_IN G13 DDRIO45NB0 MDDR_DM_RDQS1 G14 DDRIO42NB0 MDDR_WE_N G15 VREF0 G16 MSIO28NB1 G17 MSIO28PB1 G18 MSIO22NB1 G19 MSI...

Page 32: ... VDDI0 H13 VSS H14 VDDI0 H15 CCC_NE0_PLL_VDDA H16 MDDR_PLL_VDDA H17 MDDR_PLL_VSSA H18 VDDI1 H19 MSIO21NB1 H2 VSS H20 MSIO21PB1 GB5 H21 NC H22 NC H3 NC H4 MSIO77PB7 H5 MSIO77NB7 H6 MSIO76PB7 H7 MSIO75PB7 H8 NC H9 VSS J1 MSIO80PB7 J10 VSS J11 VDD J12 VSS J13 VDD J14 VSS J15 CCC_NE0_PLL_VSSA J16 CCC_NE1_PLL_VSSA J17 CCC_NE1_PLL_VDDA J18 MSIO20NB2 J19 NC J2 MSIO80NB7 J20 NC J21 VDDI1 ...

Page 33: ...D K1 MSIOD85PB6 CCC_NE1_CLKI1 K10 VDD K11 VSS K12 VDD K13 VSS K14 VDD K15 MSIO18NB2 K16 MSIO19NB2 K17 MSIO19PB2 K18 MSIO20PB2 K19 VSS K2 MSIOD85NB6 K20 MSIO17NB2 K21 MSIO17PB2 K22 NC K3 VDDI6 K4 MSIOD82PB6 K5 MSIOD82NB6 K6 MSIO81PB7 K7 MSIO81NB7 K8 MSIOD83PB6 K9 VSS L1 VSS L10 VSS L11 VDD L12 VSS L13 VDD L14 VSS L15 VPP L16 MSIO18PB2 L17 VDDI2 L18 MSIO16NB2 L19 MSIO16PB2 ...

Page 34: ... MSIOD87NB6 L6 VDDI6 L7 MSIOD84NB6 L8 MSIOD83NB6 L9 VDD M1 MSIOD92NB6 M10 VDD M11 VSS M12 VDD M13 VSS M14 VDD M15 VPPNVM M16 NC M17 NC M18 NC M19 NC M2 MSIOD90NB6 M20 VDDI2 M21 MSIO14PB2 M22 MSIO14NB2 M3 MSIOD90PB6 M4 VSS M5 MSIOD88PB6 M6 MSIOD88NB6 M7 MSIOD84PB6 CCC_NE1_CLKI2 M8 MSIOD95NB6 M9 VSS N1 MSIOD92PB6 N10 VSS N11 VDD N12 VSS N13 VDD N14 VSS N15 VSSNVM N16 MSIO8PB2 ...

Page 35: ...2 SPI_0_SS0 N3 MSIOD91PB6 N4 MSIOD91NB6 N5 MSIOD89PB6 N6 MSIOD89NB6 N7 VSS N8 MSIOD95PB6 N9 VDD P1 MSIOD94PB6 P10 VDD P11 VSS P12 VDD P13 VSS P14 VDD P15 VPP P16 MSIO7NB2 P17 MSIO6PB2 P18 MSIO6NB2 P19 SC_SPI_SDO P2 MSIOD94NB6 P20 SC_SPI_SS P21 VSS P22 MSIO11PB2 CCC_NE0_CLKI1 P3 MSIOD93NB6 P4 MSIOD93PB6 P5 VDDI6 P6 MSIOD96PB6 P7 MSIOD96NB6 P8 SERDES_0_VDD P9 VSS R1 MSIOD97NB6 R10 VSS R11 VDD R12 VS...

Page 36: ...11NB2 CCC_NE0_CLKI2 R3 MSIOD98PB6 R4 MSIOD98NB6 R5 VSS R6 NC R7 NC R8 SERDES_0_L01_VDDAIO R9 VSS T1 MSIOD100NB5 SERDES_0_REFCLK0_N T10 SERDES_0_L23_VDDAIO T11 NC T12 NC T13 MSIO107NB4 T14 VDDI4 T15 VSS T16 NC T17 VSS T18 MSIO2PB2 T19 MSIO2NB2 T2 VSS T20 MSIO5PB2 T21 MSIO5NB2 T22 VDDI2 T3 MSIOD99NB6 T4 MSIOD99PB6 T5 NC T6 SERDES_0_PLL_VSSA T7 NC T8 SERDES_0_PLL_VDDA T9 SERDES_0_VDD U1 MSIOD100PB5 S...

Page 37: ... U20 VSS U21 MSIO4NB2 U22 MSIO4PB2 U3 MSIOD101PB5 SERDES_0_REFCLK1_P U4 MSIOD101NB5 SERDES_0_REFCLK1_N U5 SERDES_0_L01_REXT U6 SERDES_0_L01_REFRET U7 SERDES_0_L01_VDDAPLL U8 SERDES_0_L23_VDDAPLL U9 VPP V1 VSS V10 VDDI4 V11 MSIO104PB4 GB3 V12 NC V13 MSIO108PB4 V14 MSIO108NB4 V15 VSS V16 MSIO115NB4 V17 NC V18 NC V19 MSIO0NB2 V2 VSS V20 JTAG_TMS V21 MSIO3NB2 V22 MSIO3PB2 V3 VSS V4 VSS V5 VSS V6 VSS V...

Page 38: ...SIO109NB4 W15 MSIO111NB4 W16 MSIO115PB4 W17 MSIO116NB4 W18 VSS W19 NC W2 VSS W20 JTAG_TCK W21 VDDI3 W22 JTAG_TDI W3 SERDES_0_RXD1_P W4 VSS W5 SERDES_0_RXD2_P W6 VSS W7 SERDES_0_RXD3_P W8 VSS W9 MSIO102PB4 Y1 SERDES_0_RXD0_N Y10 MSIO103NB4 PROBE_B Y11 VSS Y12 NC Y13 MSIO106NB4 Y14 MSIO109PB4 Y15 MSIO111PB4 Y16 VDDI4 Y17 MSIO116PB4 Y18 MSIO117PB4 Y19 MSIO117NB4 Y2 VSS Y20 NC Y21 JTAG_TDO Y22 JTAG_TR...

Page 39: ...4 Pin List IGLOO2 FPGA Evaluation Kit User Guide 39 PKG PIN M2GL010TS M2GL010T FG484 Pin Name Y4 VSS Y5 SERDES_0_RXD2_N Y6 VSS Y7 SERDES_0_RXD3_N Y8 VSS Y9 MSIO102NB4 CCC_NE1_CLKI0 ...

Page 40: ......

Page 41: ...IGLOO2 FPGA Evaluation Kit User Guide 41 5 Board Components Placement The IGLOO2 Evaluation Kit components placement on top and bottom sides are shown in the following figures ...

Page 42: ...0 G 1 A 9 10 A4 G 3 GND 4 3 4 B B1 1P8V_CUR_SENSE 2 A A1 1 2 1 GND 2 13 1 K16 1 1 2 1P8V 16 4 19 20 G 1 A 20 D7 D6 D5 40 G D4 D3 G H5 H6 J6 C7 D2 15 30 3 4 1 2 H7 G7 C5 C6 G 1 A 1 60 A 1 G 1 G A1 A 1 GND 50 17 20 2 L20 1 2 1 1 3 G 1 5 5 1 3 2 1 1 3 1 1 4 3 4 TXD2N I2C0_SDA I2C1_SDA TXD2P L2 RXD2N RXD2P I2C1_SCL Trace DBG USB FTDI 12V I P ETH PHY SGMII 12V 3 3V 5V ON SWT RMT SERDES_REFCLK1N SERDES_...

Page 43: ...4 C202 R234 C327 C312 C321 C201 C200 C165 C174 C166 R199 C131 C133 C134 C130 R163 C126 R233 C328 C316 C289 C264 C238 C213 C205 C196 C199 R191 R196 R197 R186 R187 R177 R176 C314 R229 R227 C285 R218 C232 C208 C214 C219 R183 R192 R189 R181 C141 C143 C148 R164 R168 R165 R178 R171 C139 C135 C137 C132 R185 R184 R174 R175 C297 C243 C271 C207 C223 C197 C304 C307 C300 C286 C273 C268 C255 R215 C240 C248 C21...

Page 44: ......

Page 45: ... demo design This demo design demonstrates key features of IGLOO2 device such as PCIe GPIOs and fabric interface controller of the IGLOO2 device These features can be used for rapid prototyping and validation of user specific designs Note For more details on running the demo designs refer to the IGLOO2 FPGA Evaluation Kit PCIe Demo Guide to be released ...

Page 46: ......

Page 47: ...w microsemi com soc download rsc f IGLOO2_EVAL_KIT_MTD Download and install the drivers from http www ftdichip com Drivers D2XX htm Loopback Test on SERDES Lanes Table 14 show the list of tests performed on the four SERDES lanes in EPCS mode Table 14 SERDES Lanes Loopback Tests Lane Tests Performed Lane 0 Internal loopback Lane 1 Internal and external loopback Lane 2 Internal loopback Lane 3 Inter...

Page 48: ...7 Manufacturing Test 48 IGLOO2 FPGA Evaluation Kit User Guide Figure 20 SERDES TEST APP Window 5 Click the port settings tab on the SERDES TEST APP window Figure 21 shows the port settings tab ...

Page 49: ... Manufacturing Test IGLOO2 FPGA Evaluation Kit User Guide 49 Figure 21 Port Settings Tab 6 Select the highest COM port from the drop down list and click Open to establish the connection with the test PC ...

Page 50: ...7 Manufacturing Test 50 IGLOO2 FPGA Evaluation Kit User Guide Figure 22 Selecting the COM Port 7 Click the serdes analyzer tab to verify the connection ...

Page 51: ...ES Analyzer Tab Make sure that Communication Status indicator is in green If the UART communication is not set up properly Communication Status indicator will be in red Note If the Core Reset status indicator is shown in green click Deassert Core Reset to disable the core reset ...

Page 52: ...s lane0 from the Register Space drop down list Figure 25 Selecting Register Space 9 Click Enable Near TX to RX loopback to enable the internal near end loopback on SERDES Lane 0 Figure 26 Enabling Internal Loopback Figure 27 shows Near lpbk status indicator in green after clicking Enable Near TX to RX loopback ...

Page 53: ...ation Once the PRBS GEN CHECKER is enabled observe the PRBS error count for Lane0 It should be 0 0 on PRBS error count shows that the internal loopback test is successful for SERDES lane 0 Value otherthan 0 indicated that the internal loopback test is not successful and it has the number of errors it shown 11 Click Disable PRBS Gen checker to stop the packet transmission and click Disable Near TX ...

Page 54: ...ne 3 by selecting the Lane from Register Space drop down list External Loopback on SERDES Lane1 External loopback can be performed on SERDES Lane 1 only 1 Select serdes lane1 from the Register Space drop down list Figure 31 Selecting SERDES Lane 1 2 Click Enable PRBS Gen checker to check the error count Figure 32 Enabling PRBS Genarator Figure 33 shows PRBS gen status indicator in green after clic...

Page 55: ... APP window once the test is completed LPDDR and SPI Test Use the following procedure to initiate LPDDR and SPI tests on IGLOO2 Evaluation Kit 1 Connect USB cable mini USB to Type A USB cable to J18 and other end of the cable to the USB port of test PC This is required for SERDES GUI UART communication 2 Switch ON the SW7 power supply switch 3 Make sure that the board is programmed with IGLOO2_MTD...

Page 56: ... TESTER Window 6 Select the highest COM port from the drop down list and click Open to establish the connection with the test PC Figure 36 Selecting COM Port Note When using the USB cable for UART communication four COM ports are shown in the drop down list 7 Click the register configuration tab ...

Page 57: ...ed on LPDDR memory Note By default number of locations is shown 5000 It can be modified 2 Click DDR TEST to run the LPDDR write or read test While the test is in progress the DDR TEST PROGRESS shows the progress of the test in percentage Figure 38 shows the test status as Pass once the test is completed successfully Figure 38 LPDDR Test Note If the LPDDR test fails the number of locations are disp...

Page 58: ... must glow Press SW7 H6 LED must glow Press SW4 J6 LED must glow Press SW3 H7 LED must glow Debugging the Board If the board is not programmed successfully check if all the required power supplies clocks and reset signals are within the accepted range or not Power Supply Validation 1 Check for all default jumper settings as per Table 4 2 After power ON power supplies with respect to the ground mus...

Page 59: ... 78 1P8V 1 82 3 LEDs top left of board corresponding to their respective power rails must glow 4 Ripples on power rails should be within 5 of respective voltage rail Clock Measurement Measure clock signal at Y2 pin 3 and ensure that the stable 50 MHz signal is available Reset Measurement Measure reset signal at resistor R14 and ensure that this is 3 3 V and held High FPGA Programming Check whether...

Page 60: ...n 1 October 2013 Updated 7 Manufacturing Test section SAR 52040 41 Note The revision number is located in the part number after the hyphen The part number is displayed at the bottom of the last page of the document The digits following the slash indicate the month and year of publication ...

Page 61: ...ources It is very likely we have already answered your questions Technical Support Visit the Microsemi SoC Products Group Customer Support website for more information and support http www microsemi com soc support search default aspx Many answers available on the searchable web resource include diagrams illustrations and links to other resources on website Website You can browse a variety of tech...

Page 62: ...les office Sales office listings can be found at www microsemi com soc company contact default aspx ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations ITAR contact us via soc_tech_itar microsemi com Alternatively within My Cases select Yes in the ITAR drop down list For a complete list of ITAR regulated Microsemi FPGAs vi...

Page 63: ......

Page 64: ...d communications and industrial and alternative energy markets Products include high performance high reliability analog and RF devices mixed signal and RF integrated circuits customizable s FPGAs and complete subsystems Microsemi is headquartered in Aliso Viejo Calif Learn more at www microsemi com 2013 Microsemi Corporation All rights reserved Microsemi and the Microsemi logo are trademarks of M...

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