3 – Key Components Description and Operation
IGLOO2 FPGA Evaluation Kit User Guide
15
Memory Interface
Dedicated I/Os are provided for HPMS DDR and fabric DDR for the IGLOO2 device. Apart from the dedicated I/Os,
regular I/Os can also be used to connect to other memory devices. Refer to
Figure 7
.
Mobile LPDDR SDRAM
An individual chip, 512 Mb LPDDR SDRAM memory is provided as flexible volatile memory for user applications. The
LPDDR interface is implemented in bank 0. The specifications of LPDDR SDRAM are listed below:
•
MT46H32M16LF – 8 Meg x 16 x 4 banks
•
Density: 512 Mb
•
Data rate: LPDDR 16-bit at 400 Mbps = 6.4 Gbps
Note:
For more information, refer to page 3 of Board Level Schematics document (provided separately).
SPI Serial Flash
The specifications of SPI Flash are listed below:
•
Density: 64 Mb
•
Voltage: 2.7 V - 3.6 V
•
Frequency: 104 MHz
•
Supports: SPI modes 0 and 3
•
IGLOO2 HPMS - SPI0 interfaced to SPI flash
Note:
For more information, refer to page 8 of Board Level Schematics document (provided separately).
IGLOO2 FPGA
LPDDR
MT46H32M16LFBF-6
Control lines
SPI Flash
W25Q64FVSSIG
MDDR- Bank0
Bank2
CLK
SPI_0
DQ[15:0]
A[13:0]
Winbond Electronics
Micron
Figure 7.
IGLOO2 Memory Interface
