KSZ8463_eval_bd_user_guide_1.1.docx
Micrel, Inc.
July 17, 2013
Confidential
Rev. 1.1
7/16
JUMPER
FUNCTION
SETTING
JP400
+5V supply source selection
Pins 1-2 closed: Power connector (J11)
Pins 2-3 closed: USB port
JP403
+3.3V supply for KSZ8463 analog circuits
Must be closed
JP405
+1.2V supply for KSZ8463 analog circuits
Must be closed
VDD_IO selection
3.3V
2.5V
1.8V
JP404
Pins 2-3
closed
Pins 1-2
closed
Pins 1-2
closed
JP406
X
open
closed
Table 2 Power Supply Related Jumpers
Figure 2 Power Supply Section and Related Jumper Locations
3.3 Port 3 Configuration
The board features two Media Independent Interface (MII) connectors, for interfacing the MAC of Port-3
on the KSZ8463ML/FML to either an external PHY or MAC.
The female MII connector (J4, not installed) is used for interfacing to a PHY. For example, it can be
connected to a KSZ8081 eval board. When connecting to a PHY, the KSZ8463ML/FML must be set to
MAC mode. A jumper is provided (JP301) to set Port-3 in PHY or MAC mode of operation at power-up.
The male MII connector (J3) is used for interfacing to any host processor’s MAC interface. Normally this
port connects to a Micrel KSZ9692MII-PTP-EV or KSZ9692PB-PTP-EVAL board for evaluation of the
IEEE1588 PTP functionality. When connecting to an external MAC device such as the KSZ9692, the
KSZ8463ML/FML must be set to PHY mode.
The KSZ8463ML/FML provides a bypass feature in the MII PHY mode. JP27 is used to enable the MII
bypass mode. In the bypass mode, MII (port 3) is shut down and no new ingress frames from either Port 1
or Port 2 will be sent out through Port 3. Only the switch between Port 1 and Port 2 is active for all ingress
packets, and the frames for Port 3 already in packet memory will be flushed out.
