KSZ8463_eval_bd_user_guide_1.1.docx
Micrel, Inc.
July 17, 2013
Confidential
Rev. 1.1
10/16
As shown in Table 4 and Table 5, JP28 is used for enabling or disabling the generation of 50MHz
reference clock from the REFCLK_O pin of the KSZ8463RL/FRL. The 50MHz reference clock is always
provided to KSZ8463RL/FRL via REFCLK_I (pin 27).
JUMPER
FUNCTION
SETTING
DEFAULT
(no jumper)
JP28
50 MHz Reference
clock generation
Pins 1-2 closed: REFCLK_O is enabled
(EN_REFCLKO pin = 1)
Pins 2-3 closed: REFCLK_O is disabled
(EN_REFCLKO pin = 0)
REFCLK_O
disabled
Table 4 MII Port Configuration Settings
JP28 Setting
(EN_REFCLKO pin)
Clock Source
Note
Pins 2-3 closed
(EN_REFCLKO = 0,
REFCLK_O is off)
External 50MHz Ref Clock from oscillator
(or J4 pin 9) is input to REFCLK_I.
X1/X2 25MHz clock is not
used.
Pins 1-2 closed
(EN_REFCLKO = 1,
REFCLK_O is on)
REFCLK_O output must connect to
REFCLK_I, and also drives to J4 pin 12.
X1/X2 25MHz clock is
required.
Table 5 RMII Clock Setting
The RMII provided by the KSZ8463RL/FRL is connected to the device’s third MAC. It complies with the
RMII Specification. The following table describes the signals used by the RMII interface. Refer to RMII
Specification for full detail on the signal description.
RMII
Signal
Name
RMII
Signal Description
Pin number
on MII
connectors
Direction (with
respect to the
PHY)
Direction (with
respect to the
MAC)
Test
Points
REFCLK
Synchronous 50 MHz clock
reference for receive, transmit
and control interface
12
Input
Input or Output
TP5
CRS_DV
Carrier sense/
Receive data valid
8
Output
Input
TP6
RXD0
Receive data bit 0
7
Output
Input
TP4
RXD1
Receive data bit 1
6
Output
Input
TP11
TX_EN
Transmit enable
13
Input
Output
TP6
TXD0
Transmit data bit 0
14
Input
Output
TP7
TXD1
Transmit data bit 1
15
Input
Output
TP16
RX_ER
Receive error
10
Output
Input or not required
TP15
Table 6 RMII Signal Description
