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KSZ8463_eval_bd_user_guide_1.1.docx 
 

Micrel, Inc.  

 

July 17, 2013 

Confidential 

 

Rev. 1.1 

14/16

 

3.8  List of Jumpers and Connectors 

 

Jumper 

Description 

Setting 

J12-13 

FXSD pin connections 

Pins 1-2 closed: connect to SD signal 
from fiber module 
Pins 3-4 closed: ground the FXSD pins, 
for copper mode 

J14 

USB IO voltage selection 

Close pins 1-2 or 2-3 to power USB to 
serial interface.  Either setting will work. 

JP2 

PWRDN Chip Power-down 

Place Jumper for full chip power-down 

JP3, 9 

Factory Usage 

Install no jumpers 

JP10, 11 

Power selection for the Fiber module  

Leave open when no Fiber Module 
present 

JP27 

MII bypass 

Pins 1-2 closed: Enable MII bypass mode 
Pins 2-3 closed: MII PHY mode normal 
operation 

JP28 

Enable RMII mode reference clock output from 
REFCLK_O pin  

Pins 1-2 closed: Enable  
Pins 2-3 closed: Disable 

JP32, 33 

Enable MDIO interface through MII connector 

Place both jumpers to connect MDIO 
signals from MII connector to KSZ8463 
serial port. 
When using SPI, do not install jumpers. 

JP34, 35 

KSZ8463 serial port connections 

Place both jumpers for USB port access 
and SPI interface 

JP36-38 

GPIO7, GPIO9 and GPIO10 pin source 
selection on GPIO Headers 

Pins 1-2 closed for KSZ8463RL/FRL 
Pins 2-3 closed for KSZ8463ML/FML 

JP77, 78 

FXSD1, FXSD2 Fiber signal detect input for 
Port 1 and Port 2 (not used) 

 

JP79 

Enable USB controller interface 

Close pins 1-2, 3-4, 5-6 and 7-8 to 
connect USB controller to serial bus 

JP301-305  Strapping options 

See Table 1 

JP306 

Not used 

 

JP400 

5V DC input selection 

See Table 2 

JP403-406  Power-supply strapping options 

See Table 2 

Table 9   List of Jumpers and Connectors 

 

Summary of Contents for KSZ8463ML

Page 1: ...KSZ8463_eval_bd_user_guide_1 1 docx Micrel Inc July 17 2013 Confidential Rev 1 1 1 16 KSZ8463ML RL Evaluation Board User Guide Preliminary Revision 1 1 July 17 2013...

Page 2: ...7 LED Indicators 13 3 8 List of Jumpers and Connectors 14 3 9 Board Layout 15 4 Using the KSZ8463ML RL Evaluation Board 15 5 Reference Documents 16 6 Revision History 16 List of Figures Figure 1 KSZ84...

Page 3: ...RMII mode This KSZ8463ML RL Evaluation Board User Guide provides the information necessary to configure and set up the board to evaluate or test the KSZ8463ML and KSZ8463RL devices in different envir...

Page 4: ...sed to configure various features in the device This is accomplished with on board jumper options so that the KSZ8463 powers up in the desired modes With no additional programming of registers the dev...

Page 5: ...umpers to the desired settings and apply power to the board The configuration can be changed while power is applied to the board by changing the jumper settings and pressing the manual reset button fo...

Page 6: ...pp exe plus associated DLL files MicrelSwitchConfigApp has a graphical user interface GUI and provides access via USB to many of the KSZ8463 registers via the SPI interface MicrelMDIOConfigApp and the...

Page 7: ...s used for interfacing to a PHY For example it can be connected to a KSZ8081 eval board When connecting to a PHY the KSZ8463ML FML must be set to MAC mode A jumper is provided JP301 to set Port 3 in P...

Page 8: ...ode selection for MII on Port 3 1 Pins 1 2 closed PHY mode Pins 2 3 closed MAC mode PHY mode JP27 Bypass mode for MII PHY mode link 3 Pins 1 2 closed Bypass enabled Pins 2 3 closed Normal operation No...

Page 9: ...signal in PHY mode operation and the TX_ER signal in MAC mode operation Normally RX_ER indicates a receive error coming from the physical layer device and TX_ER indicates a transmit error from the MA...

Page 10: ...LK_O output must connect to REFCLK_I and also drives to J4 pin 12 X1 X2 25MHz clock is required Table 5 RMII Clock Setting The RMII provided by the KSZ8463RL FRL is connected to the device s third MAC...

Page 11: ...ed therefore 9 GPIO pins are available If more than 9 GPIO pins are required the user needs to program IOMXSEL register 0x0D6 as follows IOMXSEL register 0x0D6 Description Setting Bit 10 Selection of...

Page 12: ...thernet the FXSD1 and FXSD2 pins should be pulled low by installing jumpers on pins 3 4 of J12 and J13 3 6 100BASE FX Fiber Port Option There are two 100BASE FX PHY ports on the KSZ8463ML RL evaluatio...

Page 13: ...xLED0 for each PHY port The LED indicators are programmable to four different states LED mode is selected through bits 9 8 of the SGCR7 register 0x00E 0x00F The LED mode definitions are specified in T...

Page 14: ...8 Enable RMII mode reference clock output from REFCLK_O pin Pins 1 2 closed Enable Pins 2 3 closed Disable JP32 33 Enable MDIO interface through MII connector Place both jumpers to connect MDIO signal...

Page 15: ...evaluation board is configured in PHY mode and connected to the SOC board through its MII port In addition to the MII connection the SOC accesses the KSZ8463 through the SPI port An interrupt line is...

Page 16: ...any time without notification to the customer Micrel Products are not designed or authorized for use as components in life support appliances devices or systems where malfunction of a product can rea...

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