KSZ8463_eval_bd_user_guide_1.1.docx
Micrel, Inc.
July 17, 2013
Confidential
Rev. 1.1
13/16
The fiber signal detect threshold is set to 1.7V internally, When FXSD is less than the threshold, no fiber
signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the fiber
signal is detected. To ensure proper operation, a resistive voltage divider is recommended to adjust the
fiber transceiver SD output voltage swing to match the FXSD pin’s input voltage threshold.
Alternatively, the user may choose not to implement the FEF feature. In this case, the FXSD input pin may
be pulled high via jumpers JP77 and JP78.
3.7 LED Indicators
The KSZ8463ML/RL evaluation board provides two LEDs (PxLED1, PxLED0) for each PHY port. The
LED indicators are programmable to four different states. LED mode is selected through bits [9:8] of the
SGCR7 register (0x00E-0x00F).
The LED mode definitions are specified in Table 7. See Figure 2 for the LEDs’ orientation on the
KSZ8463ML/RL evaluation board in the power supply section.
SGCR7 Control Register (0x00E-0x00F) Bits[9:8]
00 (default)
01
10
11
PxLED1 = Speed
PxLED1 = Active
PxLED1 = Duplex
PxLED1 = Duplex
PxLED0 = Link/Active
PxLED0 = Link
PxLED0 = Link/Active
PxLED0 = Link
Table 8 LED Functions
The KSZ8463ML/RL evaluation board also has a power LED (D3) for the 3.3V power supply. When D3 is
illuminated, the board’s 3.3V power supply is “on”.
The activity LED indicators for Port-1 and Port-2 are powered by VDD_IO, which can be set to 3.3V, 2.5V
or 1.8V. In the case of 2.5V and 1.8V selection, these LED indicators will be dimly lit or not illuminated
because of inadequate voltage across the LED.
