KSZ8463_eval_bd_user_guide_1.1.docx
Micrel, Inc.
July 17, 2013
Confidential
Rev. 1.1
15/16
3.9 Board Layout
The layout of the board is shown in Figure 3. The key areas are indicated.
Figure 4 Topside Layout of the Board
The KSZ8463ML/RL Evaluation board, together with the KSZ9692PB SOC board (KSZ9692-MII-PTP-EV),
provides a complete evaluation platform for the IEEE1588 PTP functionality. In this setup, Port 3 of the
KSZ8463 evaluation board is configured in PHY mode and connected to the SOC board through its MII
port. In addition to the MII connection, the SOC accesses the KSZ8463 through the SPI port. An interrupt
line is also used for PTP software functionality. For more details on this configuration, refer to the
KSZ8463ML Evaluation Kit User Guide.
4 Using the KSZ8463ML/RL Evaluation Board
The Evaluation Kit is intended to provide a platform that enables designers to investigate and evaluate the
capabilities of the KSZ8463 device. It is not intended to be a complete development system to be used for
an entire product design effort.
