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KSZ8463_eval_bd_user_guide_1.1.docx 
 

Micrel, Inc.  

 

July 17, 2013 

Confidential 

 

Rev. 1.1 

12/16

 

 

 

Figure 3   GPIO Connectors and Related Jumper Locations 

 

3.5  10/100 Ethernet PHY Ports 

 
There are two 10/100 Ethernet PHY ports on the KSZ8463ML/RL  evaluation board.  The ports can be 
connected to an Ethernet traffic generator or analyzer via standard RJ-45 connectors  using CAT-5  (or 
better) UTP cables.  Both ports support auto MDI/MDI-X, eliminating the need for cross-over cables. 
 
Transformers are utilized for proper interfacing to an Ethernet network. In addition, optional over-voltage 
protection devices D5 thru D12 may be installed to protect the KSZ8463 in the event of an over-voltage 
condition. 
 
For 10/100 Ethernet, the FXSD1 and FXSD2 pins should be pulled low by installing jumpers on pins 3 & 4 
of J12 and J13. 
 

3.6  100BASE-FX Fiber Port Option 

 
There are two 100BASE-FX PHY ports on the KSZ8463ML/RL evaluation board, which are not populated 
with necessary components.  The ports can be connected to an Ethernet traffic generator or analyzer via 
fiber transceiver and fiber cable. In 100BASE-FX operation, both fiber signal detect input FXSD1 and 
FXSD2 are usually connected to the fiber transceiver SD (signal detect) output pin. This is done by 
jumpering pins 1 & 2 of J12 (Port 1) and J13 (Port 2).  No jumpers are required on JP77 and JP78 except 
as noted below.  Capacitors C5 and C6 are also generally not required. 
 
100BASE-FX is supported by the KSZ8463FML and KSZ8463FRL devices.  All KSZ8463 devices power 
up in copper mode.  Fiber Mode is selected by clearing the appropriate bits in the GFCR register (0x0D8 – 
0x0D9). 

Summary of Contents for KSZ8463ML

Page 1: ...KSZ8463_eval_bd_user_guide_1 1 docx Micrel Inc July 17 2013 Confidential Rev 1 1 1 16 KSZ8463ML RL Evaluation Board User Guide Preliminary Revision 1 1 July 17 2013...

Page 2: ...7 LED Indicators 13 3 8 List of Jumpers and Connectors 14 3 9 Board Layout 15 4 Using the KSZ8463ML RL Evaluation Board 15 5 Reference Documents 16 6 Revision History 16 List of Figures Figure 1 KSZ84...

Page 3: ...RMII mode This KSZ8463ML RL Evaluation Board User Guide provides the information necessary to configure and set up the board to evaluate or test the KSZ8463ML and KSZ8463RL devices in different envir...

Page 4: ...sed to configure various features in the device This is accomplished with on board jumper options so that the KSZ8463 powers up in the desired modes With no additional programming of registers the dev...

Page 5: ...umpers to the desired settings and apply power to the board The configuration can be changed while power is applied to the board by changing the jumper settings and pressing the manual reset button fo...

Page 6: ...pp exe plus associated DLL files MicrelSwitchConfigApp has a graphical user interface GUI and provides access via USB to many of the KSZ8463 registers via the SPI interface MicrelMDIOConfigApp and the...

Page 7: ...s used for interfacing to a PHY For example it can be connected to a KSZ8081 eval board When connecting to a PHY the KSZ8463ML FML must be set to MAC mode A jumper is provided JP301 to set Port 3 in P...

Page 8: ...ode selection for MII on Port 3 1 Pins 1 2 closed PHY mode Pins 2 3 closed MAC mode PHY mode JP27 Bypass mode for MII PHY mode link 3 Pins 1 2 closed Bypass enabled Pins 2 3 closed Normal operation No...

Page 9: ...signal in PHY mode operation and the TX_ER signal in MAC mode operation Normally RX_ER indicates a receive error coming from the physical layer device and TX_ER indicates a transmit error from the MA...

Page 10: ...LK_O output must connect to REFCLK_I and also drives to J4 pin 12 X1 X2 25MHz clock is required Table 5 RMII Clock Setting The RMII provided by the KSZ8463RL FRL is connected to the device s third MAC...

Page 11: ...ed therefore 9 GPIO pins are available If more than 9 GPIO pins are required the user needs to program IOMXSEL register 0x0D6 as follows IOMXSEL register 0x0D6 Description Setting Bit 10 Selection of...

Page 12: ...thernet the FXSD1 and FXSD2 pins should be pulled low by installing jumpers on pins 3 4 of J12 and J13 3 6 100BASE FX Fiber Port Option There are two 100BASE FX PHY ports on the KSZ8463ML RL evaluatio...

Page 13: ...xLED0 for each PHY port The LED indicators are programmable to four different states LED mode is selected through bits 9 8 of the SGCR7 register 0x00E 0x00F The LED mode definitions are specified in T...

Page 14: ...8 Enable RMII mode reference clock output from REFCLK_O pin Pins 1 2 closed Enable Pins 2 3 closed Disable JP32 33 Enable MDIO interface through MII connector Place both jumpers to connect MDIO signal...

Page 15: ...evaluation board is configured in PHY mode and connected to the SOC board through its MII port In addition to the MII connection the SOC accesses the KSZ8463 through the SPI port An interrupt line is...

Page 16: ...any time without notification to the customer Micrel Products are not designed or authorized for use as components in life support appliances devices or systems where malfunction of a product can rea...

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