KSZ8463_eval_bd_user_guide_1.1.docx
Micrel, Inc.
July 17, 2013
Confidential
Rev. 1.1
8/16
Whereas the KSZ8463ML/FML uses the full MII signaling pins of the connectors, the KSZ8463RL/FRL
makes use of a subset of the available pins, as defined by the RMII standard. The RMII standard requires
a 50 MHz clock which can be generated by the KSZ8463RL/FRL chip, or supplied externally. The
KSZ8463ML/RL Evaluation board provides both options. JP28 is connected to EN_REFCLKO (pin 23), to
enable or disable the generation of the 50 MHz clock by the KSZ8463RL/FRL on REFCLK_O (pin 32).
When REFCLKP_O (JP28) is enabled, the Input Clock Select option (JP305) must be set to “25MHz from
X1/X2”.
An on-board 50 MHz oscillator (Y2, not installed) is also provided for the RMII devices. This oscillator
drives a 50 MHz clock both to the J4 connector (pin 12) and to the KSZ8463RL/FRL (REFCLK_I, pin 27).
In this configuration, REFCLK_O (JP28) must be disabled, and JP305 is used to select the “50MHz from
REFCLK_I” option. When installing Y2, it is also necessary to install R181, R187, and to remove R51,
R53 and R58.
JUMPER
FUNCTION
SETTING
DEFAULT
(no jumper)
JP301
MAC/PHY mode
selection for MII on
Port-3
[1]
Pins 1-2 closed: PHY mode
Pins 2-3 closed: MAC mode
PHY mode
JP27
Bypass mode for MII
PHY mode link
[3]
Pins 1-2 closed: Bypass enabled
Pins 2-3 closed: Normal operation
Normal
operation
JP28
50 MHz Reference
clock generation
[4]
Pins 1-2 closed: REFCLK_O is enabled
(EN_REFCLKO pin = 1)
Pins 2-3 closed: REFCLK_O is disabled
(EN_REFCLKO pin = 0)
REFCLK_O
disabled
JP305
Input Clock Select
[2]
Pins 1-2 closed: 25MHz from X1/X2
Pins 2-3 closed: 50MHz from REFCLK_I
25MHz
Table 3 MII / RMII Port Configuration Settings
Notes:
3. The Bypass mode option applies only when in MII PHY mode. When in MII MAC mode, do not
install any jumper on JP27.
4. The 50 MHz reference option applies only to RMII devices (KSZ8463RL and KSZ8463FRL). For
MII devices (KSZ8463ML and KSZ8463FML), do not install a jumper on JP28.
3.3.1 MII Port Configuration (KSZ8463ML, KSZ8463FML)
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 standard. It provides a
common interface between PHY layer and MAC layer devices. The MII provided by the KSZ8463ML/FML
is connected to the device’s third MAC (Port 3). The interface contains two distinct groups of signals, one
for transmission and the other for reception. The following table describes the signals used by the MII
interface to connect either external MAC or external PHY.
