Maxim Integrated MAX31782, User Manual

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MaximIntegrated 9-6
MAX31782 User’s Guide
Revision 0; 8/11
9.2PWMOutputRegisterDescriptions
The following peripheral registers are used to control the PWM outputs of the MAX31782 . Each of the six independent
PWM outputs has four associated registers . Since there are six independent PWM outputs, the registers are described
in a batch manner . For example, the control register is denoted as PWMCNn, where n = 0 to 5 . Each PWM register is
independent, meaning each PWM can be configured and operated differently .
9.2.1PWMControlRegister(PWMCNn)
The PWM control register, PWMCNn, is used to set up and start the PWM output . To avoid undesired operation, the user
should
not modify the reserved bits in the PWMCNn registers .
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name — — — PWMCS PWMCR PWMPS2 PWMPS1 PWMPS0 TFB — — DCEN — PWMEN ETB —
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access r r r rw rw rw rw rw rw r r rw r rw rw r
BIT NAME DESCRIPTION
15:13 — Reserved . The user should not write to these bits .
12:11
PWMCS,
PWMCR
PWM Pin Output Set/Reset Mode Bits . These mode bits define if the PWM output function is
enabled on the PWM .n pin, the initial output starting state when the PWM is disabled (PWMEN = 0),
and what compare mode output function is used .
10:8 PWMPS[2:0]
PWM Clock Prescaler Bits . These bits select the clock prescaler applied to the system clock, which
is then used as the PWM clock . The PWMPS[2:0] bits should be configured by the user when the
timer is stopped (PWMEN = 0) . While hardware does not prevent changing the PWMPS[2:0] bits
when the PWM is running, the resulting behavior is nondeterministic .
PWMPS[2:0] PWMINPUTCLOCK
000 Sysclk
001 Sysclk/4
010 Sysclk/16
011 Sysclk/64
100 Sysclk/256
101 Sysclk/1024
11x Sysclk
7 TFB
PWM Overflow Flag . This bit is set when the PWM overflows or reaches PWMRn and is reloaded to
0000h . The TFB flag is also set when PWMVn is equal to 0000h in when counting down . The setting
of this flag causes an interrupt if enabled . This flag must be cleared by software .
6:5 — Reserved . The user should not write to these bits .
4 DCEN
Down-Count Enable . The DCEN bit controls if the PWM operates in normal PWM mode and counts
up only (DCEN = 0), or operates in up/down count mode and counts up and down (DCEN = 1) .
3 — Reserved . The user should not write to this bit .
2 PWMEN
PWM Run Control . This bit enables PWM operation when set to 1 . Clearing this bit to 0 halts the
PWM operation and preserves the current count in PWMVn .
1 ETB PWM Interrupt . Setting this bit to 1 enables interrupts from the TFB flag .
0 — Reserved . The user should not write to this bit .