MaximIntegrated 7-3
MAX31782 User’s Guide
Revision 0; 8/11
7.1.2SlaveAddress
Prior to communication, an I
2
C slave address may need to be selected . The I
2
C slave controller normally responds to
two slave addresses . The I
2
C bootloader uses address 34h . This bootloader address cannot be changed and should
not be used as the device slave address for normal communication . The second slave address is the address used
for communication with the host . This slave address is set using the I2CSLA_S register . The address contained in the
I2CSLA_S register is the address without the R/
W
bit . For example, the default I
2
C slave address is 36h, meaning the
I2CSLA_S register contains 1Bh . If an address other than 36h is desired, the I2CSLA_S register can be programmed
with this new address .
The I
2
C slave controller can also be programmed to respond to a third address, the general call address, which is 00h .
This feature can be enabled by setting the I2CCN_S .I2CGCEN bit to 1 .
7.1.3I
2
CSTARTDetection
The I
2
C slave controller always monitors the I
2
C bus for an I
2
C START, which is a high-to-low transition on SDA while
SCL is held high . If an I
2
C START (or restart) condition is detected, the I
2
C slave sets the I2CSRI bit in the I2CST_S
register, which can cause an interrupt if enabled . The detection of a START brings the I
2
C controller out of its idle state .
Following a START, the I
2
C controller begins to monitor data on the I
2
C bus and the I2CBUSY bit is set to 1 . The I2CBUS
bit is also set to 1 indicate that the I
2
C bus is currently busy .
7.1.4I
2
CSTOPDetection
The I
2
C slave controller also always montors the I
2
C bus for an I
2
C STOP, which is a low-to-high transition on SDA
while SCL is held high . If an I
2
C STOP condition is detected, the I
2
C slave controller sets the I2CSPI bit in the I2CST_S
register, which can cause an interrupt if enabled . The I2CBUS bit is cleared to 0 following a STOP to indicate that the
I2C bus is no longer busy .
7.1.5SlaveAddressMatching
Following an I
2
C START or restart, the I
2
C slave controller knows that the next byte of data transmit by the host should
be the slave address . The I
2
C slave automatically monitors for the slave address without any software interaction
required . The I
2
C slave controller compares the first 7 bits received to the slave address programmed into I2CSLA_S .
After receiving the first 8 bits of data following a START, the I
2
C controller compares the first 7 bits to the value pro-
grammed into the I2CSLA_S register . If the received slave address matches I2CSLA_S, the I
2
C slave controller does
the following steps, as illustrated in
.
• Transmits an ACK or NACK on the 9th clock based upon the setting of the I2CCN_S .I2CACK bit .
• Sets the I2CCN_S .I2CMODE bit with the value of the received R/
W
bit . This bit can be used by software to determine
if the I
2
C slave controller would be asked to receive or transmit data .
• Sets the I2CST_S .I2CAMI bit to indicate that a slave address match was made . The setting of this bit can generate
an interrupt if enabled .
• Clears the I2CBUSY flag .
Upon completion of the slave data byte (7 bits of slave a R/
W
bit + ACK/NACK), the I
2
C slave controller enters
one of three states:
• Data Transmit: The slave address matched and the R/
W
bit was a 1 . The host is now expecting to clock data from
the MAX31782 . The MAX31782 retains control of the SDA line so data can be transmit to the host .
• Data Receive: The slave address matched and the R/
W
bit was a 0 . The host wants to write data to the MAX31782 .
After the ACK/NACK bit, the MAX31782 releases SDA and prepares to receive a byte of data .
• Wait for START/STOP: The received slave address did not match I2CSLA_S . The controller enters idle state and
waits for the next START condition or STOP condition .
