MaximIntegrated 18-4
MAX31782 User’s Guide
Revision 0; 8/11
If SPE is not set, the MAX31782 then enables the slave I
2
C interface . The I2C_SPE bit in the I2C_SPB register is read
to determine if I
2
C bootloader operation is desired . The I2C_SPB register is not cleared by a reset . See
for more details on setting the I2C_SPE bit . If I2C_SPE is set, the MAX31782 sets the PSS[1:0] bits to
01, which designates I
2
C bootloader, and enters bootloader operation .
If the I2C_SPE bit is not set, the ROM code then checks for a valid password in flash . See
for more details about the password . If there is not a valid password, the MAX31782 ROM code assumes that the
program memory is blank and the device has never been programmed . The ROM code sets the I2C_SPE bit and the
PSS[1:0] bits to 01 and then enters I
2
C bootloader operation . Because of this operation, it is required that all programs
contain a valid password in order for the MAX31782 to enter normal operation following a reset .
If none of the preceding conditions have been met, the MAX31782 ROM code will be complete . The MAX31782 then
jumps to program memory location 0000h and begin normal program execution .
18.1.1PasswordProtection
The MAX31782 uses a password to protect the contents of the program memory from simple access and viewing . The
password resides in the 32 bytes of program memory at byte address 0020h to 003Fh . A valid password is defined as
any value that does not contain all 0000h or FFFFh . Following a reset, the password lock bit (PWL) in the SC register is
set if the MAX31782 contains a valid password .
To protect the program memory, MAX31782 grants full access to in-system programming, in-application program-
ming, or in-circuit debugging only after a password match has occurred . When a password match occurs, the PWL
bit is cleared to 0 . When bootloading the device, the password can be matched using the Password Match command,
through either the JTAG or I
2
C interface .
18.1.2EnteringJTAGBootloader
To enable the bootstrap loader and establish a desired communication channel through JTAG, the system program-
ming instruction (100b) must be loaded into the TAP instruction register using the IR-Scan sequence . The TAP retains
the System Programming instruction until a new instruction is shifted in or the TAP controller returns to the Test-Logic-
Reset state . See
SECTION 16: Test Access Port (TAP)
for more information regarding the JTAG port .
Once the instruction is latched in the instruction parallel buffer (IR[2:0]) and is recognized by the TAP controller in the
Update-IR state, a 3-bit data shift register is activated as the communication channel for DR-Scan sequences . This
3-bit shift register formed between the TDI and TDO pins is directly interfaced to the 3-bit serial programming buffer
(SPB) .
provides a detailed description of the system programming buffer (SPB) . The data content of the SPB
is reflected in the ICDF register, which allows read and write access by the CPU . These bits are cleared by power-on
reset or Test-Logic-Reset of the TAP controller .
Table18-1.SystemProgrammingBuffer(SPB)
BIT
NAME
DESCRIPTION
2:1
PSS[1:0]
Programming Source Select . These bits select the programming interface source .
PSS1
PSS0
PROGRAMMINGSOURCE
0
0
JTAG
0
1
I
2
C
1
x
Exit loader
0
SPE
System Programming Enable (SPE) . Setting this bit to a 1 denotes that JTAG bootloading is desired
upon exiting reset . The logic state of SPE is examined by the utility ROM following a reset to deter-
mine the program flow . When SPE = 1, the bootstrap loader selected by the PSS[1:0] bits is activat-
ed to perform a bootstrap loader function . If SPE = 0, the utility ROM determines if I
2
C bootloading
is required before transferring execution control to the normal user program .
