MaximIntegrated 8-8
MAX31782 User’s Guide
Revision 0; 8/11
If clock stretching is enabled after the 8th clock pulse, the master I
2
C controller will continue outputting the value of the
I2CACK bit until clock stretching is released by clearing I2CSTRI . This allows software time to examine the data that
was received prior to sending an ACK or NACK to the slave . The continuous output of I2CACK will occur even if the
master I
2
C controller is transmitting data . In this mode, the slave should be sending the acknowledgement . To allow
the slave to send the proper acknowledgement, the I2CACK bit should be set to a 1, which prompts the master I
2
C
controller to release SDA .
The master I
2
C controller may need to use clock stretching when receiving data from a slave . When receiving data,
the master I
2
C controller automatically generates clock pulses . Without using clock stretching, this automatic clock
generation is only halted when a STOP command is issued or a receive overrun occurs . If clock stretching is enabled,
software can control when each byte of data is clocked from the slave device .
8.1.11ResettingtheI
2
CMasterController
The I
2
C master controller can be reset by setting the RESET_M bit in the SMBUS register . After a delay of at least one
system clock, this bit needs to be cleared by software to complete the reset . A reset will force the master I
2
C controller
to release both MSDA and MSCL if they are being held low by the I
2
C master controller . A reset will also turn off the I
2
C
master controller (I2CEN = 0), reset all of the master I
2
C registers, and reset the I
2
C master controller’s internal state
machine . Following a reset, the I
2
C master controller must be reinitialized before it can be used again .
After a reset, the master I
2
C controller will be in a known state but the slave devices may be in an unknown state . It
is recommended that the master I
2
C controller attempts to reset the slave devices prior to beginning communication .
A reset of slave devices can be performed by outputting at least nine clock pulses on the MSCL line while MSDA is
high . This easiest way to achieve this is to use MSDA and MSCL as GPIO pins (see
) while the master I
2
C controller is disabled (I2CEN = 0) . After the nine clock pulses, a STOP
command should be generated . This can be done either using GPIO, or by enabling the master I
2
C controller and
generating a STOP .
8.1.12OperationasaSlave
The MAX31782 contains two I
2
C interfaces, the master (MSDA and MSCL) and slave (MAX31782 SDA and SCL pins) .
These are two totally separate blocks within the MAX31782 . However, both of the blocks are identical . Because of this,
it is possible to operate the master as a slave and also operate the slave as a master .
To operate the master (MSDA and MSCL) as a slave I
2
C interface, the I2CMST bit in I2CCN_M needs to be set to a
0 . When the master is operating as a slave, it will use the same registers (I2CCN_M, I2CST_M, etc) that it uses for
master operation . However, the bits in these registers will have different functionality, as described in
. The SMBUS .RESET_M bit can still be used to reset this interface (MSDA and MSCL)
when operating as a slave . The SMBUS .SMB_MOD_M bit only affects the interface when it is operating as a slave . See
for details on initializing and using a slave I
2
C interface .
8.1.13GPIO
When the I
2
C master controller is disabled (I2CEN = 0), the MSDA and MSCL pins can be used as GPIO pins . The
MSDA pin is mapped to GPIO port P2 .7 and MSCL is mapped to GPIO port P2 .6 . When used as GPIO outputs, the
MSDA and MSCL pins are only capable of being open-drain outputs . See
