MaximIntegrated 5-8
MAX31782 User’s Guide
Revision 0; 8/11
5.3.2InterruptPrioritizationbySoftware
All interrupt sources of the MAX31782 naturally have the same priority . However, when CPU operation vectors to the
programmed interrupt vector address, the order in which potential interrupt sources are interrogated is left entirely up
to the user, as this often depends upon the system design and application requirements . The IMR system register pro-
vides the ability to knowingly block interrupts from modules considered to be of lesser priority and manually re-enable
the interrupt servicing by the CPU (by setting INS = 0) . Using this procedure, a given interrupt service routine can con-
tinue executing, only to be interrupted by higher priority interrupts . An example demonstrating this software prioritization
is provided in the
5.3.3InterruptExceptionWindow
An interrupt exception window is a noninterruptable execution cycle . During this cycle, the interrupt handler does not
respond to any interrupt requests . All interrupts that would normally be serviced during an interrupt exception window
are delayed until the next execution cycle .
Interrupt exception windows are used when two or more instructions must be executed consecutively without any
delays in between . Currently, there is a single condition in the MAX31782 that causes an interrupt exception window:
activation of the PFX register .
When the PFX register is activated by writing a value to it, it retains that value only for the next clock cycle . For the prefix
value to be used properly by the next instruction, the instruction that sets the prefix value and the instruction that uses
it must always be executed back to back . Therefore, writing to the PFX register causes an interrupt exception window
on the next cycle . If an interrupt occurs during an interrupt exception window, an additional latency of one cycle in the
interrupt handling is caused since the interrupt is not serviced until the next cycle .
