MaximIntegrated 8-9
MAX31782 User’s Guide
Revision 0; 8/11
8.2I
2
CMasterControllerRegisterDescriptions
Following are the registers that are used to control the I
2
C master interface, which is the MSDA and MSCL pins . These
registers are used to control the I
2
C master interface if it is operating as either a master or slave . The bit descriptions
below detail how to use these registers when operating in master mode . When operating in slave mode, some of the
bits and registers have different functionality . See
how to control the I
2
C master interface when it is operating as a slave .
8.2.1I
2
CMasterControlRegister(I2CCN�M)
Address: M1[0Ch]
*
Unrestricted read. Unrestricted write access when I2CBUSY = 0. Writes to I2CEN are disabled when I2CBUSY = 1.
Note:
The I2CSTART and I2CSTOP bits are mutually exclusive. If both bits are set at the same time, it is considered an invalid
operation and the I2C controller ignores the request and resets both bits to 0. Setting the I2CSTART bit to 1 while I2CSTOP = 1 is
an invalid operation and is ignored, leaving the I2CSTART bit cleared to 0.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
I2CSTREN I2CGCEN I2CSTOP I2CSTART I2CACK I2CSTRS
—
I2CMODE
I2CMST
I2CEN
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Access
r
r
r
r
r
r
rw
rw
rw
rw
rw
rw
r
rw*
rw*
rw*
BIT
NAME
DESCRIPTION
15:10
—
Reserved . The user should not write to these bits .
9
I2CSTREN
I
2
C Master Clock Stretch Enable . Setting this bit to 1 stretches the clock (hold SCL low) at the end of
the clock cycle specified by I2CSTRS . Clearing this bit disables clock stretching .
8
I2CGCEN
This bit has no function when operating in master mode .
7
I2CSTOP
I
2
C
STOP Enable . Setting this bit to 1 generates a STOP condition . This bit is automatically cleared
to 0 after the STOP condition has been generated . The setting of I2CSTOP starts the timeout timer if
enabled . If the timeout timer expires before the STOP condition is generated, the I2CTOI flag is set,
which can generate an interrupt if enabled . A timeout also clears the I2CSTOP bit .
6
I2CSTART
I
2
C
START Enable . Setting this bit to 1 generates a START or repeated START condition . This bit is
automatically cleared to 0 after the START condition has been generated . The setting of I2CSTART
starts the timeout timer if enabled . If the timeout timer expires before the START condition is gener-
ated, the I2CTOI flag is set, which can generate an interrupt if enabled . A timeout also clears the
I2CSTART bit .
5
I2CACK
I
2
C Master Data Acknowledge Bit . This bit selects the acknowledge bit returned by the master I
2
C
controller while acting as a receiver . Setting this bit to 1 generates a NACK (leaving SDA high) .
Clearing the I2CACK bit to 0 generates an ACK (pulling SDA low) during the acknowledgement
cycle . This bit retains its value unless changed by software or hardware .
4
I2CSTRS
I
2
C Master Clock Stretch Select . Setting this bit to 1 enables clock stretching after the falling edge
of the 8th clock cycle . Clearing this bit to 0 enables clock stretching after the falling edge of the 9th
clock cycle . This bit has no effect when clock stretching is disabled (I2CSTREN = 0) .
3
—
Reserved . The user should not write to this bit .
2
I2CMODE
I
2
C Master Transfer Mode Select .
When the I2CMODE bit is set to 1, the master is operating in
receiver mode (reading from slave) . When the I2CMODE bit is cleared to 0, the master is operating in
transmitter mode (writing to slave) .
1
I2CMST
I
2
C Master Mode Enable . Setting this bit to 1 enables I
2
C master functionality on the MSDA and
MSCL pins . Setting this bit to 0 enables I
2
C slave functionality . See
section for more details .
0
I2CEN
I
2
C Enable . This bit enables the I
2
C master interface . When set to 1, the I
2
C master interface is
enabled . When cleared to 0, the I
2
C function is disabled .
