MaximIntegrated 5-7
MAX31782 User’s Guide
Revision 0; 8/11
5.2.6PeripheralModule5InterruptIdentificationRegister(MIIR5,M5[18h])
5.3InterruptSystemOperation
The interrupt handler hardware responds to any interrupt event when it is enabled . An interrupt event occurs when
an interrupt flag is set . All interrupt requests are sampled at the rising edge of the clock and can be serviced by the
processor one clock cycle later, assuming the request does not hit the interrupt exception window . The one-cycle stall
between detection and acknowledgement/servicing is due to the fact that the current instruction may also be accessing
the stack . For this reason, the CPU must allow the current instruction to complete before pushing the stack and vector-
ing to IV . If an interrupt exception window is generated by the currently executing instruction, the following instruction
must be executed, so the interrupt service routine is delayed an additional cycle .
Interrupt operation in the MAX31782 CPU is essentially a state machine generated long CALL instruction . When the
interrupt handler services an interrupt, it temporarily takes control of the CPU to perform the following sequence of
actions:
1) The next instruction fetch from program memory is cancelled .
2) The return address is pushed on to the stack .
3) The INS bit is set to 1 to prevent recursive interrupt calls .
4) The instruction pointer is set to the location of the interrupt service routine (contained in the IV register) .
5) The CPU begins executing the interrupt service routine .
Once the interrupt service routine completes, it should use the RETI instruction to return to the main program . Execution
of RETI involves the following sequence of actions:
1) The return address is popped off the stack .
2) The INS bit is cleared to 0 to re-enable interrupt handling .
3) The instruction pointer is set to the return address that was popped off the stack .
4) The CPU continues execution of the main program .
Pending interrupt requests do not interrupt an RETI instruction; a new interrupt is serviced after first being acknowl-
edged in the execution cycle that follows the RETI instruction and then after the standard one stall cycle of interrupt
latency . This means there are at least two cycles between back-to-back interrupts .
5.3.1Synchronousvs.AsynchronousInterruptSources
Interrupt sources can be classified as either asynchronous or synchronous . All internal interrupts are synchronous inter-
rupts . An internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle . All external
interrupts are asynchronous interrupts by nature . When the device is not in stop mode, asynchronous interrupt sources
are passed through a 3-clock sampling/glitch filter circuit before being routed to the interrupt handler . The sampling/
glitch filter circuit is running on the system clock . An interrupt request with a pulse width less than three system clock
cycles is not recognized . Note that the granularity of interrupt source is at module level . Synchronous interrupts and
sampled asynchronous interrupts assigned to the same module produce a single interrupt to the interrupt handler .
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TACH5
TACH4
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
r
r
r
r
r
r
r
r
r
R
r
r
r
r
r
BIT
NAME
DESCRIPTION
15:2
—
Reserved . A read returns 0 .
1
TACH5
This bit is set when there is an interrupt from tachometer 5 (TACH .5) .
0
TACH4
This bit is set when there is an interrupt from tachometer 4 (TACH .4) .
