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Maxim Integrated MAX31782, User Manual

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MaximIntegrated  3-1

MAX31782 User’s Guide

Revision 0; 8/11

SECTION 3: SYSTEM REGISTER DESCRIPTIONS

3 .1 System Register Bit Descriptions .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-4

3 .1 .1 Accumulator Pointer Register (AP, 8h[0h])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-4
3 .1 .2 Accumulator Pointer Control Register (APC, 8h[1h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-4
3 .1 .3 Processor Status Flags Register (PSF, 8h[4h])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-5
3 .1 .4 Interrupt and Control Register (IC, 8h[5h])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-5
3 .1 .5 Interrupt Mask Register (IMR, 8h[6h])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-6
3 .1 .6 System Control Register (SC, 8h[8h])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-6
3 .1 .7 Interrupt Identification Register (IIR, 8h[Bh])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-7
3 .1 .8 System Clock Control Register (CKCN, 8h[Eh])   .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-7
3 .1 .9 Watchdog Control Register (WDCN, 8h[Fh]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-8
3 .1 .10 Accumulator n Register (A[n], 9h[nh]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-9
3 .1 .11 Prefix Register (PFX[n], Bh[n]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-9
3 .1 .12 Instruction Pointer Register (IP, Ch[0h])   .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-9
3 .1 .13 Stack Pointer Register (SP, Dh[1h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-10
3 .1 .14 Interrupt Vector Register (IV, Dh[2h])   .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-10
3 .1 .15 Loop Counter 0 Register (LC[0], Dh[6h])   .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-10
3 .1 .16 Loop Counter 1 Register (LC[1], Dh[7h])   .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-10
3 .1 .17 Frame Pointer Offset Register (OFFS, Eh[3h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-10
3 .1 .18 Data Pointer Control Register (DPC, Eh[4h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-11
3 .1 .19 General Register (GR, Eh[5h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-11
3 .1 .20 General Register Low Byte (GRL, Eh[6h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-11
3 .1 .21 Frame Pointer Base Register (BP, Eh[7h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-12
3 .1 .22 General Register Byte-Swapped (GRS, Eh[8h])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-12
3 .1 .23 General Register High Byte (GRH, Eh[9h])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-12
3 .1 .24 General Register Sign Extended Low Byte (GRXL, Eh[Ah])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-12
3 .1 .25 Frame Pointer Register (FP, Eh[Bh])  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-12
3 .1 .26 Data Pointer 0 Register (DP[0], Fh[3h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-12
3 .1 .27 Data Pointer 1 Register (DP[1], Fh[7h]) .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-13

LIST OF TABLES

Table 3-1 . System Register Map  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-2
Table 3-2 . System Register Bit Functions  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .3-3

This section contains the following information:

Summary of Contents for MAX31782

Page 1: ...Functional Diagrams Pin Configurations appear at end of data sheet Functional Diagrams continued at end of data sheet UCSP is a trademark of Maxim Integrated Products Inc MAX31782 User s Guide Revisi...

Page 2: ...SECTION 8 I2C Compatible Master Interface 8 1 SECTION 9 PWM Outputs 9 1 SECTION 10 Fan Tachometer 10 1 SECTION 11 General Purpose Input Output GPIO Pins 11 1 SECTION 12 Timer B Module 12 1 SECTION 13...

Page 3: ...HDOG TIMER AND POWER MONITOR CKCN RST WDCN IC IC IP LOOP COUNTERS DATA POINTERS DPC MAXQ20 CORE SYSTEM MODULES REGISTERS LC n AP APC PSF IMR IIR INTERRUPT LOGIC ADDRESS GENERATION 1KWords SRAM DP 0 DP...

Page 4: ...Independent slave and master I2C compatable interfaces Six independent PWM outputs and tachometer Inputs Hardware multiplier unit 32KWords of flash and 1KWords of SRAM memory Included ROM routines th...

Page 5: ...Utility ROM 2 10 2 4 4 3 Memory Map When Executing from SRAM 2 11 2 5 Data Alignment 2 12 2 6 Reset Conditions 2 12 2 6 1 Power On Brownout Reset 2 12 2 6 2 Watchdog Timer Reset 2 13 2 6 3 External R...

Page 6: ...and data spaces and thus facilitates in system programming and fast access to data tables arrays and constants located in flash memory This section provides details on the following topics 1 Instructi...

Page 7: ...instruction set is designed to be highly orthogonal All arithmetic and logical operations that use two registers can use any register along with the accumulator Data can be transferred between any two...

Page 8: ...source module width If the source is from a module containing 8 bit or 8 bit and 16 bit source registers the source data is equal to the prefix data as the upper 8 bits and 00h as the lower 8 bits If...

Page 9: ...ack is used automatically by the processor when the CALL RET and RETI instructions are executed and when an interrupt is serviced The stack can also be used explicitly to store and retrieve data by us...

Page 10: ...0000h User program code should always begin at this address 2 4 3 Data Memory Access Data memory mapping and access control are handled by the memory management unit MMU Read write access to data mem...

Page 11: ...7 MAX31782 User s Guide Revision 0 8 11 Figure 2 2 Program Memory Mapping PROGRAM SPACE FFFFh A3FFh 8FFFh 7FFFh 3FFFh 8000h 4000h 0000h A000h 1K x 16 SRAM 4K x 16 UTILITY ROM 16K x 16 FLASH PAGE 1 16K...

Page 12: ...ts flash SRAM utility ROM The MMU can also write data directly to the SRAM memory segment Data memory can be written to the flash memory segment but because writing to flash requires the use of the ut...

Page 13: ...space The utility ROM cannot be written Figure 2 3 illustrates the mapping of the SRAM and utility ROM memory segments into data memory space when code is executing from the flash memory segment PROGR...

Page 14: ...ned by the CDA0 bit Figure 2 4 illustrates the mapping of the SRAM and flash memory segments into data memory space when code is executing from the utility ROM memory segment Figure 2 4 Memory Map Whe...

Page 15: ...sh accessed is determined by the CDA0 bit Figure 2 5 illustrates the mapping of the flash and utility ROM memory segments into data memory space when code is executing from the SRAM memory segment Fig...

Page 16: ...ompleted or been removed code execution begins at the beginning of utility ROM which is address 8000h The utility ROM code interrogates the I2C_SPE JTAG_SPE and PWL bits to determine if bootloading is...

Page 17: ...clock cycles Once the MAX31782 enters reset mode it remains in reset as long as the RST pin is held at logic 0 After the RST pin returns to logic 1 the processor exits reset within 12 clock cycles An...

Page 18: ...active during stop mode Table 2 2 details the state of the MAX31782 s analog and digital blocks during the different modes of operation The MAX31782 exits stop mode when any of the following interrupt...

Page 19: ...er Register IP Ch 0h 3 9 3 1 13 Stack Pointer Register SP Dh 1h 3 10 3 1 14 Interrupt Vector Register IV Dh 2h 3 10 3 1 15 Loop Counter 0 Register LC 0 Dh 6h 3 10 3 1 16 Loop Counter 1 Register LC 1 D...

Page 20: ...rs and control and stack pointer The peripheral registers define additional functionality and the functionality is broken up into discrete modules This section describes the MAX31782 s system register...

Page 21: ...SC TAP CDA0 ROD PWL IIR IIS II5 II4 II3 II2 II1 II0 CKCN STOP WDCN POR EWDI WD1 WD0 WDIF WTRF EWT RWT A n n 15 0 A n 16 bits PFX n n 7 0 PFX n 16 bits IP IP 16 bits SP SP 4 bits IV IV 16 bits LC 0 LC...

Page 22: ...s are set to a nonzero value the accumula tor pointer AP 3 0 is automatically incremented or decremented following each arithmetic or logical operation The mode for the auto increment decrement is det...

Page 23: ...carry out of bit 15 but not out of bit 14 from the last arithmetic operation otherwise the OV flag remains as 0 OV indicates a negative number resulted as the sum of two positive operands or a positi...

Page 24: ...0 Reserved All reads return 0 SC 1 PWL Password Lock This bit defaults to 1 on a power on reset When this bit is 1 it requires a 32 byte password to be matched with the password in the program space...

Page 25: ...odule are disabled or when the interrupt flags are cleared by software BIT FUNCTION IIR 0 II0 Interrupt Identifier Flag for Register Module 0 IIR 1 II1 Interrupt Identifier Flag for Register Module 1...

Page 26: ...elapsed or can be set to 1 by user software When WDIF 1 an interrupt request occurs if the watchdog interrupt has been enabled EWDI 1 and not otherwise masked or prevented by an interrupt already in...

Page 27: ...after which it reverts to 0000h Although this is a 16 bit register only the lower 8 bits are actually used for prefixing purposes by the next instruction Writing to or reading from any index in the pr...

Page 28: ...ted before a value is popped from the stack SP 15 4 Reserved All reads return 0 BIT FUNCTION IV 15 0 This register contains the address of the interrupt service routine The interrupt handler generates...

Page 29: ...FS changes the setting of the SDPS bits to reflect the active source pointer selection DPC 2 WBS0 Word Byte Select 0 This bit selects access mode for DP 0 When WBS0 is set to logic 1 the DP 0 is oper...

Page 30: ...BIT FUNCTION BP 15 0 This register serves as the base pointer for the frame pointer FP The frame pointer is formed by unsigned addi tion of frame pointer base register BP and frame pointer offset reg...

Page 31: ...is cleared to 0000h on all forms of reset Access Unrestricted direct read write access BIT FUNCTION DP 1 15 0 This register is used as a pointer to access data memory DP 1 can be automatically increm...

Page 32: ...PWMC2 MCNT 01h PO1 I2CST_M I2CST_S PWMR0 PWMR2 MA 02h I2CIE_M I2CIE_S PWMC1 PWMC3 MB 03h MIIR0 PO6 MIIR2 PWMR1 PWMR3 MC2 04h MIIR1 SMBUS MC1 05h TACHR0 TACHR2 MC0 06h TB0C EIF6 ADST MC1R 07h TB0R EIE6...

Page 33: ...IE I2CNACKIE I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE PO6 03h PO6_7 PO6_6 PO6_4 PO6_3 PO6_2 PO6_1 PO6_0 MIIR1 04h I2CM_WU I2CM P6_7 P6_6 SVM P6_4 P6_3 P6_2 P6_1 P6_0 EIF6 06h IFP6_7 IFP6_6 IFP...

Page 34: ...TOP I2CSTART I2CACK I2CSTRS I2CMODE I2CMST I2CEN I2CCK_S 0Dh I2CCKH 7 0 I2CCKL 7 0 I2CTO_S 0Eh I2CTO 7 0 I2CSLA_S 0Fh A 6 0 I2C_SPB 15h I2C_SPE DEV_NUM 16h DEVICE NUMBER 7 0 ICDT0 18h ICDT0 15 0 ICDT1...

Page 35: ...CHCN3 0Fh TRPS 1 0 TPS 2 0 TF TEXF TEXEN TACHE TACHIE MIIR4 10h TACH3 TACH2 MODULE 5 REGISTER INDEX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCNT 00h OF MCW CLD SQU OPCS MSUB MMAC SUS MA 01h MA 15 0 MB 0...

Page 36: ...M2 03h 5 6 5 2 4 Peripheral Module 3 Interrupt Identification Register MIIR3 M3 10h 5 6 5 2 5 Peripheral Module 4 Interrupt Identification Register MIIR4 M4 10h 5 6 5 2 6 Peripheral Module 5 Interrupt...

Page 37: ...a single instruction This promotes a simple fast and user definable interrupt prioritization scheme The interrupt source enable hierarchy is illustrated in Figure 5 1 as well as Table 5 1 When an int...

Page 38: ...ABLE I2CIE_M x OVERFLOW TB0CN TFB LOCAL ENABLE TB0CN ETB SVM INTERRUPT SVM SVMI SVM INTERRUPTS LOCAL ENABLE SVM SVMIE IIR II3 IMR IM3 MODULE 3 ENABLE OVERFLOW TACHCN0 TF TACHOMETER 0 INTERRUPTS MODULE...

Page 39: ...EIE6 IEP6_7 MIIR1 P6_7 Supply Voltage Monitor Interrupt SVM SVMI SVM SVMIE MIIR1 SVM I2C Slave START Interrupt I2CST_S I2CSRI I2CIE_S I2CSRIE MIIR2 I2CS IIR II2 IMR IM2 I2C Slave Transmit Complete Int...

Page 40: ...is set when an interrupt is generated by the Timer Counter B module Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I2CM_WU I2CM P6_7 P6_6 SVM P6_4 P6_3 P6_2 P6_1 P6_0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 41: ...nterrupt I2CSRI Once set this bit is cleared by clearing the I2CST_S I2CSRI bit 1 I2CS This bit is set when there is an interrupt from the I2C slave block The I2C interrupt is a combina tion of all in...

Page 42: ...xecution of RETI involves the following sequence of actions 1 The return address is popped off the stack 2 The INS bit is cleared to 0 to re enable interrupt handling 3 The instruction pointer is set...

Page 43: ...terrupt exception window is a noninterruptable execution cycle During this cycle the interrupt handler does not respond to any interrupt requests All interrupts that would normally be serviced during...

Page 44: ...DATA when ADCFG 1 6 8 6 2 4 2 ADC Data Buffer ADDATA when ADCFG 0 6 9 6 2 5 External Temperature Slope Control Register ETS 6 10 6 2 6 ADC External Temperature Offset Register TOEX 6 11 6 2 7 ADC Volt...

Page 45: ...internal reference is used the ADC full scale can be set to either 1 225V ADGAIN 0 or 5 5V ADGAIN 1 When an external reference is desired the reference supply needs to be connected to pin AD3N See 6 1...

Page 46: ...remains set until the ADC has finished conversion on the last channel in the sequence In continuous mode ADCONT 1 the ADCONV bit remains set until the continuous mode is stopped Writing a 0 to the ADC...

Page 47: ...les A temperature conversion requires that this integration and conversion process be performed twice The extended acquisition time function does not apply when in temperature sensing mode The time re...

Page 48: ...r a sequence that uses only one configuration register ADSTART ADEND setting ADDAINV 00 generates an interrupt with the same interval as ADDAINV 01 In both cases the ADDAI flag is set after every samp...

Page 49: ...ADDAI AT 00 Every ADC sample 01 End of every sequence ADSTART to ADEND 10 Every 12 ADC samples 11 Every 16 ADC samples 9 8 Reserved The user should not write to these bits 7 IREFEN Internal Reference...

Page 50: ...auses an interrupt if the ADDAIE is enabled This bit is cleared by software writing a 0 or when software changes ADCONV bit from 0 to 1 4 ADCFG ADC Conversion Configuration Register Select This bit se...

Page 51: ...ng of this bit For external temperature measurement the ADC does the following A current source generated on the chip is directed to one of six positive ADC channel pins AD0P AD5P based on channel sel...

Page 52: ...mode this bit selects the ADC conversion mode When this bit is set to 1 the ADC conversion is in differential mode When this bit is cleared to 0 the ADC conversion is performed in single ended mode Du...

Page 53: ...en the external diodes are at room temperature The ETS register should only be set to the values shown in Table 6 4 Table 6 4 ETS Register Settings Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ETS7...

Page 54: ...ence voltage is set to 1 215V and cannot be changed by the user When using the internal reference ADCG1 and ADCG5 are factory calibrated to produce ADC full scale levels of 1 225V and 5 5V respectably...

Page 55: ...Right Aligned ADDATA 0x85 ADCFG 2 External temperature CH5 right aligned ADDATA 0x86 ADCFG 3 Internal temperature CH6 right aligned ADADDR_bit ADSTART 0 start sequence with ADCFG 0 ADADDR_bit ADEND 3...

Page 56: ...X 0 ADIDX 0 set to ADCFG 0 ADDATA 0x08 ADCFG 0 Differential voltage ch0 1 225V FS Right Aligned ADADDR 0x0000 ADSTART 0 ADEND 0 sequence is only ADCFG 0 ADST_bit ADDAI 0 clear the interrupt flag ADST_...

Page 57: ...as a Master 7 7 7 1 12 GPIO 7 7 7 2 I2C Slave Controller Register Descriptions 7 8 7 2 1 I2C Slave Control Register I2CCN_S 7 8 7 2 2 I2C Slave Status Register I2CST_S 7 9 7 2 3 I2C Slave Interrupt En...

Page 58: ...aded are shown in more detail in Figure 7 2 Figure 7 1 Slave I2C Flow 7 1 Detailed Description 7 1 1 Default Operation The I2C slave controller is enabled I2CCN_S I2CEN 1 by default As long as the I2C...

Page 59: ...2CSPI bit in the I2CST_S register which can cause an interrupt if enabled The I2CBUS bit is cleared to 0 following a STOP to indicate that the I2C bus is no longer busy 7 1 5 Slave Address Matching Fo...

Page 60: ...lave control ler samples the acknowledge bit following the rising 9th SCL rising edge After the acknowledge bit is sampled the MAX31782 I2C slave controller performs the following tasks Sets the I2CST...

Page 61: ...ve controllers attempt to copy the shift register to I2CBUF_S 1 If I2CBUF_S is empty the I2C slave controller copies the data from the shift register into I2CBUF_S The I2CRXI flag is set to indicate a...

Page 62: ...slave controller needs to either read the received byte from I2CBUF_S or write the next byte to transmit to I2CBUF_S Without using clock stretching the host can begin clocking the next byte before th...

Page 63: ...ler The I2C slave controller can be reset by setting the RESET_S bit in the SMBUS register After a delay of at least one system clock this bit needs to be cleared to 0 by software and the reset is com...

Page 64: ...the I2C to respond to a general call address address 0000 0000 Clearing this bit to 0 disables the response to general call address 7 I2CSTOP This bit has no function when operating in slave mode 6 I...

Page 65: ...is bit must be cleared to 0 by software once set Setting this bit to 1 by software causes an interrupt if enabled 7 I2CNACKI I2C Slave NACK Interrupt Flag This bit is set by hardware to either a 1 if...

Page 66: ...KI 1 Clearing this bit to 0 disables the NACK detection interrupt 6 Reserved The user should not write to this bit 5 I2CAMIE I2C Slave Address Match Interrupt Enable Setting this bit to 1 causes an in...

Page 67: ...face When a match to this address is detected the I2C controller automatically acknowledges the host with the I2CACK bit value and the I2CAMI flag is set to 1 An interrupt is generated if enabled The...

Page 68: ...used by the software to unconditionally reset and disable the I2C slave interface After at least one system clock cycle this bit must be cleared by software After this bit is toggled all the relevant...

Page 69: ...C Master Controller Register Descriptions 8 9 8 2 1 I2C Master Control Register I2CCN_M 8 9 8 2 2 I2C Master Status Register I2CST_M 8 10 8 2 3 I2C Master Interrupt Enable Register I2CIE_M 8 11 8 2 4...

Page 70: ...setting the clock rate timeout period and which I2C events should generate interrupts The MAX31782 master I2C controller is not intended to be used on an I2C bus that has multiple masters connected to...

Page 71: ...egister to 0 The I2C timeout timer starts counting When the I2CSTART bit is set to 1 The I2C controller monitors the status of SDA and SCL until it can generate a START condition If the controller has...

Page 72: ...busy the I2C master controller attempts to generate a START Because the SDA line is feedback into the device when the master generates a START it can also detect the START condition When a start condi...

Page 73: ...e the STOP condition it will also start the timeout timer if this feature is enabled If a timeout is generated before the STOP condition is detected a timeout will occur When a timeout occurs the I2CT...

Page 74: ...mode after transmitting a slave address with the R W bit I2CMODE set to a 0 The steps of data transmission are shown in Figure 8 5 Data transmission is started by software loading a byte of data into...

Page 75: ...enabled 2 If I2CBUF_M is full the data in the shift register cannot be copied into I2CBUF_M This causes a receive overrun condition The receive overrun flag I2CROI will be set which can generate an in...

Page 76: ...vices may be in an unknown state It is recommended that the master I2C controller attempts to reset the slave devices prior to beginning communication A reset of slave devices can be performed by outp...

Page 77: ...tion has been generated The setting of I2CSTOP starts the timeout timer if enabled If the timeout timer expires before the STOP condition is generated the I2CTOI flag is set which can generate an inte...

Page 78: ...This bit has no function when operating in master mode 7 I2CNACKI I2C Master NACK Interrupt Flag This bit is set by hardware to a 1 if a NACK was received from a slave or a 0 if an ACK was received fr...

Page 79: ...not write to this bit 5 I2CAMIE This bit has no function when operating in master mode 4 I2CTOIE I2C Master Timeout Interrupt Enable Setting this bit to 1 enables an interrupt when a timeout condi ti...

Page 80: ...I2CCKL5 I2CCKL4 I2CCKL3 I2CCKL2 I2CCKL1 I2CCKL0 Reset 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 Access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw BIT NAME DESCRIPTION 15 8 I2CCKH 7 0 These bits define the...

Page 81: ...TION 15 4 Reserved The user should not write to these bits 3 RESET_S This bit does not affect the master I2C interface MSDA and MSCL 2 RESET_M I2C Master Reset Bit This bit can be used by the software...

Page 82: ...PWMCNn 9 6 9 2 2 PWM Value Register PWMVn 9 7 9 2 3 PWM Reload Register PWMRn 9 7 9 2 4 PWM Compare Register PWMCn 9 7 9 2 5 PWM Register Locations 9 7 9 3 PWM Output Code Example 9 7 LIST OF TABLES T...

Page 83: ...s shown in Figure 9 1 Figure 9 1 PWM Output Block Diagram PWMPS 2 0 15 PWMCn 0 15 0 001 010 011 100 101 11x 000 SYSTEM CLOCK 4 SYSTEM CLOCK 16 SYSTEM CLOCK 64 SYSTEM CLOCK 256 SYSTEM CLOCK 1024 SYSTEM...

Page 84: ...utput Modes The PWM can provide up to 16 bit resolution of the frequency or duty cycle A timed setting or clearing of the PWM n pin can also be generated without the need for the MAX31782 to time the...

Page 85: ...ates the PWM waveforms when the PWM is operating with DCEN 0 The period of the PWM waveform is set by the value in the PWMRn register The set and reset modes provide similar functionality The formulas...

Page 86: ...olution In set mode the duty cycle is always less than 50 and in reset mode the duty cycle is always greater than 50 The toggle mode provides a center aligned 16 bit PWM with twice the period of the n...

Page 87: ...WMEN 0 and what compare mode output function is used 10 8 PWMPS 2 0 PWM Clock Prescaler Bits These bits select the clock prescaler applied to the system clock which is then used as the PWM clock The P...

Page 88: ...f PWM operation the PWM n pin is driven high or low when a match between PWMVn and PWMCn occurs This register is cleared to 0000h on all forms of reset and has unrestricted read write access 9 2 5 PWM...

Page 89: ...Tachometer Value Register TACHVn 10 5 10 2 3 Tachometer Capture Register TACHRn 10 5 10 2 3 Tachometer Register Locations 10 5 10 3 Tachometer Pin and GPIO Multiplexing 10 5 10 4 Tachometer Code Examp...

Page 90: ...ck Diagram CLOCK PRESCALER TEXF 0000h TACHVn REGISTER TACHRn REGISTER 15 0 15 0 TF TACHIE TACHOMETER INTERRUPT SYSTEM CLOCK TACHE CAPTURE TACH n PIN REVOLUTION PRESCALER TEXEN TPS 2 0 000 001 010 011...

Page 91: ...lock counts for the fan revolution When a capture is triggered the following occurs 1 The value in the TACHV counter register is copied to the capture register TACHR 2 The TACHV register is reset to 0...

Page 92: ...100 Sysclk 256 101 Sysclk 1024 11x Sysclk 1 7 TF Overflow Flag This bit is set when the tachometer s TACHV register overflows from FFFFh to 0000h An interrupt will be generated if TACHIE 1 This flag...

Page 93: ...access 10 2 3 Tachometer Register Locations The addresses for the tachometer registers are given as Mx yy where x is the module number from 0 to 5 decimal and yy is the register index from 00h to 1Fh...

Page 94: ...captured tachometer value can be periodically polled by software Tachometer setup TACHCN0_bit TPS 3 tachometer clock is sysclk 64 or 62 5kHz TACHCN0_bit TRPS 1 set for 2 pulses per revolution TACHCN0_...

Page 95: ...nput Register for Port 2 PI2 11 5 11 3 GPIO Port 6 Register Descriptions 11 6 11 3 1 GPIO Direction Register Port 6 PD6 11 6 11 3 2 GPIO Output Register Port 6 PO6 11 6 11 3 3 GPIO Input Register for...

Page 96: ...pin s output state can still be controlled by the GPIO register settings or driven by external hardware Table 11 1 details all the GPIO pins as well as what other functions are multiplexed with each...

Page 97: ...24 PWM 2 P1 2 PWM 2 PWMCN2 PWMCR or PWMCS 1 GPIO 20 PWM 3 P1 3 PWM 3 PWMCN3 PWMCR or PWMCS 1 GPIO 18 PWM 4 P1 4 PWM 4 PWMCN4 PWMCR or PWMCS 1 GPIO 16 PWM 5 P1 5 PWM 5 PWMCN5 PWMCR or PWMCS 1 GPIO 30...

Page 98: ...the port 1 pins are operating as PWM pins the data in PD1 does not affect PWM operation 11 1 2 GPIO Output Register Port 1 PO1 PO1 is an 8 bit register that controls the output data of a GPIO pin If...

Page 99: ...en functioning as an input The p channel pullup transistor is controlled by the PO2 n bit If PO2 n is set to 1 the corresponding weak pullup is turned on if the PO2 n bit is cleared to 0 the weak pull...

Page 100: ...cial or alternate function Three additional registers EIF6 EIE6 and EIES6 are used to control the GPIO interrupts 11 3 1 GPIO Direction Register Port 6 PD6 PD6 is an 8 bit register used to determine t...

Page 101: ...when a negative edge IESP6 n 1 or a positive edge IESP6 n 0 is detected on the P6 n pin Setting any of the bits to 1 generates an interrupt to the CPU if the corresponding interrupt is enabled These b...

Page 102: ...set direction PD6 4 to 1 for an output PO6 0x10 set the output PO6 4 high set pin 6 4 as a high impedance input PD6 0x10 set direction PD6 4 to 0 for input PO6 0x10 set PO6 4 low to disable weak pullu...

Page 103: ...1 12 2 4 Timer B Compare Register TB0C 12 11 12 3 Timer B Code Examples 12 12 12 3 1 Auto Reload Mode 12 12 12 3 2 Clock Output Mode 12 12 12 3 3 PWM Output Mode 12 12 LIST OF TABLES Table 12 1 Timer...

Page 104: ...e Timer B control register to 1 If this bit is cleared to 0 reset default condition no timer activity is possible When the Timer B is operated as a timer i e it counts scaled system clocks the TBPS 2...

Page 105: ...ontained in the TB0V register When the value in the TB0V register reaches the value in the capture reload register TB0R the TFB flag is set to 1 which can generate an interrupt if enabled Also when th...

Page 106: ...eloads with a value of 0000h and continues counting When the timer is counting down and an underflow occurs the TB0V register reaches 0000h the TB0V register is reloaded with the value in the TB0R reg...

Page 107: ...overflow flag TFB is set which can generate an interrupt if enabled After an overflow the timer continues counting upward This counting is repeated without processor intervention until the timer is d...

Page 108: ...B Clock 2 TB0R 1 where Timer B clock is the prescaled version of the system clock The prescaler is set using the TBPS 2 0 bits In clock output mode the setting of the TFB overflow flag does not cause...

Page 109: ...the detection of a falling edge on the TBB pin results in the setting of the EXFB interrupt flag but does not force an auto reload A timed setting or clearing of the TBB pin can also be generated wit...

Page 110: ...utput mode The period of the PWM waveform is set by the value in the TB0R register The set and reset modes provide similar functionality The formulas for period and duty cycle are PWM PERIOD TB0R 1 TI...

Page 111: ...bit resolution In set mode the duty cycle is always less than 50 and in reset mode the duty cycle is always greater than 50 The toggle mode provides a center aligned 16 bit PWM with twice the period o...

Page 112: ...e system clock which is then used as the Timer B clock The TBPS 2 0 bits should be configured by the user when the timer is stopped TRB 0 While hardware does not prevent changing the TBPS 2 0 bits whe...

Page 113: ...tion as either a standard GPIO pin or a counter input for the Timer B 4 DCEN Down Count Enable In the compare modes the DCEN bit controls whether the timer counts up and resets DCEN 0 or counts up and...

Page 114: ...operation 12 3 2 Clock Output Mode Creating a 100kHz clock on the TBA pin TB0CN_bit CPnRLB 0 clear for reload TB0CN_bit TBPS 1 prescaler divide sysclk 4 for 1MHz Timer B Clock TB0R 4 set for 100 kHz o...

Page 115: ...V increments The default value is 00h 2 3V Supply Voltage Monitor Threshold 2 3V SVTH 3 0 x 0 2V Note that the SVTH 3 0 bits can only be modified when SVMEN 0 Writing to these bits is ignored if SVMEN...

Page 116: ...5 1 Multiplier Control Register MCNT 14 6 14 5 2 Multiplier Operand A Register MA 14 7 14 5 3 Multiplier Operand B Register MB 14 7 14 5 4 Multiplier Accumulator 2 Register MC2 14 7 14 5 5 Multiplier...

Page 117: ...re functions Signed or Unsigned Multiply 16 bit x 16 bit Signed or Unsigned Multiply Accumulate 16 bit x 16 bit Signed or Unsigned Multiply Subtract 16 bit x 16 bit Signed Multiply and Negate 16 bit x...

Page 118: ...to 1 for a signed operation the SUS bit must be cleared to 0 The multiplier treats unsigned numbers as absolute magnitude For a 16 bit positional binary number this represents a value in the range 0...

Page 119: ...ould either reload that same operand register or use the CLD bit in the MCNT register to reinitialize the multiplier otherwise loading data to another operand register triggers the calculation The CLD...

Page 120: ...M5 03h Multiplier Accumulate Register 2 Contains the two most significant bytes of the accumulator register The 48 bit accumulator is formed by MC2 MC1 and MC0 The most significant bit of this regist...

Page 121: ...c 0 the hardware square function is disabled 0 Square function disabled 1 Square function enabled 3 OPCS Operand Count Select This bit defines how many operands must be loaded to trigger a multiply or...

Page 122: ...he accumulator register The 48 bit accumulator is formed by MC2 MC1 and MC0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name MA 15 MA 14 MA 13 MA 12 MA 11 MA 10 MA 9 MA 8 MA 7 MA 6 MA 5 MA 4 MA 3 MA 2 M...

Page 123: ...this register can change if MCNT MA MB or MC 2 0 is changed 14 6 Hardware Multiplier Examples The following are code examples of multiplier operations Unsigned Multiply 16 bit x 16 bit move MCNT 21h...

Page 124: ...00_0100_0001h move MCNT 07h MMAC 1 MSUB 1 SUS 1 unsigned move MA 0FFFh move MB 1001h MC1R MC0R FF00_0003h MC2 0 0000_0000_0002h Signed Multiply Subtract 16 bit x 16 bit MC2 0 0000_0100_0001h move MCNT...

Page 125: ...hdog Timer Interrupt Operation 15 3 15 1 2 Watchdog Timer Reset Operation 15 3 15 1 3 Watchdog Timer Applications 15 3 15 2 4 Watchdog Timer Control Register WDCN 15 4 LIST OF TABLES Table 15 1 Watchd...

Page 126: ...ion is enabled When the watchdog timer is initially enabled there is a one clock to three clock cycle delay before it starts The divider output is selectable and determines the interval between timeou...

Page 127: ...upt during software development can allow the user to select ideal watchdog reset locations Code is first developed without enabling the watchdog interrupt or reset functions Once the program is compl...

Page 128: ...s elapsed or can be set to 1 by user software When WDIF 1 an interrupt request occurs if the watchdog interrupt has been enabled EWDI 1 and not otherwise masked or prevented by an interrupt already in...

Page 129: ...TAP Communication Examples IR Scan and DR Scan 16 6 LIST OF TABLES Table 16 1 Test Access Port Pins 16 2 Table 16 2 Instruction Register Content vs TAP Controller State 16 4 Table 16 3 Instruction Re...

Page 130: ...SC 7 bit to 0 This disables the TAP JTAG interface and allows the four pins to operate as normal port pins See Figure 16 1 Figure 16 1 TAP and TAP Controller EXTERNAL PIN SIGNAL FUNCTION TDO Test Dat...

Page 131: ...o 1 8 the system clock frequency This section provides a brief description of the state machine and its state transitions The state diagram in Figure 16 2 summarizes the transitions caused by the TMS...

Page 132: ...ng to one of the two state sequences in which the controller performs meaningful operations Controller state sequence IR Scan or Data register state sequence DR Scan 16 2 3 IR Scan Sequence The contro...

Page 133: ...is formed between the TDI and TDO pins in the Shift DR state If the System Programming instruction is entered into the instruction register IR 2 0 a 3 bit serial data shift register is formed between...

Page 134: ...annel is established In circuit debug or in system programming commands and data can be exchanged between the host and the MAX31782 by operating in the data register portion of the state sequence i e...

Page 135: ...REGISTER TCK TMS TDI TDO CONTROL STATE SHIFT REGISTER PARALLEL OUTPUT INSTRUCTION REGISTER TDO ENABLE DON T CARE OR UNDEFINED DON T CARE OR UNDEFINED DON T CARE OR UNDEFINED TEST LOGIC RESET RUN TEST...

Page 136: ...2 5 Debug Mode Special Considerations 17 12 17 3 In Circuit Debug Peripheral Registers 17 13 17 3 1 In Circuit Debug Temp 0 Register ICDT0 M2 18h 17 13 17 3 2 In Circuit Debug Temp 1 Register ICDT1 M2...

Page 137: ...the embedded debug engine to debug the actual sys tem in place of the in circuit emulator that uses external hardware to duplicate operation of the microcontroller outside of the real application envi...

Page 138: ...BP0 BP5 read write internal in circuit debug registers ICDC ICDF ICDA ICDD monitor to determine when a breakpoint match has occurred directly invoke debug mode Table 17 2 shows the background mode co...

Page 139: ...e ICDB register for host read This command requires two follow on transfer cycles with the least significant byte first 0001 0001 Write ICDC Write control data to the ICDC The contents of ICDB are loa...

Page 140: ...he breakpoint 1 register is accessible only via background mode read write commands Breakpoint registers BP0 BP1 BP2 and BP3 serve as program memory address breakpoints When DME bit is set in backgrou...

Page 141: ...by the M 3 0 bits and the register within that module is defined by the R 4 0 bits 17 1 1 6 Breakpoint 5 Register BP5 The breakpoint 5 register is accessible only via background mode read write comma...

Page 142: ...ode if register breakpoints are to remain enabled When a breakpoint match occurs the debug engine forces a break and the MAX31782 enters Debug Mode If a break point match occurs on an instruction that...

Page 143: ...the debug engine has received the proper number of command and follow on bytes for a given ROM assisted operation it responds with the following actions Updates the command bits CMD 3 0 in the ICDC r...

Page 144: ...ed off the stack and returned in descending order 0010 0100 Write register Write data to a selected register This command requires four follow on transfer cycles two for the register address and two f...

Page 145: ...d and reserved peripheral registers in the range M0 00h to M5 17h are represented as empty word values in Table 17 4 These values should be ignored The first byte output by this command is the value 1...

Page 146: ...MB 194 A 5 3 MIIR0 35 PO6 67 MIIR2 99 PWMR1 131 PWMR3 163 MC2 195 A6 4 36 MIIR1 68 100 SMBUS 132 164 MC1 196 A 7 5 37 69 101 TACHR0 133 TACHR2 165 MC0 197 A 8 6 TB0C 38 EIF6 70 ADST 102 134 166 MC1R...

Page 147: ...ollowing are special considerations when using debug mode Special caution should be exercised when using the Write Register command on register bits that globally affect system operation e g IGE STOP...

Page 148: ...l restrictions or conditions that could apply when reading or writing this bit are detailed in the bit description 17 3 1 In Circuit Debug Temp 0 Register ICDT0 M2 18h This register is read write acce...

Page 149: ...BP5 are used as register breakpoints A break occurs when the content of BP4 is matched with the destination address of the current instruction For BP5 a break occurs only on a selected data pattern f...

Page 150: ...JTAG_SPE bit is used for In System programming support and its logical state when read by the CPU always reflects the logical OR of the JTAG_SPE bit that is write accessible by the CPU and the SPE bit...

Page 151: ...atches the destination register address of the current instruction 17 3 7 In Circuit Debug Data Register ICDD M2 1Eh This register is used by the debug engine to store data or read count so that ROM c...

Page 152: ...18 3 5 Command 04h Get Status 18 9 18 3 6 Command 05h Get Supported Commands 18 10 18 3 7 Command 06h Get Code Size 18 10 18 3 8 Command 07h Get Data Size 18 10 18 3 9 Command 08h Get Loader Version 1...

Page 153: ...Bootloader Status Bits 18 5 Table 18 3 Special Functions of Address 34h 18 5 Table 18 4 Example Bootload Command 18 6 Table 18 5 Command Families 18 8 Table 18 6 Bootloader Status Flags 18 9 Table 18...

Page 154: ...termines if the MAX31782 should enter into a bootloader mode First the ICDF register which is not cleared by a reset is read to see if the system programming enable SPE bit is set See 18 1 2 Entering...

Page 155: ...has occurred When a password match occurs the PWL bit is cleared to 0 When bootloading the device the password can be matched using the Password Match command through either the JTAG or I2C interface...

Page 156: ...update the firmware using only the I2C bus without JTAG or firmware intervention To access the bootloading function slave address 34h is used This slave address is setup by hardware and cannot be chan...

Page 157: ...bytes that are input to the bootloader that are required for the command The number of Data In bytes var ies for each command Some commands do not require any Data In bytes NOP The NOP byte is only u...

Page 158: ...s 4 The NOP byte is not required for the I2C interface Sending a NOP byte when using the I2C bootloader places the bootloader into an unknown state Instead an I2C restart needs to be issued followed b...

Page 159: ...operation all bytes of data listed for the command must be written or read from the bootloader This includes the Return byte and for the I2C bootloader the Dummy RX byte If all bytes are not read the...

Page 160: ...on occurs and only reflect the last error The Status Codes are cleared When the bootloader is initially entered At the start of execution of all commands except Familiy 0 commands At the start of exec...

Page 161: ...t Data Out Data Out Return Dummy RX Input 05h 00h 00h 00h 00h 00h 00h 00h Output X X SupportL SupportH 00h 00h 3Eh X Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Command NOP Data Out Data Out Return Dumm...

Page 162: ...e The MAX31782 uses a little endian memory architecture where the least significant byte of each word is loaded first For example if you load bytes 11h 22h 33h 44h starting at address 0000h the first...

Page 163: ...of each word is loaded first For example if you load bytes 11h 22h 33h 44h starting at address 0000h the first two words of memory space are written to 2211h 4433h This command is password protected 1...

Page 164: ...ion is complete 18 3 18 Command 40h Verify Code This command operates in the same manner as the Load Code command except that instead of programming the input data into flash memory it verifies that t...

Page 165: ...and This command is password protected 18 3 22 Command E0h Code Page Erase This command erases programs to FFFFh all words in a 256 word 512 byte page of the program flash memory The MAX31782 has 128...

Page 166: ...Source 19 8 19 5 4 ALU Operations Using Only the Active Accumulator 19 8 19 5 5 ALU Bit Operations Using Only the Active Accumulator 19 9 19 5 6 Example Adding Two 4 Byte Numbers Using Auto Increment...

Page 167: ...31782 are 16 bits long and execute in a single cycle However some operations require more data than can be specified in a single cycle or require that high order register index bits be set to achieve...

Page 168: ...0h move WDCN 80h 33h 19 3 2 Loading a 16 Bit Register with a 16 Bit Immediate Value Any writable 16 bit register with a sub index from 0h to 07h can be loaded with an immediate value in a single cycle...

Page 169: ...se the GR register Transferring the 16 bit source to the GR register adds a single cycle move GR LC 0 move LC 0 to the GR register move IC GRH copy the high byte into the IC register 16 bit destinatio...

Page 170: ...VE instruction can also be used to directly set or clear any one of the lowest 8 bits of a peripheral register in module 0h 5h or a system register in module 8h The set or clear operation will not aff...

Page 171: ...each arithmetic or logical opera tion This is useful for operations involving a number of accumulator registers such as adding or subtracting two mul tibyte integers If auto increment decrement is en...

Page 172: ...as selects the range of bits modulo in the AP register that will be incremented or decremented There are nine different unique settings for the APC register as listed in Table 19 1 Table 19 1 Accumul...

Page 173: ...h Acc Acc 0032h Carry sub A 15 Acc Acc A 15 subb A 1 Acc Acc A 1 Carry cmp 00h If Acc 0000h set Equals flag and A 0 Acc Acc AND A 0 or 55h Acc Acc OR 0055h xor A 1 Acc Acc XOR A 1 19 5 4 ALU Operation...

Page 174: ...hich can also be used for conditional program branching 19 6 1 Sign Flag The Sign flag PSF 6 reflects the current state of the most significant bit of the active accumulator If signed arithmetic is be...

Page 175: ...ce to active accumulator ADDC src Add source and Carry to active accumulator SUB src Subtract source from active accumulator SUBB src Subtract source and Carry from active accumulator SLA SLA2 SLA4 Ar...

Page 176: ...t in counters and address registers are provided to control looping operations 19 7 1 Obtaining the Next Execution Address The address of the next instruction to be executed can be read at any time by...

Page 177: ...Acc 0 jump s A 2 jump to A 2 if Sign flag is set jump e Label1 jump to Label1 if Equal is set jump ne Label1 jump to Label1 if Equal is cleared JUMP E and JUMP NE may only use immediate destinations...

Page 178: ...C 1 LoopTop decrement LC 1 and jump if nonzero When the supplied loop address is outside the relative jump range the prefix register PFX 0 is used to supply the high byte of the loop address as requir...

Page 179: ...be handled the IGE bit in the Interrupt and Control register IC must first be set to 1 Next the interrupt itself must be enabled at the module level and locally within the module itself The module int...

Page 180: ...g module or system from generating an interrupt request Configuring an IMR mask bit to 0 does not prevent the cor responding IIR system or module identification flag from being set This means that whe...

Page 181: ...0 Thus the following two instructions would be equivalent popi IP reti The SP mnemonic can be used by the MAX31782 so that stack values may be used directly by ALU operations e g ADD src XOR src etc w...

Page 182: ...me Pointer offset register OFFS is implemented internally as a 9 bit register e g 8 0 The WBSn bit for the respective pointer controls whether the highest 16 bits 16 1 of the pointer are in use as is...

Page 183: ...lect DP 0 as the active pointer To simplify data pointer increment decrement operations without disturbing register data a virtual NUL destination has been assigned to system module 6 sub index 7 to s...

Page 184: ...1 1010 C Z Y SRA2 Shift Acc right arithmetically twice 1000 1010 1110 1010 C Z Y SRA4 Shift Acc right arithmetically four times 1000 1010 1011 1010 C Z Y SR Shift Acc right 0 msbit 1000 1010 1010 1010...

Page 185: ...OTES BRANCHING L S JUMP src IP IP src or src f000 1100 ssss ssss 6 L S JUMP C src If C 1 IP IP src or src f010 1100 ssss ssss 6 L S JUMP NC src If C 0 IP IP src or src f110 1100 ssss ssss 6 L S JUMP Z...

Page 186: ...ster is used to supply the high byte of data for 16 bit sources Status Flags C S Z OV ADD Operation Acc Acc src Encoding 15 0 f100 1010 ssss ssss Example s Acc 2345h for each example ADD A 3 A 3 FF0Fh...

Page 187: ...AND A 3 A 3 0F0Fh Acc 0305h S 0 Z 0 AND 33h Acc 0001h AND 2233h generates object code below MOVE PFX 0 22h smart prefixing AND 33h Acc 2201h MOVE PFX 0 0Fh AND M0 8 M0 8 0Fh assume M0 8 is an 8 bit re...

Page 188: ...te a relative short call but is flagged by the assembler if the destination is out of range Specifying an internal register src always produces an absolute CALL to a 16 bit address thus the L and S pr...

Page 189: ...ces Status Flags E Operation Acc src E 1 Acc src E 0 Encoding 15 0 f111 1000 ssss ssss Example s CMP 45h Acc 0145h E 0 CMP 145h PFX 0 register used MOVE PFX 0 01h smart prefixing CMP 45h E 1 CPL Compl...

Page 190: ...eg ister The DJNZ LC n src instruction decrements the LC n loop counter and branches to the address defined by src if the decremented counter has not reached 0000h Program branches can be relative or...

Page 191: ...nerate a relative short jump but will be flagged by the assembler if the destination is out of range Specifying an internal register src always produces an absolute JUMP to a 16 bit address thus the L...

Page 192: ...et while JUMP NE branches if the Equal flag is clear JUMP S results in a branch if the Sign flag is set Program branches can be relative or absolute depending upon the src specifier and may be qualifi...

Page 193: ...ncoding 15 0 0011 1100 ssss ssss Example s JUMP E label1 E 1 branch taken Special Notes The src specifier must be immediate data JUMP NE Operation E 0 IP IP src relative or src absolute E 1 IP IP 1 En...

Page 194: ...ol Register WDCN 1 1111 1000 8 Watchdog Control Register A n 1 nnnn 1001 16 nnnn Selects One of 16 Accumulators Acc 1 0000 1010 16 Active Accumulator A AP Update AP per APC A AP 1 0001 1010 16 Active...

Page 195: ...First 8 Accumulators A 0 A 7 Acc 000 1010 16 Active Accumulator A AP PFX n nnn 1011 8 nnn Selects One of 8 Prefix Registers SP 000 1101 16 16 Bit Word SP Pre Increment SP SP 001 1101 16 Stack Pointer...

Page 196: ...the assembler and is therefore an optional step for the user when writing assembly source code Examples of the automatic PFX n code insertion by the assembler are demonstrated below Initial Assembly C...

Page 197: ...ample s Acc 01C0h C 0 MOVE C Acc 8 C 1 MOVE C src b Move Bit to Carry Flag Description Replaces the Carry C status flag with the specified source bit src b Status Flags C Operation C src b Encoding 15...

Page 198: ...SF S Z Operation dst b 0 Encoding 15 0 1ddd dddd 0bbb 0111 Example s M0 0 FEh MOVE M0 0 1 0 M0 0 FCh MOVE M0 0 7 0 M0 0 7Ch Special Notes Only system module 8 and peripheral modules 0 5 are supported...

Page 199: ...Performs a logical OR between the active accumulator Acc or A AP and the specified src data For the complete list of src specifiers reference the MOVE instruction Because the source is lim ited to 8 b...

Page 200: ...ncoding 15 0 1010 1010 bbbb 1010 Example s Acc 2345h C 0 at start OR Acc 1 Acc 1 0 C 0 OR Acc 2 Acc 2 1 C 1 POP dst Pop Word from the Stack Description Pops a single word from the stack SP to the spec...

Page 201: ...acknowledge additional interrupts Status Flags S Z if dst Acc or AP or APC C E if dst PSF Operation dst SP INS 0 Encoding 15 0 1ddd dddd 1000 1101 Example s See POP PUSH src Push Word to the Stack De...

Page 202: ...xxh 0103h SP before RET xxxxh SP after RET xxxxh RET C RET NC RET Z RET NZ RET S Conditional Return on Status Flag Description Performs conditional return RET based upon the state of a specific proces...

Page 203: ...oes not occur RET Z Operation Z 1 IP SP Z 0 IP IP 1 Encoding 15 0 1001 1100 0000 1101 Example s RET Z Z 0 return RET does not occur RET NZ Operation Z 0 IP SP Z 1 IP IP 1 Encoding 15 0 1101 1100 0000...

Page 204: ...atus Flag Description Performs conditional return RETI based upon the state of a specific processor status flag RETI C returns if the Carry flag is set while RETI NC returns if the Carry flag is clear...

Page 205: ...mple s RETI Z Z 0 return from interrupt RETI does not occur RETI NZ Operation Z 0 IP SP INS 0 Z 1 IP IP 1 Encoding 15 0 1101 1100 1000 1101 Example s RETI NZ Z 0 return from interrupt RETI is performe...

Page 206: ...instruction includes the Carry C flag in the circular left shift Status Flags C for RLC only S Z for RLC only RL Operation 15 Active Accumulator Acc 0 Acc 15 1 Acc 14 0 Acc 0 Acc 15 Encoding 15 0 1000...

Page 207: ...RRC instruction includes the Carry C flag in the circular right shift Status Flags C for RRC only S Z for RRC only RR Operation 15 Active Accumulator Acc 0 Acc 14 0 Acc 15 1 Acc 15 Acc 0 Encoding 15 0...

Page 208: ...int at which overflow underflow would occur Status Flags C S Z SLA Operation Carry Flag 15 Active Accumulator Acc 0 0 C Acc 15 Acc 15 1 Acc 14 0 Acc 0 0 Encoding 15 0 1000 1010 0010 1010 Example s Acc...

Page 209: ...shift a copy of the current msb into the accumulator thereby preserving any sign orientation For each shift iteration the accumulator lsb is shifted into the Carry C flag Status Flags C S changes for...

Page 210: ...Acc 15 2 Acc 15 14 Acc 15 C Acc 1 Encoding 15 0 1000 1010 1110 1010 Example s Acc 0003h C 0 Z 0 SRA2 Acc 0000h C 1 Z 1 SRA4 Operation 15 Active Accumulator Acc 0 Carry Flag Acc 11 0 Acc 15 4 Acc 15 1...

Page 211: ...on Because the source is limited to 8 bits the PFX n register is used to supply the high byte of data for 16 bit sources Status Flags C S Z OV SUB Operation Acc Acc src Encoding 15 0 f101 1010 ssss ss...

Page 212: ...ion Acc 15 8 Acc 7 0 Acc 7 0 Acc 15 8 Encoding 15 0 1000 1010 1000 1010 Example s Acc 2345h XCHN Acc 4523h XCHN Exchange Accumulator Nibbles Description Exchanges the upper and lower nibbles in the ac...

Page 213: ...es Status Flags S Z Operation Acc Acc XOR src Encoding 15 0 f011 1010 ssss ssss Example s Acc 2345h XOR A 2 A 2 0F0Fh Acc 2C4Ah Special Notes The active accumulator Acc is not allowed as the src for t...

Page 214: ...21 3 4 UROM_moveDP1 21 6 21 3 5 UROM_moveDP1inc 21 6 21 3 6 UROM_moveDP1dec 21 6 21 3 7 UROM_moveBP 21 7 21 3 8 UROM_moveBPinc 21 7 21 3 9 UROM_moveBPdec 21 7 21 3 10 UROM_copyBuffer 21 8 21 3 11 UROM...

Page 215: ...y 800Dh 2 flashEraseAllEntry romMemory functionTable 2 It is also possible to call utility ROM functions directly using the entry points given in Table 21 1 Calling a function directly will provide fa...

Page 216: ...he page which is being erased 21 2 3 UROM_flashEraseAll Notes If the watchdog reset function is active it should be disabled before calling this function Interrupts are disabled while in this function...

Page 217: ...these functions are executed from utility ROM addresses must be specified correctly to point to the intended memory segments When executing from utility ROM the memory map is illustrated in Figure 21...

Page 218: ...Implemented as move GR DP 0 21 3 3 UROM_moveDP0dec Notes Before calling this function DPC should be set appropriately to configure DP 0 for byte or word mode The address passed to this function should...

Page 219: ...Implemented as move GR DP 1 21 3 6 UROM_moveDP1dec Notes Before calling this function DPC should be set appropriately to configure DP 1 for byte or word mode The address passed to this function should...

Page 220: ...nted as move GR BP OFFS 21 3 9 UROM_moveBPdec Notes Before calling this function DPC should be set appropriately to configure BP OFFS for byte or word mode The address passed to this function should b...

Page 221: ...nction should be based on the data memory mapping for the utility ROM as shown in Figure 21 1 When a byte mode address is used CDA0 must be set appropriately to access either the upper or lower half o...

Page 222: ...g Constant Byte Data from Flash Indirect Function Call INDX_moveDP0inc equ 4 move DPC 1Ch Set all pointers to word mode move DP 0 800Dh Fetch location of function table from Utility ROM move BP DP 0 S...

Page 223: ...her than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time The parame...

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