MagnaChip HMS39C7092, User Manual, Page: 92 / 197

Watchdog Timer Flash MCU(HMS39C7092)
92
The following functions are provided :
•
Selecting the timer mode
•
Selecting the internal clock source
•
Selecting the reset mode
•
Setting the timer enable bit
•
Being enable interrupt request
•
Being enable reset signal occurrence
The clock signals are obtained by dividing the frequency of the system clock.
Table 7.2 Internal Counter Clock Sources
OVERFLOW INTERVAL
CKSEL CLOCK SOURCE
33 MHZ 50 MHZ
000 SYSCLK / 2 15.5 us 10.2 us
001 SYSCLK / 8 62.0 us 40.9 us
010 SYSCLK / 32 248.2 us 163.8 us
011 SYSCLK / 64 496.4 us 327.6 us
100 SYSCLK / 256 1.98 ms 1.31 ms
101 SYSCLK / 512 3.97 ms 2.62 ms
110 SYSCLK / 2048 15.88 ms 10.48 ms
111 SYSCLK / 8192 63.55 ms 41.94 ms
WRSR Reset Status Register ( 0x0900_1104 Read-Only )
b31 - b2 b1 b0
WRSR Reserved ITOVF WTOVF
Reset - 0 0
Initial value : 0x-0 1 : Overflowed
0 : Normal
WTOVF : Watchdog timer overflow flag. Indicates
that the WTCNT has overflowed in the watchdog
timer mode.
ITOVF : Interval timer overflow flag. Indicates that the
WTCNT has overflowed in the watchdog timer
mode.
Two-bit read only register. The WRSR indicates whether WTCNT is overflowed or not.
The WRSR is initialized to 0x0 by the reset signal, Internal RESET .
Bit 0 (WTOVF) indicates that the WTCNT has overflowed in the watchdog timer
mode. Bit 1 (ITOVF) indicates that the WTCNT has overflowed in the interval timer
mode.