MagnaChip HMS39C7092, User Manual, Page: 102 / 197

General Purpose Timer Flash MCU(HMS39C7092)
102
8.2 General Purpose Timer Unit Memory Map
8.2.1 Register Assignment
The base address of the general-purpose timer unit is 0x0900_1300 and the offset of
any particular register from the base address is fixed.
Table 8.1 Timer Global Control Register Map
REG.
I/O
OFFSET
DIR.
DESCRIPTION
TSTARTR
0x1300 R/W Timer Start Register
TSYNCR 0x1304 R/W Timer Sync. Register
TPWMR 0x1308 R/W Timer PWM Mode Register
-
0x130C W (test only)
- 0x1310 R (test only)
- 0x1314 W (test only)
-
0x1318 R (test only)
Table 8.2 Timer Channel Control Register Map
REG.
I/O
OFFSET
DIR.
DESCRIPTION
TCR0 0x1320 R/W Timer 0 Control Register
TIOCR0
0x1324 R/W Timer 0 I/O Control Register
TIER0 0x1328 R/W Timer 0 Interrupt Enable Register
TSR0 0x132C R Timer 0 Interrupt Status Register
TCNT0
0x1330 R/W Timer 0 Counter Register
GRA0 0x1334 R/W Timer 0 General Register A
GRB0 0x1338 R/W Timer 0 General Register B
GP Timer Unit has consists of six unit timer channels and each address starts at
following address
Table 8.3 Timer Channel Starting Address
Timer No. Starting Offsets
Timer 0 0x1320
Timer 1 0x1340
Timer 2 0x1360
Timer 3 0x1380
Timer 4 0x13A0
Timer 5 0x13D0