MagnaChip HMS39C7092, User Manual, Page: 139 / 197

Flash MCU(HMS39C7092) GPIO
139
10.2 GPIO Registers
The following user registers are provided:
P n DR* Port n Data Register. Values written to this read/write register will be input
on port A pins if the corresponding data direction bits are set to HIGH (port
input). Values read from this register reflect the external states of port n,
not necessarily the value should be written to it. All bits are cleared by a
system reset.
P n DDR* Port n Data Direction Register. Bits set in this read/write register will select
the corresponding pins in port n to become an input, clearing a bit sets the
pin to output. All bits are cleared by a system reset.
*n is: A, B, 1, 2, 3, 4, 5, 6, 7, 8 or 9
10.2.1 Register Memory Map
The start address of the GPIO is 0x0900_1600 and the offset of any particular
register from the base address is determined.
Table 10.1 GPIO Register Memory Map
REG.
I/O
OFFSET
DIR DESCRIPTION
PADR 0x1600 R/W 8-bit Port A Data register
PADDR 0X1604 R/W Port A Data Direction register
PBDR 0X1608 R/W 8-bit Port B Data register
PBDDR
0X160C R/W Port B Data Direction register
P1DR 0X1610 R/W 8-bit Port 1 Data register
P1DDR 0X1614 R/W Port 1 Data Direction register
P2DR
0X1618 R/W 8-bit Port 2 Data register
P2DDR 0X161C R/W Port 2 Data Direction register
P3DR 0X1620 R/W 8-bit Port 3 Data register
P3DDR
0X1624 R/W Port 3 Data Direction register
P4DR 0X1628 R/W 8-bit Port 4 Data register
P4DDR 0X162C R/W Port 4 Data Direction register
P5DR
0X1630 R/W 4-bit Port 5 Data register
P5DDR 0X1634 R/W Port 5 Data Direction register
P6DR 0X1638 R/W 8-bit Port 6 Data register
P6DDR
0X163C R/W Port 6 Data Direction register
P7DR 0X1640 R/W 3-bit Port 7 Data register
P7DDR 0X1644 R/W Port 7 Data Direction register
P8DR
0X1648 R/W 5-bit Port 8 Data register
P8DDR 0X164C R/W Port 8 Data Direction register
P9DR 0X1650 R/W 7-bit Port 9 Data register
P9DDR
0X1654 R/W Port 9 Data Direction register