MagnaChip HMS39C7092, User Manual, Page: 81 / 197

Flash MCU(HMS39C7092) Interrupt controller
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6.2 Interrupt Controller Registers
The start address of the interrupt controller is 0x0900_1200 . The offset of any
particular register from the start address is fixed. The following registers are
provided for both FIQ and IRQ interrupt controllers:
Table 6.2 Memory Map of the Interrupt Controller
REG. I/O OFFSET Dir Description
GMR
0x1200 R/W Global Mask Register
TMR 0x1204 R/W Trigger Mode Register
TPR
0x1208 R/W Trigger Polarity Register
IDR 0x120C R/W Interrupt Direction Register
FSR 0x1210 R FIQ Status Register
ISR
0x1214 R IRQ Status Register
FMR 0x1218 R/W FIQ Mask Register
IMR 0x121C R/W IRQ Mask Register
ISCR
0x1220 W Interrupt Status Clear Register
GMR Global Mask Register (0x0900_1200 R/W)
b31 - b21 b20 b19 b18 b17b16 b15b14b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GMR Reserved I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
Reset 0000000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Initial value : 0x01FFFFF Bit field I0-I24 1 : Mask
0 : Unmask
The interrupt mask register is used to mask the interrupt input sources and defines
which active sources will generate an interrupt request to the processor. If certain bits
within the interrupt controller are not implemented, the corresponding bits in the
interrupt mask register must be masked. A bit value 0 indicates that the interrupt is
unmasked and will allow an interrupt request to reach the processor. A bit value 1
indicates that the interrupt is masked. Once a bit is masked, the corresponding bit in
the status register is cleared. On reset, all interrupt input-sources are masked.
TMR Trigger Mode Register (0x0900_1204 R/W)
b31 - b21 b20 b19 b18 b17b16 b15b14b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TMR Reserved I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
Reset 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Initial value : 0x0100000 Bit field I0-I24 1 : Level Trigger Mode
0 : Edge Trigger Mode
The interrupt trigger mode register is used to configure the interrupts with the
interrupt trigger polarity register. Each interrupt can be configured to level or edge
triggered. A bit value 0 indicates that the interrupt is configured to edge triggered and
a bit value 1 indicates that the interrupt is configured to level triggered. On reset, all
interrupt input sources are configured to edge triggered.