MagnaChip HMS39C7092, User Manual, Page: 83 / 197

Flash MCU(HMS39C7092) Interrupt controller
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FSR FIQ Status Register (0x0900_1210 Read Only)
b31 - b21 b20 b19 b18 b17b16 b15b14b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
FSR
Reserved I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
Reset 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Initial value : 0x00000000 Bit field I0-I24 1 : FIQ Pending
0 : FIQ Idle
The FIQ status register is used to reflect the status of all channels set to produce an
FIQ interrupt (IDR n = 1). When an interrupt is set for an FIQ occurring, the
corresponding bit is set in FIQ status register. The interrupt handler will examine this
register to determine the channel(s) that caused the FIQ interrupt. When the status
clear register is written to ë1í, the corresponding bit is cleared if that channel is
configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and
will generate an interrupt to the processor.
ISR IRQ Status Register (0x0900_1214 Read Only)
b31 - b21 b20 b19 b18 b17b16 b15b14b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ISR Reserved I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
Reset 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Initial value : 0x00000000 Bit field I0-I24 1 : IRQ Pending
0 : IRQ Idle
The IRQ status register is used to reflect the status of all channels set to produce an
IRQ interrupt (IDR(i) = 0). When an interrupt is set for an IRQ occurring, the
corresponding bit is set in IRQ status register. The interrupt handler will examine this
register to determine the channel(s) that caused the IRQ interrupt. When the status
clear register is written to ë1í, the corresponding bit is cleared if that channel is
configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and
will generate an interrupt to the processor.
FMR FIQ Mask Register (0x0900_1218 R/W)
b31 - b21 b20 b19 b18 b17b16 b15b14b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
FMR Reserved I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
Reset 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Initial value : 0x00000000 Bit field I0-I24 1 : Disable FIQ
0 : Enable FIQ
The FIQ request mask register is used to mask the request to generate an interrupt
to a processor. If certain bits within the interrupt controller are not implemented, the
corresponding bits in the FIQ request mask register must be masked. A bit value 0
indicates that the interrupt is unmasked and will allow an interrupt request to reach
the processor. A bit value 1 indicates that the interrupt is masked. On reset, all FIQ
requests are unmasked.